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JPH03148143A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03148143A
JPH03148143A JP1286217A JP28621789A JPH03148143A JP H03148143 A JPH03148143 A JP H03148143A JP 1286217 A JP1286217 A JP 1286217A JP 28621789 A JP28621789 A JP 28621789A JP H03148143 A JPH03148143 A JP H03148143A
Authority
JP
Japan
Prior art keywords
bonding pad
bonding
neighboring
ball
dug part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1286217A
Other languages
Japanese (ja)
Inventor
Toshio Noda
野田　利雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1286217A priority Critical patent/JPH03148143A/en
Publication of JPH03148143A publication Critical patent/JPH03148143A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce a bonding pad pitch by providing a rectangular dug part right below a bonding pad which connects a metallic wiring layer with a metallic fine line, and providing two passivation films between it and another and neighboring bonding pad. CONSTITUTION:A rectangular dug part 16, at a silicon substrate 1, and first and second passivation films 14 and 15, between it and a neighboring dug part 16, are provided, whereby solid structure is formed. As a result, if bonding is done, the ball of an Au wire 7 is approximately buried in the bonding pad provided at the dug part 16, so it never expands toward a neighboring bonding pad 3, and in the result the ball size can be made small. Hereby, pad pitch P1 can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

第３図（ａ）　、　（ｂ）は従来の半導体装置のボンデ
ィングパッド部の平面図及びｃ−ｃ’線断面図である。FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along line cc' of a bonding pad portion of a conventional semiconductor device.

シリコン基板ｌの上に絶Ｒ膜２を介してＡｎ等の金属膜
によってボンディングパッド３が形成されており、平面
的には金属配融層５の末端部を装置に設けられている構
造になっている。A bonding pad 3 is formed by a metal film such as An on a silicon substrate 1 via an insulating film 2, and in plan view, the end portion of the metal fusion layer 5 is provided in the device. ing.

Ａｕ１ＩＡ７をボール・ボンディングした時、ボールサ
イズｓ、ＩＩ′ｉ、７０〜９（１ｍであるために、バ。When Au1IA7 is ball bonded, ball size s, II'i, 70-9 (1m, so Ba.

ドビッチＰ！は設計上１００μｍ以下にすることができ
ない。Dobitch P! cannot be made smaller than 100 μm due to design.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のボンディングパッドは、平らなシリコン
基板に平面的に形成されているために、半導体素子の表
面を占める割合が大きいという欠点があった。具体的に
は、通常使用される寸法として、ボンディングパッド・
サイズが、９０〜１２０μｍ１開孔部が７０〜１００μ
ｍ、Ａｕ細線の直径が２５〜４０μｍ１及びそのＡｕ細
線のボンディング後のボールサイズＳ、が７０〜９０μ
ｍとされている。The above-described conventional bonding pads have the disadvantage that they occupy a large proportion of the surface of a semiconductor element because they are formed two-dimensionally on a flat silicon substrate. Specifically, the dimensions commonly used are bonding pads and
The size is 90 to 120 μm and the opening part is 70 to 100 μm.
m, the diameter of the Au thin wire is 25 to 40 μm1, and the ball size S after bonding of the Au thin wire is 70 to 90 μm
It is said to be m.

その為、半導体素子の設計データとして必要なパッドビ
、チＰ、は、どう工夫しても１００μｍを超えてしｌう
ことになる。Therefore, no matter how we try, the pads and chips required as design data for semiconductor devices end up exceeding 100 μm.

なぜなら（パッドピッチ）≧（ボールサイズ）＋（８孔
部〜ボール間の間隔）＋（パッジベージ田ン膜の幅）＝
７０＋１０＋２０＝１００μｍとなるからである。Because (pad pitch) ≧ (ball size) + (distance between 8 holes and balls) + (width of padding membrane) =
This is because 70+10+20=100 μm.

そこで、例えば４００　ｐｉｎの半導体チップを考えた
場合、ボンディングパッドを四周に１列に配置となυチ
ップサイズはどうしても１０ｍｍ角を超えてしまう。Therefore, when considering a 400-pin semiconductor chip, for example, if bonding pads are arranged in one row around the circumference, the chip size inevitably exceeds 10 mm square.

従って、半導体装置が多ピン化するにつれて要求される
ボンディングパッド数の増大に追いついていけなくなっ
てくるという重大な問題がある。Therefore, there is a serious problem that it becomes impossible to keep up with the increase in the number of bonding pads required as semiconductor devices increase in number of pins.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、金属配線層と金属細線を接続す
るボンディングパッドの直下に矩形の掘り込み部が設け
られ、隣接する別のボンディングパッドとの間に少くと
も２つのパッジページ璽ン膜を設けたことを特徴とする
。In the semiconductor device of the present invention, a rectangular recessed portion is provided directly below a bonding pad that connects a metal wiring layer and a thin metal wire, and at least two pad page films are provided between the bonding pad and another adjacent bonding pad. It is characterized by having been established.

〔実施例〕〔Example〕

次に、実施例について図面を参照して説明する。 Next, examples will be described with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ電断面図である。FIGS. 1(a) and 1(b) are a plan view and an A-A electric cross-sectional view of an embodiment of the present invention.

シリコン基板１に掘夛込み部１６と、新たに第１パツジ
ベージｌン膜１４を加えてちゃ、立体的な構造になって
いる点が従来と異なっている。It differs from the conventional method in that it has a three-dimensional structure by adding a recessed portion 16 and a new first package substrate film 14 to the silicon substrate 1.

第２図（包（ｂ）は第１図に示す実施例にボンディング
を行った後の状態を示す。FIG. 2 (b) shows the state of the embodiment shown in FIG. 1 after bonding.

Ａｕ線７のボールはａ＋ｂ込み部１６を設けたボンディ
ングパッド３にほぼ埋まってしまうため、隣接するボン
ディングパッド３の方向へ拡がることがなく、結果的に
ボールサイズＳ１を小さくでき、パッドピッチＰ１も小
さくて済むことになる。Since the ball of the Au wire 7 is almost buried in the bonding pad 3 provided with the a+b recessed part 16, it does not spread toward the adjacent bonding pad 3, and as a result, the ball size S1 can be reduced, and the pad pitch P1 can also be reduced. It ends up being small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、ボンディングできる効
果がある。As explained above, the present invention has the advantage of enabling bonding.

更に、Ａｕ線のボール部がボンディングパッドにほぼ埋
設されるため、半導体チップ表面で局在する応力を減ら
すこと及びボール部とボンディングパッド間の接着力が
増すという効果もある。Furthermore, since the ball part of the Au wire is almost buried in the bonding pad, there are also effects of reducing localized stress on the surface of the semiconductor chip and increasing the adhesive force between the ball part and the bonding pad.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）　、　（ｂ）は本発明の一実施例の平面図
及びＡ−Ａ’線断面図、第２図（ａ）　、　（ｂ）は第
１図に示す実施例にボンディングを行った後の状態を示
す平面図及びＢ−Ｂ’線断面図、第３図（ａ）　、　（
ｂ）は従来の半導体装置のボンディングパッド部の平面
図及びＣ−Ｃ′線断面図である。 １・・・・・・シリコン基板、２・・・・・・絶縁層、
３・・・・・・ボンディングパッド、４・・・・・・バ
ッジベージ璽ン膜、５・・・・・・金属配線層、６・・
・・・・開孔部、７・・・・・・Ａｕ線、１４・・・・
・・ｇｉパッジベージ璽ンＪｉ、１５・・・・・・第２
パ、シベーシ冒ンＬｘ６・・・・・・掘り込ミ部。FIGS. 1(a) and (b) are a plan view and a cross-sectional view taken along the line A-A' of an embodiment of the present invention, and FIGS. 2(a) and (b) show bonding in the embodiment shown in FIG. A plan view and a sectional view taken along the line B-B', and Fig. 3(a), (
b) is a plan view and a sectional view taken along the line CC' of a bonding pad portion of a conventional semiconductor device. 1... Silicon substrate, 2... Insulating layer,
3... Bonding pad, 4... Badge page seal film, 5... Metal wiring layer, 6...
...Opening part, 7...Au wire, 14...
・・gi pudgebage seal Ji, 15・・・・・・2nd
Pa, Shibeshi Encyclopedia Lx6...Digital Mibu.

Claims (1)

【特許請求の範囲】[Claims] 　金属配線層と金属細線を接続するボンディングパッド
の直下に矩形の掘り込み部が設けられ、隣接する別のボ
ンディングパッド部との間に少くとも２つのパッシベー
ション膜を設けたことを特徴とする半導体装置。A semiconductor device characterized in that a rectangular recessed portion is provided directly below a bonding pad that connects a metal wiring layer and a thin metal wire, and at least two passivation films are provided between the bonding pad and another adjacent bonding pad. .
JP1286217A 1989-11-02 1989-11-02 Semiconductor device Pending JPH03148143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1286217A JPH03148143A (en) 1989-11-02 1989-11-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1286217A JPH03148143A (en) 1989-11-02 1989-11-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03148143A true JPH03148143A (en) 1991-06-24

Family

ID=17701491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1286217A Pending JPH03148143A (en) 1989-11-02 1989-11-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03148143A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3036688A4 (en) * 2013-08-23 2017-05-17 Fingerprint Cards AB Connection pads for a fingerprint sensing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3036688A4 (en) * 2013-08-23 2017-05-17 Fingerprint Cards AB Connection pads for a fingerprint sensing device

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