JPH03144842A - Data transfer controller - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by transferring the data read out of a transferer and put on a data bus directly to a transferee without fetching the data. CONSTITUTION:The address latch circuits 18 and 20 are connected between the transferer and transferee devices 14 and 16 and an address bus 10 respectively. Then both circuit 18 and 20 latch the address signals to be sent to the transferer and the transferee respectively for simultaneous execution of a data reading or outputting operation of the transferer and a data writing or inputting operation of the transferee. Furthermore the data outputted onto a data bus 12 from the device 14 are not fetched once by a controller but transferred directly to the device 16 via the bus 12. In such a constitution, the time required for a data transfer cycle is shortened and the data can be transferred at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for transferring data without using a CPU.

[Prior Art] A method of transferring data between memories or between a single memory and an input/output device without going through a CPU is called DMA (Direct Memory Access), and is used for high-speed data transfer and image processing. It is often used for data transfer, etc.

FIG. 3 shows the timing of inter-memory data transfer by a conventional DMA controller. The DMA controller is
First, an address signal and a read control signal are given to the transfer source memory to read data Dk onto the data bus, and store it in its own register. Next, an address signal and a write control signal are given to the transfer destination memory, and the above-mentioned data Dk is output from the register onto the data bus, so that the data Dk is written into the transfer destination memory.

[Problems to be Solved by the Invention] As described above, data transfer by a conventional DMA controller involves reading data from the transfer source memory (or input/output device), importing it into itself, and then Data is sent onto the data bus and written to the destination memory (or input/output device), and the time required for the data transfer cycle increases as the DMA controller takes in and outputs the data. was.

The present invention has been made in view of such problems, and is a data transfer control device that achieves high-speed data transfer by directly transferring data read from a transfer source onto a data bus to a transfer destination without importing it. The purpose is to provide

[Means for Solving the Problems] To achieve the above object, the data transfer control device of the present invention includes a first address latch means connected between a first device and an address bus; a second address latch means connected between the second device and the address bus; and a first address latch means for latching an address for the first device to transfer data from the first device・At the same time as outputting on the bus,
and control means for causing the second address latch means to launch the address for the device to input the data on the data bus to the second device.

[The action control means first sends out an address signal for the transfer source (first) device onto the address bus, and activates the first latch means. It also activates a control signal for data transmission or output to the transfer source device. As a result, with the address signal latched by the first latch means, the transfer source device performs successive read or output operations, and data is output onto the data bus.

During such a data read or output operation of the transfer source, the control means sends out an address signal for the transfer destination (second) device onto the address bus, activates the second launch circuit, and also activates the second launch circuit. Activate control signals for data writing or input to the transfer source device. As a result, while the address signal is latched in the second latch circuit, a write or input operation is performed in the transfer destination device, and the above data currently on the data bus (output from the transfer source) is data) is written or input to the destination device.

As described above, in the present invention, the transfer source address signal and the transfer destination address signal successively outputted from the control means are latched in the first and second launch circuits, respectively, and the transfer source address signal and the transfer destination address signal are latched by the first and second launch circuits, respectively. The previous data write or input operation is performed simultaneously, and the data output from the transfer source device onto the data bus is transferred as is to the transfer destination device.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 shows the main configuration of a computer system to which a data transfer control device according to this embodiment is applied.

According to this embodiment, an address latch circuit 1 is provided between the address bus 10 and the two memories 14 and 18, respectively.
8.20 is connected. Both memory 14.18 and data
The bus 12 is directly connected as usual. And DMA
A control circuit 22 is provided to perform the following. The address terminal A of this control circuit 22 is connected to the address bus 10, the latch control terminals Ll and L2 are connected to the latch circuit 18.20, and the successive control terminals R1 and R2 are connected to the memory 1J14.1, respectively.
The read control terminals R1 and R2 of No. 6 are connected to write control terminals.

The punishment is written to the write control terminal W1. of the memo U14.16 respectively. W
Connected to 2. The control circuit 22 is also supplied with a system clock CLK, and exchanges control signals C1 and C2 regarding the right to use the bus and the like with the CPtJ24.

Next, referring to FIG. 2, the operation of inter-memory data transfer using DMA in this system will be explained.

This example is a data transfer in which a cycle of transferring one piece of data from the memory 14 to the memory 1e is repeated a predetermined number of times.

During this data transfer cycle, the control circuit 22 sets the successive control signal disconnection to the active level "L" for the transfer source memory 14, and sets the write control signal to the transfer destination memory 16 at an active level. ] is set to the active level "L".In one cycle, the control circuit 22
First, an address signal A1 for successive data output to the transfer source memory 14 is sent onto the address bus 10, and a latch control signal Ll is applied to the latch circuit 18 (FIGS. 2(B) and 2(C)). As a result, the address signal AI is latched by the latch circuit 18, and the launch circuit 18
is applied to the address terminal A of the transfer source memory 14 from the output terminal of the transfer source memory 14. As a result, a read operation is performed in the memory 14, data D1 is read from the memory address specified by the address signal AI, and the data D1 is read from the data terminal.
I is output on the data bus 12 (FIG. 2(G))
.

While the above read operation is being performed in the transfer source memory 14, the control circuit 22 sends an address signal An for data writing to the transfer destination memory 18 onto the address bus 10, and performs launch control. A signal L2 is given to the latch circuit 20 (FIGS. 2(B) and (E)).

As a result, the address signal An is latched by the latch circuit 20 and applied to the address terminal A of the transfer destination memory 16. As a result, a write operation is performed in the memory i6, and the above data DI currently on the data Φ bus 12 is written to the memory address specified by the address signal An. This completes one data transfer cycle.

In this embodiment, address bus 10 and memory 14.1
Address latch circuits 18 and 20 are respectively provided between the 8 and 8, and these latch circuits 18 and 20 simultaneously latch the address signal for data read and the address signal for data write, and perform the read operation and the data write operation of the source memory. Write operations to the transfer destination memory are performed simultaneously. The data read from the transfer source memory onto the data bus 12 is not once taken into the control circuit 22, but the data is written directly from the data bus 12 to the transfer destination memory. Therefore, one cycle of data transfer is significantly shorter than in the conventional method (FIG. 3), and the data transfer speed is significantly improved.

Note that when the memory 16 is the transfer source and the memory 14 is the transfer destination, the operations are the same except that both memories replace each other. Furthermore, although this embodiment concerned data transfer between two memories 14 and 18, data transfer between an input/output device and memory, and between an external device (memory or peripheral device) and memory is also possible. The present invention can be applied in the same way as above.

[Effects of the Invention] By having the above-described configuration, the present invention provides the following effects.

An address latch circuit is connected between the transfer source device and the transfer destination device and the address bus, and these latch circuits latch the address signal for the transfer source and the address signal for the transfer destination, respectively. The output operation and the data write or input operation of the transfer destination are performed simultaneously, and the data output from the transfer source device onto the data bus is transferred directly from the data bus to the transfer destination device without being imported into the control device. Since the data is transferred, the time required for the data transfer cycle can be shortened and the data transfer speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main configuration of a computer system to which a data transfer control device according to an embodiment of the present invention is applied. FIG. 2 explains the operation of inter-memory data transfer using DMA in the embodiment. FIG. 3 is a timing diagram for explaining the operation of inter-memory data transfer by a conventional DMA controller. 10... Address bus, 12... Data bus, 14... First device (memory), 16...
Second device (memory), 18...first address latch means (latch circuit), 20...second address latch means (latch circuit), 22...control means ( control circuit).

Claims (1)

[Claims] A control device for transferring data from a first device to a second device via a data bus, comprising: a control device connected between the first device and an address bus; a first address latch means; a second address latch means connected between the second device and the address bus; At the same time, the address for the second device is latched by the second address latch means to output data from the first device onto the data bus. A data transfer control device comprising: control means for inputting the data to the second device.