JPH03144744A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent a CPU from running away and to reduce the malfunction of a system by providing a microcomputer with a runaway monitoring circuit. CONSTITUTION:There are two cases for outputting a reset signal 11 from the runaway monitoring circuit 5 to the CPU 1. When a ROM chip select signal 13 is non-active, a memory read signal 8 is active and a CPU status signal 10 is in an operation code fetching cycle in the 1st case, the CPU 1 is reset if addresses are not in a ROM area though the CPU 1 is in the operation code fetching cycle. If the CPU 1 tries to write data in the ROM 4 when both of the ROM chip select signal 13 and memory write signal 8 are active in the 2nd case, the CPU 11 is reset. Consequently, the system can be prevented from generating malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer having a CPU, memory, and other peripheral circuits.

[Prior art] Figure 2 shows a conventional central processing unit (hereinafter referred to as cPU).
In Figure 0, which is a block diagram of a microcomputer having memory and peripheral circuits, 1 is a CPU, 2 is an address decoding circuit, 3 is a RAM, 4 is a ROM, 6 is a data bus, 7 is an address signal, and 8 is a memory read. ” words,
9 is a memory write signal, 12 is a RAM chip select signal, and 13 is a ROM chimp select signal.

In a conventional microcomputer having a CPU, a memory, and a peripheral circuit, when the CPU accesses the ROM 4, an address signal 7 specifying an address and a memory read signal 8 are output from the CPU 1 to the ROM 4. At this time, the address decode circuit 2 decodes the address signal 7, creates a ROM chip select signal 13, and R
When a signal of 0 or more is input to the ROM 4, the data at the designated address is output to the CPU 1 through the data bus 6.

On the other hand, when the CPUI accesses the RAM 3, an address signal 7 specifying the address and a memory read signal 8
Alternatively, the memory write signal 9 is output from the CPU 1 to the RAM 3. At this time, in the address decoding circuit 2,
It decodes the address signal 7, creates a RAM chip select signal 12, and outputs it to the RAM 3. The above signal is RA
When input to M3, data at the specified address is output to the CPUI through the data bus 6 when reading memory.
At the time of memory write, data from CPU 1 is stored at the specified address.

[Problem to be solved by the invention]

Conventional CPUs, memories, and peripheral circuits are configured as described above, so if the CPU goes out of control, it may read or write incorrect data, resulting in system malfunctions or memory destruction. there were.

This invention was made in order to solve the problems of the conventional ones as mentioned above, and when the J'CPU goes out of control, the CPU
The object of the present invention is to obtain a microcomputer having a runaway monitoring circuit that resets U.

[Means to solve the problem]

The microcomputer according to the present invention includes a runaway monitoring circuit that monitors the output from the CPU, and when it is determined that the CPU is running out of control, outputs a reset signal to the CPU.

[Effect]

The runaway monitoring circuit according to the present invention resets the CPU when the CPU accesses the ROM, when the address runs outside the ROM eI area, and when the address runs outside the RAM area in a memory write cycle.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a microcomputer according to an embodiment of the present invention, and in the figure, 1 to 4.6 to 9 degrees and 12.13 are exactly the same as the conventional circuit.

5 is a runaway monitoring circuit, 10 is a CPU status signal, 11
is a CPU reset signal.

FIG. 3 shows an example of the runaway monitoring circuit shown in FIG. 1. In the figure, 51 is a two-man power NOR circuit, 52 is a two-man power OR circuit, 53, 54 is an inverter, 55 is a four-man power NOR circuit, and 56 is a D Flip-flop, 57 is a buffer, 58
is a two-person AND circuit. Further, 10a is a halt signal, 10b is a LIBI signal, IMBK is a boat switching signal, and PWRP is a power-on reset signal.

In the CPU and memory peripheral circuit configured as described above, when cput is operating normally, the operation is the same as before. In order to monitor CPUI runaway, the runaway monitoring circuit 5 receives a memory read signal 8. Memory write signal9.
CPU status signal 10. A ROM chip select signal 13 is input.

There are two cases in which the runaway monitoring circuit 5 outputs the reset signal 11 to the CPUI. First, in the first case, the ROM chip select signal 13 is inactive,
When the memory read signal 8 is active and the CPU status signal 10 indicates an opcode fetch cycle, and the CPU is in an opcode fetch cycle but the address is not running in the ROM fiJf area, reset the CPUI.0 Next, in the second case, when both the ROM chip select signal 13 and the memory write signal 8 are active and the CPU attempts to write data to the ROM 4, the CPU 11 is reset.

In the above embodiment, the runaway monitoring circuit is configured with hardware, but it is also possible to provide a board with software.
It is also possible to use the runaway monitoring circuit by turning it ON only when it is desired to use it, using the switching signal IMBK shown in FIG.

Further, although the above embodiment shows a case where runaway related to memory is monitored, runaway related to other peripheral circuits may be monitored, and the same effects as in the above embodiment can be obtained.

(Effects of the Invention) As described above, according to the present invention, since a runaway monitoring circuit is provided in a microcomputer having a CPU, memory, and peripheral circuits, runaway of the CPU can be prevented and system malfunctions can be reduced. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention, FIG. 2 is a block diagram of a microcomputer having a conventional CPU and memory peripheral circuit, and FIG.
The figure shows an example of the configuration of the runaway monitoring circuit shown in FIG. 1. ■...CPU, 2...Address decoding circuit, 3.
...RAM, 4...ROM, 5...runaway monitoring circuit,
6...Data bus, 7...Address signal, 8...
Memory read signal, 9...Memory write signal, 10.
...CPU status signal, 11...CPU reset signal, 12...RAM chip select signal, 13...
・ROM chip select signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A microcomputer equipped with a central processing unit, a memory such as ROM or RAM, and a peripheral circuit, characterized in that the microcomputer is equipped with a runaway monitoring circuit that monitors runaway of the CPU and resets it. .