JPH03144701A - Fuzzy controller and its operating method - Google Patents

Abstract

PURPOSE:To attain rapid fuzzy inference processing by providing the fuzzy controller with a membership function memory for outputting a truth value corresponding to the input data supplied from an input register and an arithmetic circuit for executing fuzzy operation between plural truth values outputted from membership functions in each rule. CONSTITUTION:The codes of subrules are formed by using codes indicating the input variables of an antecedent part in each rule and codes indicating membership functions, then stored in a rule memory 21 in a fixed order. Then input data stored in an input register 22 are selected by the codes indicating the input variables included in the codes of the subrules. On the other hand, data indicating plural kinds of membership functions in each input variable are previously stored in the membership function memory 23 and one membership function is specified by the code indicating the input variable included in the subrule code and the code indicating the membership function. Thus, rapid inference can be attained.

Description

[Detailed description of the invention] Read sub-rules from the invention's summary rule memory in a fixed order. By that sub-rule. Specifies the membership function in the membership function memory and reads the value of the input variable in the 9-input register. A truth value is obtained by applying the read input variable to the membership function. A truth value calculation is performed between subrules belonging to one rule. Reading subrules from rule memory. The output of the truth value from the membership function memo and the operation of the truth value are executed sequentially by pipeline processing for each subrule.

BACKGROUND OF THE INVENTION This invention relates to fuzzy controllers and methods of operation thereof.

Processing using fuzzy theory, which is referred to by various terms such as fuzzy inference processing and fuzzy control, is in the spotlight, and dedicated hardware architectures for fuzzy inference are also being developed. This hardware is called a fuzzy inference device, a fuzzy control device, a fuzzy computer, a fuzzy controller, etc.

Fuzzy inference is typically If. This is done according to the Modus-Bonens inference format called the then rule. This rule uses the antecedent part starting with 1r and the antecedent part starting with 1r.
It consists of the consequent part which is received by hen.

Generally, the antecedent part includes multiple input variables and is often relatively complex, so even if a dedicated hardware architecture is used, it is relatively time consuming.

Summary of the Invention This invention provides a fuzzy
The purpose is to provide a controller and its operating method.

The fuzzy controller according to the present invention has a rule memory that stores subrules that are decomposed and coded for each input variable in a fixed order.

An input register that temporarily stores input data for each input variable, multiple types of membership functions that are stored in advance, and sub-registers that are read from the rule memory, and membership functions specified by the rules from the input registers. It includes a membership function memory that outputs truth values corresponding to given input data, and an arithmetic circuit that performs fuzzy operations for each rule between the truth values output from the membership functions.

According to the operating method of the fuzzy controller according to the present invention, the code of the sub-rule is formed using the code representing the input variable of the antecedent part of the rule and the code representing the membership function, and the food of this sub-rule is arranged in a certain order. The above rule is stored in the memory. Then, the input data stored in the input register is selected by the code representing the input variable included in the code of the sub-rule. In addition, data representing multiple types of membership functions for each input variable is stored in the membership function memory in advance, and the code representing the input variable and the code representing the membership function included in the code of the sub-rule are unified. Specify one membership function.

As described above, according to the present invention, it is possible to read sub-rules from the rule memory, read truth values from the membership function memory, and perform fuzzy operations between truth values by so-called pipeline processing. , the execution speed of fuzzy inference becomes faster, and high-speed inference becomes possible.

Explanation of Example Overall configuration of fuzzy controller and i of fuzzy inference
FIG. 1 shows the overall structure of the fuzzy controller. The fuzzy controller is the control unit 11. It is composed of a fuzzy inference section 12 and an AD/DA conversion section 13, and these sections 11, 12, and 13 are interconnected by a digital ◆ bus 14 via a suitable interface.

The control unit 11 includes a microprocessor that controls the overall operation of the fuzzy controller, a ROM that stores its execution program, and a RAM that stores various data. The control unit If also performs comprehensive calculation and definite value calculation (for example, centroid calculation) using the fuzzy inference results. If necessary, input/output devices such as a keyboard and a CRT display device are connected to the control unit U.

The fuzzy inference unit 12 includes a rule memory 21. Input register 22, membership function memory 2B, KIN circuit 24, MAX
Circuit 25. It includes a timing control circuit (as shown), etc., and performs predetermined fuzzy inference calculations.

The AD/DA converter 13 includes an AD converter that converts an analog input into a digital signal and a DA converter that converts a digital output into an analog output signal. In this example, the number of input variables is four.

The number of output variables is three.

As will become clear later, the fuzzy controller of this embodiment has eight input variables (xl, x2.x3 .
x4. x5. x6. x7 and x8). Any specified four of these eight input variables can actually be taken into the AD/DA converter 13, and control rules for the specified four input variables are set. It is possible. The three output variables are denoted yl, y2 and y3.

FIG. 2 shows an example of a membership function.

In this example, membership functions NL, NM of class 78
, NS, ZR, PS, PM and PL are used. The meanings of these membership functions are as follows.

NL: Negative Large: Large negative value NM: Negative McdluII:
Negative medium value N S : Negative Small
l : Negative small value Z R : Zero : is °bo zero P S : Po5itive Small : Positive small value P M : Po5itive Medium :
Positive medium value PL: Po5itive Large
e: The large positive value NL-PL is called the label of the membership function.

The membership function is not limited to a triangular shape as shown in the m2 diagram, but can be set to any shape.

FIG. 3 shows an example of a singleton representation of a membership function. Such a singleton is particularly suitable for expressing a fuzzy set of consequents in a rule, and in that case, comprehensive operations and definite value operations become extremely easy.

The rules for fuzzy control are II', then (
If..., then...) is expressed in the form. Of the eight input variables, xi, x3. Assuming that x5 and X7 are selected, an example of a rule for output y1 using these input variables will be shown below.

(Rule 1) l(' xl is NS, x3 Is PS
, x5 is ZRand x 7 Is
NS, then y 1 is NL This is simplified and expressed as follows.

(Rule 1) xi-NS, x3-PS, x5-ZR.

x 7 = N S 4y 1
- N Lxl=Ns-x7-NS is the antecedent part, yl
-NL is called the consequent part. Below, examples of three rules will be shown in the same way.

(Rule 2) x3-PM, x7-NS, x5 Hall PM.

xl=PL-eyl-NM(
Rule 3) xi-NL, x3-NS, x5-PL →y 1 ■PL (Rule 4) x5=NL, x3-ZR, x7-PM.

xi-NS -yl-=PL Although the order of the input variables is not constant in the above, there is no particular problem in the processing in the fuzzy inference unit 12, which will be described in detail later.

The fuzzy inference process for Rule 1 is shown in FIG.

The goodness of fit (this is called a truth value) al of the input X1 with respect to the membership function NS is determined.

Similarly, input x3 in the membership functions PS, ZR, NS. x5. Truth value of x7 a3゜a5. a7 is required.

Next, these truth values al, a3. M of a5 and a7
An I N operation (select the smallest) is performed. Let the calculation result of M I N l be aNL.

MIN between the membership function NL of the consequent part in rule 1 for output y1 and the MIN calculation result aNL
A computation (truncation) is performed to obtain the membership function SNL shown with diagonal lines in FIG.

Fuzzy inference is similarly performed for Rule 2 as well.

The membership functions of the consequent parts of Rule 3 and Rule 4 are both PL. Therefore, in such a case, rule 3
A MAX operation L2 (selecting the larger one) between the inference result a of the antecedent part of rule LI and the inference result a of the antecedent part of rule 4 is performed. The result of this MAX operation is set as a, and the L MIN operation between aPL and PL is performed to obtain results S and L.

Inference results S, S for each rule obtained in this way
The MAX operation of S is NL NM' shown in Figure 5.
PL The final inference result is obtained. By defuzzifying this final inference result (which is fuzzy) (e.g. by centroid calculation),
A definite value W is obtained. This determined value W will be output as the output y1.

When the membership function of the consequent part is a singleton, the definite value W is obtained by the following equation.

PL -P-L W-Σ k ・a, /Σ at 1・NL 111-NL kl is the singleton weighting coefficient 1-NL-PL The fuzzy inference unit 12 uses the MIN operation result a 1 (1-N
A calculation process (this is referred to as fuzzy inference process in a narrow sense) is performed to obtain L-PL. The subsequent arithmetic processing (referred to as comprehensive arithmetic and fixed value arithmetic processing) is executed by the control unit 11.

Creating rule code Each rule is decomposed into as many subrules as there are input variables.

For example, if Rule 1 above is decomposed into four sub-rules as follows.

xi-NS -" yl-NL x3-PS -yl-NL x5-ZR→yl-NL・It is called a code.

Figure 9 shows how the four rules (rules 1 to 4) described above (shown in Figure 8) regarding the output variable y1 are each broken down into sub-rules, converted into rule codes, and arranged in a certain order. As shown in the figure. “
``rule code, etc.'' will be stored in the rule memory 21 of the fuzzy inference section 12, which will be described later.

In this way, a large number of rules are arranged in a certain order.
A first-order method is adopted to represent a set of bit rule codes.

(1) Form a block for each output variable. That is,
A set of rules (rule code) for the output variable y1 is set in block 1. A set of rules for the output variable y2 is set as block 2. Let block 3 be a set of rules for output variable y3.

A block flag (8 bits) indicating the number of the block is placed at the beginning of the set of rule codes.

(2) The membership functions of the consequent part are NL and NM.

Rules (subrules) are arranged in the order of NS, ZR, PS, PM, and PL.

(3) For membership functions NL-PL of the consequent part for which no rules exist, insert null rules. This empty rule has an input variable of X8 and a membership function of the antecedent part of N8. The membership function N8 always takes a value of 0.

For example, among rules 1 to 4 shown in FIG. 8, there are no rules whose consequent parts are NS, ZR, PS, and PM. Therefore, these membership functions NS, ZR,
For PS and PM, empty rules x8-N8 (4 empty sub-rules) are set in the consequent part. Due to this.

The arrangement order of the rules is always as shown in (2) above.

(4) The number of sub-rules constituting each rule is always a constant number (four in this embodiment).

Four subrules are generated from each of the above rules 1, 2, and 4. However, rule 3 only yields three subrules. Then there is one empty (Null)
) subrules are added to bring the number of subrules to 4.

In this case, in the empty subrule, the input variable is xl and the membership function is N1 (xl-Nl). It is assumed that the membership function N1 always takes a value of 1.

Regarding the empty rules, four empty sub-rules x8-N8 are each created as described above.

(5) Change the format of the 8-bit rule code to 6th.
As shown in the figure. That is, among the codes D7 to DO, D7 is a label flag and D6 is a rule flag. In addition, input variables X1 to X are input using 3 bits D5 to D3.
8, and the label N of the antecedent part is represented by 3 bits D2 to DO.
Represents L-PL (and Nl, N8). Input variable X1
.about.x8 and the codes (3 bits) assigned to the labels NL-PL, Nl, and N8 of the antecedent part are shown in FIG.

The label flag D7 is set to "1" at a location where the membership function of the consequent part arranged in a certain order according to the rule shown in (2) above changes. That is, it is set to "1" only in the code of the first subrule among the four subrules that have the same consequent label (for example, subrule No. 2. 6. A in FIG. 9).
E, 12.16° LA).

Rule flag D6 indicates rule flags arranged in a fixed order.
Set to l'' where the rules of the code change.

In other words, it is set to "1" only in the code of the first subrule among the subrules belonging to one rule (
For example, sub-rule No. 2.6 in FIG. A,
E, 12.1B, IA and 1E). In Figure 9, there are two rules whose consequent is labeled PL (Rule 3
Since there is a rule 4), the sub-rule number is D7 in the IA rule code. Note that both D6 are 1°, but only D6 is 1'' in the rule code of sub-rule No. and IE.

Flag D7. D6 applies similarly to empty rules.

However, code D5. D4. D3 and D2. D
I, Do are specific codes in the empty subrule, in this example xl or x8 (0
00 or 1ll) and N1 or N8 (both 11
1).

(6) Rules for configuring one flock ◆ Place a start flag and an end flag before and after the code set, respectively. In this example, the start flag is ooooottt and the end flag is 11100111.

In FIG. 9, sub-rule numbers are also assigned to these start flags and end flags.

This is for managing all codes and is not an essential matter. Furthermore, in FIG. 9, a code indicating the number of subrules is inserted between the block flag and the start flag. When the reading of the same number of rule codes (including start flags and end flags) from the rule memory 21 as the number of sub-rules is completed, processing for one block is completed.

Returning to FIG. 1, this fuzzy controller has two modes: a program mode and an operating mode.

In the program mode, membership functions are input and set, rules are input and set, and the like. Data representing a membership function input from an input device such as a keyboard is set and stored in the membership function memory 23 of the fuzzy inference section 12 from the control section 11. Similarly, rules input using an appropriate language or code from an input device are temporarily stored in the RAM in the control unit 11.

It is converted into a rule code as shown in FIG. 9 through the rule code creation process by the CPU.

It is stored in the rule memory 21 within the fuzzy inference section 12.

FIGS. 10a and 10b show the procedure of the rule code creation process.

First, in FIG. 10a, the rule of block N081,
In other words, the process starts with the output variable y1 (
Step 101). If a rule has been input and set for output variable y1 (No in step 102), a block flag (00000001 as shown in FIG. 9 for block 1) is set (step 10).
3). Subsequently, the number of sub-rules (including empty sub-rules and start and end flags) derived from the input and set rules is calculated and set (step 104).

Furthermore, a start flag is set (step 105).
, the process moves to the rule code creation routine shown in FIG. 2 (step 106). When all the rule-codes of block 1 have been created by this routine, an end flag is finally set (step 107).

If a rule for the output variable y1 has not been input or set (YES in step 102), the processes in steps 103 to 107 described above are skipped.

In this example, the number of output variables is three.

The processing of steps 102 to 107 is repeated three times. That is, the process returns to step 102 via steps tag and 109, and the process is repeated until the creation of the rule code for output variable y3 is completed.

In the rule code creation routine of FIG. 10b, processing starts with the first label NL in the arrangement order (step 111), and first, label flag D7 is set to "
1" (step 112). Since multiple rules may be set for one type of label (as in rule 3.4 for label PL described above), the first rules are imported and the rule flag D6 is set to "1" (step 1).
14).

As mentioned above, since the membership functions (labels) of the consequent part need to be arranged in a certain order (starting with NL and ending with PL), the rule code must also be created in that order.

Therefore, it is checked whether the labels of the rules to be processed now are in that order (step 115).
.

If the labels follow a certain order, the first one in the rule
The second sub-rule is fetched (step 116) and it is checked whether it is an empty sub-rule (step 118). If the subrule is not an empty subrule, the input variables and labels of the antecedent part of the subrule are coded according to the code assignment shown in FIG.
t). In the case of empty subrules, D5 to DO are 0 (10
111 (step ll9). Step 1
The processes 17 to 119 are performed for all subrules in one rule (steps 120, 12
1).

Further, the processing in steps 114 to 121 described above is as follows.

This is repeated for all rules in one type of consequent label (steps 122 and 123).

If no rule is input or set for the consequent label, it is an empty label, so four empty rule codes 111111 are set (steps 124 and 1).
25).

The processes of steps 112 to 125 are sequentially executed for all labels in a fixed order (steps 128 and 1.27). And the last label PL
When the rule code creation for is completed, this routine is skipped and the process moves to step 107 in FIG. 10a.

Fuzzy Inference Operation Next, the details of the fuzzy inference operation in the fuzzy controller will be explained.

As described above, the fuzzy inference section 12 executes fuzzy inference processing in a narrow sense, and the control section 11 executes comprehensive calculation and definite value calculation processing, but the processing in both sections 11 and 12 is performed in parallel.

The situation is shown in FIG. This is an example where there is one output variable.

The AD-converted input data from the AD/DA converter 13 (
xi, x3. x5. x7, etc.) is taken in under the control of the CPU of the control unit 11, and this is input to the input register 2 of the inference unit 12.
Written to 2. The input data in the input register 22 is held until the fuzzy inference processing in a narrow sense regarding it is completed.

Thereafter, the fuzzy inference unit 12 performs fuzzy inference processing in a narrow sense using the input data held in the input register 22. In parallel, the control unit 11 calculates the result (a) obtained by the fuzzy inference unit 12 in the previous cycle.
: 1-NL-PL) is used to perform comprehensive calculation and definite value calculation processing, and the final result is output. Generally, the inference processing in the inference unit 12 takes more time than the calculation processing in the control unit 11, so the control unit 11
Wait until the inference process in .

This completes one cycle of operation, and the control unit 11 and inference unit 12
Then, the process proceeds to the writing process of the next AD conversion data to the acquisition 1 input register.

FIG. 12 shows the flow of fuzzy inference processing in a narrow sense by the fuzzy inference unit 12 in FIG. 11. Since processing is performed based on the rule code as shown in FIG. 9, a signal based on the start flag is first output. Subsequently, fuzzy inference processing is performed on the label NL, and a signal based on the label flag is output at the start of the fuzzy inference processing. When the fuzzy inference processing for the label NL is completed, the inference result a is output, and this aNL is taken into the control unit L11. Subsequently, fuzzy inference processing for label NM is performed in the same manner. When the processing for the label PL is completed, a signal based on the end flag is output.

Start flag, end flag, label flag.

The control unit 11 sends a signal based on the rule flag to the inference unit 12.
or manage the inference result a1(t -N'L~PL)
It is used for timing control, etc. in the inference unit 12.

FIG. 13 shows a specific example of the configuration of the fuzzy inference section 12. FIG. 14 is a time chart showing the operation timing of the circuit shown in FIG. 13. In FIG. 13, a timing circuit and a timing signal.

and circuits (buses, gate circuits, control signals, etc.) for writing the rule code into the rule memory 21 and for writing data representing the membership function into the membership function (MSF) memory 23. Illustration is also omitted. In FIG. 14, inference regarding one subrule is performed during one period T of the clock signal QO. Fuzzy inference is executed by so-called vibe line processing, and the timing signals for this are CA and CB.

Shown as CC, CD, CE.

Referring to these figures, rule memory 21 stores all of the rule codes as shown in FIG. 9 in the order of addresses in accordance with the order in which they were created. If there are two or more output variables, subrules of the rules set for all output variables are stored in the rule e memory 21.

As described above, the input data taken in from the AD/DA converter 13 is held in the input register 22 for one cycle.

, membership function (MSF) memory 23 is prestored with one data representing 17 membership functions NL-PL for each of the 58 possible inputs x1-x8. Furthermore, the above-mentioned membership functions N1 and N8 are set for the input functions x1 and x8, respectively.

The rule memory 21 stores one period T of the clock signal QO.
Address signal Q1~ which is incremented by 1 every time
Qll is given. Due to this.

The rule code, etc. (including various flags, etc.) stored in the rule memory 21 are read out N times every cycle T. Among the code-data Do-D7 read from the rule memory 21, DO-D5 is given to the membership function memory 23.

Other bits D6 and D7 are MIN circuit 24 and MA
The signals are respectively applied to the X circuits 25. Further, code data D3 to D5 representing one input variable are given to the input register 22. The start flag is used as a wait cycle to synchronize the address counters.

After synchronization is established, the input register 22 outputs input data (8 bits) related to the input variables specified by the given input variable codes D3 to D5, and supplies it to the membership function memory 23.

Among the membership functions stored in the membership function memory 23, the one specified by the code data DO-D2 representing the label given from the rule memory 21 and the code data D3-D5 representing the input variables is selected. be done. In this selected membership function, truth values (aj:j=1 to 7 in FIG. 4) corresponding to the input data given from the 1-input register 22 are read out from the membership function memory 23.

In this embodiment, this truth value is 4-bit data TAO~
It is represented by TA3 and is input to the MIN circuit 24.

As explained using FIG. 4, the MIN circuit 24 has 1
It performs MIN calculation of truth values between subrules in one rule, and register 3I, comparison circuit 32, and O
It is composed of an R circuit 33.

The read data TAO-TA3 of the memory 23 is stored in the register 3.
1 and input A of the comparison circuit 32. The data held in register 31 is applied to input B of comparison circuit 32. Comparison circuit 32 compares two inputs A and B and generates an output when A<B.

This output is applied as a trigger to the clock input terminal CLK of the register 31 via the OR circuit 33. Further, the rule flag bit D6 read from the rule memory 21 is also applied as a trigger to the clock input terminal CLK of the register 31 via the OR circuit 33. Therefore, 1
The truth value of the first subrule of the two rules is taken into the register 31 by the rule flag ♦ bit D6 and applied to the input terminal B of the comparison circuit 32. After one period T, the truth value of the next subrule is applied to the input terminal A of the comparison circuit 32. If the truth value of input terminal A is smaller than the truth value held in register 31.

The contents of the register 31 are updated by the truth value applied to the input terminal A by the output of the comparison circuit 32. The above operations are repeated, and the minimum truth value derived from subrules belonging to one rule is extracted.

Note that if the sub-rule read from the rule memory 21 is an empty rule (xl=N1), the maximum truth value (that is, data corresponding to 1.0) is transferred from the memory 23 to data TAO-TA3. Since it is output as
It does not affect the MxN operation described above.

When there are two or more rules with the same membership function (label) of the consequent part, as in rules 3 and 4 described above, the MAX circuit 25 calculates the MIN in those rules.
Used to select the largest value of the calculation result.

The MAX circuit 25 has a register 41, a comparison circuit 42, and an A.N.
The register 41 is cleared by applying the label flag bit D7 outputted from the device rule memory 21 consisting of the D' circuit 43 and the NOT circuit 44 to the clear terminal of the register 41 via the NOT circuit 44. . The output of the register 41 is applied to one input terminal B of the comparison circuit 42. on the other hand.

The output of the register 31 of the Fvl 1 N circuit 24 is input to the other input terminal A of the comparison circuit 42. The comparison circuit 42 generates an output when A>B, and the output is sent to the AND circuit 4.
Enter 3. After register 4I is cleared, its output is zero, so output j is generated from comparator circuit 42.

On the other hand, the counter 26 counts the timing signal CB generated every cycle T of the clock signal QO.

When the count value becomes 4 or more, a 2-bit output is generated and applied to the AND circuit 43. The output of the AND circuit 43 is applied to the clock input terminal CLK of the register 41.

Therefore, when reading the truth value for one rule including four sub-rules is completed, the MIN operation result held in register 31 at that time is stored in register 4.
It will be incorporated into 1. If only one rule exists for one consequent label, the MIN calculation result held in this register 4i is taken into the control unit 11 as data TO to T3. At this time, MAX calculation is not substantially performed. Counter 26 is cleared by the rule flag bit.

If there are two or more rules for one type of label in the m case part, the first MI held in the register 41
N operation result (input B) and 2 held in register 31
The comparison circuit 42 compares the second MIN operation result (input A) with the second MIN operation result (input A), and only when A>B, the second MIN operation result is taken into the register 41, and when A≦B, the register 4
The contents of L are retained as is. The same applies when there is a third rule. In any case, when the MAX operation for that label is completed, the data T in register 41 is
O to T3 are taken into the control section 11.

Even for an empty label for which there is no rule for the consequent label, the MIN/MAX calculation is apparently performed for four periods 4T according to the subrule x8mN8. In this case, the register 41 holds data 0.

This is taken into the control section 11. This data is the control unit 1
It does not affect the overall calculation performed in 1.

A label counter 27 is provided that counts the bits of label flag D7. The control unit 11 controls this counter 2
The inference result a1 of the inference unit 12 is taken in at the time when the count value of 7 changes. Further, when the counter 27 counts the label flag of the end flag and the counted value reaches 0100, an interrupt signal is given to the control section 11. As a result, the control section 11
learns that the inference for one output variable has ended and clears all the counters in the inference section 12.

In the above embodiment, MIN/MAX is used as a fuzzy inference calculation.
'IrAW is used, but the present invention is not limited thereto, and it goes without saying that it can also be applied to fuzzy inference using other operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an overview of the overall configuration of the fuzzy controller. FIG. 2 shows an example of a membership function, and FIG. 3 shows a singleton. Figures 4 and 5 show the fuzzy inference process.
FIG. 4 is for explaining the inference for each rule, and FIG. 5 is for explaining the overall arithmetic processing. FIG. 6 shows the rule code format, and FIG. 7 shows the codes assigned to input variables, labels, and output variables. FIG. 8 shows an example of a rule for one output variable, and FIG. 9 shows a state in which the rule in FIG. 8 is broken down into sub-rules and coded. FIGS. 10a and 10b are flow charts showing the rule code creation processing procedure. FIG. 1 is a time chart showing the parallel processing of the fuzzy inference section and the control section. FIG. 12 is a time chart showing the flow of fuzzy inference processing for one block (one output variable). Figure 13 shows the specific configuration of the fuzzy inference section -fMI 4
The block diagram shown in FIG. 14 is a rhythm chart showing its operation. 11...control unit. 12...Fuzzy reasoning section. 13...AD/DA conversion section. I4... bus. 21... Rule memory. 22...Input register. 23... Membership function (MSF) 24...M
IN circuit. 25...MAX circuit. 26...Counter. 31, 41... register. 32, 42... Comparison circuit. 33...OR circuit. 43...AND circuit. Over Memory Figure Rule Code Format Figure 8 Figure 10b Figure 0g

Claims (10)

[Claims] (1) Rule memory that stores subrules decomposed and coded for each input variable in a fixed order, input registers that temporarily store input data for each input variable, and multiple types of membership functions stored in advance. and a membership function memory that outputs a truth value corresponding to the input data given from the input register in the membership function specified by the sub-rule read from the rule memory, and output from the membership function. Between the truth values,
A fuzzy controller comprising: a first arithmetic circuit that performs a first fuzzy operation for each rule. (2) The apparatus further includes a second arithmetic circuit that performs a second fuzzy operation between the arithmetic results of the first arithmetic circuit when there are multiple rules for one type of membership function in the consequent part. The fuzzy controller according to claim (1). (3) Claim (1) wherein the first arithmetic circuit is a MIN circuit.
The fuzzy controller described in (4) Claim (2) wherein the second arithmetic circuit is a MAX circuit.
The fuzzy controller described in (5) The fuzzy controller according to claim (2), further comprising a counter that counts the number of sub-rules generated from one rule and controls the second arithmetic circuit based on the counted value. (6) A sub-rule code is formed using a code representing an input variable of an antecedent part of a rule and a code representing a membership function, and the sub-rule code is stored in the rule memory in a fixed order ( 1) Operation method of the fuzzy controller described in 1). (7) The operating method according to claim (6), wherein the input data stored in the input register is selected by a code representing an input variable included in the code of the sub-rule. (8) Data representing multiple types of membership functions for each input variable is stored in the membership function memory in advance, and the code representing the input variable and the code representing the membership function included in the code of the sub-rule are stored in advance. 7. A method of operation according to claim 6, wherein one membership function is specified. (9) A rule flag bit indicating a change point of the rules arranged in a certain order is included in the code of the sub-rule, and the first arithmetic circuit is controlled by the rule flag bit. A method of operating the fuzzy controller described in (1). (10) A label flag bit indicating a change point in the type of membership function of the consequent in a rule arranged in a certain order is included in the code of the above sub-rule, and this label flag bit is used to 3. The fuzzy controller operating method according to claim 2, wherein the fuzzy controller is configured to control a second arithmetic circuit.