JPH0314382A - Signal processor for digital signal - Google Patents

Abstract

PURPOSE:To attain a quick recording mode by fetching video signals corresponding to the number of operations coincident with the number of memories when a function switch is continuously depressed within a period required for recording video signals corresponding to one screen. CONSTITUTION:When a mode switch 120 is switched to a single mode, a single recording mode is set up. When a shutter switch 122 is depressed thereafter, video signals for one field at the operation timing are inputted to a memory means 60. If the shutter switch 122 is continuously depressed twice or more within a prescribed time, video signals corresponding to the number of fields coincident with the number of used memories in the memory means 60 are fetched to the memory mean 60 in each field. Consequently, a so-called quick recording mode capable of fetching video signals intermittently at 1/60sec intervals can be attained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal processing device for digital signals suitable for use as an adapter for a digital audio tape recorder, and particularly to a signal processing device for continuously capturing inserted screens. Concerning specific examples of possible screen capture methods.

[Prior Art] Current digital audio tape recorders (hereinafter referred to as DAT) are capable of recording and reproducing only audio signals.

However, it would be very convenient if not only audio signals but also other signals, such as video signals for still images, could be recorded and played back simultaneously.

Here, in order to record and reproduce Video I No. 8, it is conceivable to record each signal one channel at a time, such as recording audio signals on odd-numbered tracks and recording video signals on even-numbered tracks.

Alternatively, it may be possible to record in a format other than the current audio format.

[Problems to be Solved by the Invention] However, if an audio signal is recorded on one channel and a video signal is recorded on the other channel in the DAT audio format, unless a playback device that can also play back the video signal is used. , the video signal will also be played back at the same time.

In a DAT having only an audio signal reproducing device, when a video signal is reproduced, this becomes excessive noise and is therefore unusable.

If a video signal is recorded in a format other than the current audio format, it will not be compatible with the current DAT, and therefore the normal DAT will not be able to reproduce even the audio signal.

In order to solve these problems, it is necessary to be able to record and reproduce video signals without adversely affecting audio signals while maintaining compatibility with current models.

Furthermore, in a signal processing device that implements such signal processing, there are times when it is desired to capture not only one screen but two or more consecutive screens that match the audio signal to be recorded.

For example, when two consecutive screens are more effective as an insert video.

Since the video signal of the inserted screen is usually temporarily stored in memory, the video signal is captured intermittently. Furthermore, since the video signal is captured after a certain period of time, a certain amount of technical ingenuity is required to capture the video signal multiple times within a short period of time.

Therefore, the present invention takes these points into consideration, and particularly proposes a signal processing device having a function of continuously capturing necessary screens.

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the present invention, the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this A digital signal processing device in which a video signal is added to or separated from the audio signal for signal processing, comprises a memory means having two or more memories, and a function for capturing the video signal at an arbitrary timing. and a switch, so that when the function switch is operated continuously within the period required to record the video signal for one screen, the video signal is captured for the number of operations equal to the number of the memories. It is characterized by what has been done.

[Function] When the mode switch 120, which is a function switch, is set to the continuous mode side, the video signal for one field (or one frame) is stored in the memory means 6 at predetermined intervals.
0 and is mixed with the audio signal and recorded. The predetermined time is any time longer than the time required to record one screen worth of video signals (in this example, 2 seconds or more).

When the mode switch 120 is now switched to the single mode, the mode becomes the single recording mode. After that, when the shutter switch 122 is operated, 1
A field worth of video signals is taken into memory means 60.

At this time, when the shutter switch 122 is operated two or more times in succession within a predetermined period of time, the video signal of the number of fields equal to the number of memories used in the memory means 60 is also taken into the memory means 60 in units of one field. .

Then, in the fastest operation, video {g can be intermittently taken in at 1760 second intervals, so a so-called quick-shot mode can be realized.

[Embodiment] Next, an example of a signal processing device for digital signals according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 2 shows an example of the format (bit configuration) of the digital signal DS in which the audio signal Sa and the video {epsilon number Sv are mixed.

In this invention, in consideration of both compatibility with conventional models and the playback quality of audio signals, the D
Although the number of bits of the AT original digital signal DS is used, it is divided into two as shown in A and B in the same figure, and the digital audio signal DSa is on the upper bit side.
A digital video signal DSv is applied to each of the lower bits.

If it conforms to the audio format, the total number of bits is T (T
is an integer), this is selected as T=16, the number of bits of the digital audio signal DSa is set to N (N is an integer), and the remaining bits 'Pl. M(=TN
) is the digital video signal DSv, better results can be obtained by selecting N such that N≧1/2T. Among these, a practical value is about N=8 to 10 (Fig. 2A). As a result, the digital video signal DSV has a 6- to 8-bit configuration (FIG. 2B). In this example, N=10 and M=6.

Then, if the digital audio signal DSa and the digital video signal DSv are mixed so that the digital audio signal DSa is on the upper bit side, the upper 10 bits become the area of the digital audio signal DSa,
The lower 6 bits are the area of the digital video signal DSy (FIG. 2C).

When mixing the audio signal Sa with the video signal SV after applying noise countermeasures such as noise reduction, the relationship between the audio signal Sa and the video signal Sv is not limited to the above-mentioned relational expression, and the audio signal It is also possible to further reduce the number to Pi 1 of Sa.

A digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, is recorded thereon, and is reproduced from the rotating magnetic head (not shown).

48kHz as audio sampling clock fs
On the other hand, if the video sampling clock is 3fsc (fsc is 3.58MHz), the frequency difference between the two is about 112 times, so one field of video signal takes about 2 seconds to record. Ru. Also,
Since the audio (narration and BGM) corresponding to the image content of the video signal is usually longer than 2 seconds, the audio signal for one image is usually 2 seconds or more.
Recorded for more than seconds. As a result, if the audio signal is used as a reference, a plurality of images can be inserted before the audio signal ends.

Considering the later search processing and the like, it is preferable to add the video signal to the audio signal with some kind of identification code added to the video signal (image data). Signal formats have been constructed from such key points.

FIG. 3 shows an example.

An identification code ID is added before and after the video signal (image data) inserted into the audio signal (sound data). As shown in the figure, the identification code ID includes a start code section S-ID that is added immediately before the video signal, and a stop code section E that is added immediately after the video signal.
- An example of a case where the ID is configured is shown below.

Examples of how the start code section S-ID is used include (1) identification code of the video signal data, that is, the image data itself, (2) the format of the video signal, that is, whether it is a composite video, or Y Signal and C {g video or R. G. Examples include identification code for B component video, (3) quantization bit number of image data, and (4) cue code (LS/ID) for image data. However, this is just an example. To realize this usage example, start code section S
- It is possible to configure the ID as follows.

Figure 4 is an example. First, as shown in the figure, a 6-bit code in which only the least significant bit is "1" is used as a start code. Similarly, a code consisting of all "O's" is used as a stop code.

If 6 bits are treated as l block B, (4800
+1) Start code section S-IDII in block (approx. 50 msec)! i+ is constructed, 600 of which are main blocks, and the same code data is inserted into each main block. This is to enable the start code section S-ID to be searched no matter where in the start code section it is reproduced.

The main block is divided into 20 sub-blocks of 30 blocks, of which the first 12 sub-blocks F
O to Fil are used as framing codes. Then, when the codes of the blocks that make up each sub-block are all start codes, "O" is selected for the first time.
If all sub-blocks FO to Fll are "O", this is determined as a framing code.

Furthermore, the remaining eight subblocks DO to D7 are used as mode codes.

An example of the mode code is shown in FIG. The content of the mode code is an example.

As shown in FIG. 4, the stop code section E-ID is composed of 8 blocks (approximately 93 μsec) in this example.

Then, a certain blank period is placed in the latter half of this stop code section E-ID, and this start code section S-ID is set as a blank period.
From the beginning of the ID to the end of the blank period (approximately 2
seconds)' is taken as a unit area of one image data. The time of this unit area also corresponds to 120 times the vertical period.

Since the phase of the subcarrier fsc goes around in four fields, if the unit area is set to approximately 120 times the subcarrier fsc, the phase of the still image video signal Sv recorded before and after is always O phase, and the subcarrier fsc
Avoid the discontinuity of sc.

Now, FIG. 1 shows that after processing the digital signal No. 3 DS so as to adopt such a signal form, the digital signal DS recorded on the DAT and reproduced from this is converted into the original audio signal Sa and video signal Sv. An example of a main part of a signal processing device for separating and processing is shown below.

The signal processing system for the audio signal Sa will be explained first.

The audio signal Sa supplied to the audio input terminal 12 is supplied to the low-pass filter 16 via the amplifier 14, where it is band-limited, and then supplied to the A/D converter 18, where it is converted into a 10-bit digital audio signal DSa. be done. The audio sampling clock used at this time is fs (48kHz).

Digital audio No. 4g DSa mixes and separates means 86
The video signal is supplied to a mixing means (adder M) 20 constituting the video signal and mixed with a digital video signal DSv, which will be described later. The combined digital signal DS (FIG. 2C) is supplied to the digital out processing circuit 22 and converted into a digital signal conforming to the audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a bit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head via the terminal 24 and recorded.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a reproduction terminal 32, and subjected to digital-in processing.

For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced bit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the digital audio signal DSa and the digital video signal DSV are separated and outputted from the next-stage separation means 36. (Fig. 2 A, B).

10-bit digital audio signal DS
The signal a is converted into an analog signal by the D/A converter M3B, is limited to a predetermined band by the low-pass filter 40, and is then output to the audio out terminal 44 via the amplifier 42.

The signal processing system for the video signal Sv has the following configuration.

The still image video signal Sv supplied to the video input terminal 50 is supplied to the A/D converter 54 via the amplifier 52, and is converted into a 6-bit digital video signal DSV in this example.
is converted to The sampling clock used at that time has a frequency that is an integral multiple of the subcarrier fsc, and
In this example, it is 3fSe.

The digital video signal DSv is supplied to the memory means 60 via a changeover switch 56 for switching between an input signal and a reproduction signal and a changeover switch 58 for after-recording.

The memory means 60 functions as a time axis conversion means for the digital video signal DSV.

In other words, in order to combine the digital video signal DSv with the digital audio signal DSa, it is used for time axis expansion when reading out the digital video signal DSv in synchronization with the bit clock BCK, and for the time axis of the reproduced digital video signal DSv. Used for compression.

The memory means 60 has a pair of memories 62, 64, and a memory control circuit 70, 64 provided in association therewith.
Control is performed by 72 so that one field (or one frame) is stored in the corresponding memories 62 and 64.

When only one image is inserted one-shot, only one field of video signal is stored in one of the memories. If the same screen is to be inserted continuously, the stored video signal may be repeatedly read out. When inserting different screens successively, video signals are captured at predetermined time intervals and are stored alternately. memory 62
．． Since it takes about 2 seconds to read data from 64, the predetermined time is any time longer than 2 seconds.

Here, writing to the memories 62 and 64 is performed using the 3fSC clock. The reading is performed using a 2fs clock.

This is to make the time axis of the digital video signal DSv coincide with the time axis of the digital audio {M number DSa while maintaining synchronization. As shown in Figure 6,
Since both the L and R channels of the digital audio signal DSa are recorded sequentially, a 2fs clock instead of an fs clock is used during reading.

Reference numeral 100 denotes a control means for a memory, etc., to which the subcarry 7rsc extracted by the subcarrier extraction circuit 110 is first supplied. The control means 100 supplies a control lit signal to each memory control circuit 70, 72 based on this subcarrier fsc.

Reference numeral 124 denotes a changeover switch that is controlled in relation to the recording mode and playback mode in the signal processing device @lO, and the mode is determined based on the switching state.

ffilJ? The ff1 means 100 includes a digital out processing circuit 22 and a digital in processing circuit 3.
A bit clock BCK is supplied from four clocks. Therefore, a predetermined control signal is supplied to the memory control circuits 70 and 72 so that a read clock RCK (=2 fs) synchronized with this bit clock BCK is generated.

As a result, the digital audio signal DSa and the digital video signal DSV are input to the mixing means 2o in complete synchronization with this bit clock BCK.

In addition, in the digital out processing circuit 22, the detailed explanation is omitted, but based on the bit clock BCK,
A bit switching signal BS of 0 bit and 6 bit is created,
This bit switching {g signal BS is supplied to the mixing means 20, and the 10-bit digital audio signal DSa and the 6-bit digital video signal DSV are mixed as shown in FIG. 2C.

Reference numeral 112 denotes a vertical synchronization signal separation circuit, and a vertical synchronization signal extracted and separated from the digital video signal DSv is supplied to the control circuit 100. This allows the memory 62
．． 64, one field of digital video No. 3 DSv is always stored on the basis of the vertical period.

A pair of output changeover switches 66 and 68 that are switched in conjunction with each other are provided downstream of the memories 62 and 64. The output changeover switch 68 is used during signal recording, and the other output changeover switch 66 is used during signal reproduction.

The digital video {g DSv read out alternately from the memories 62 and 64 by the output cut-off 1M switch 68 is
The signal is supplied to a sync bit shift encoder 76, where sync bit shift processing is performed.

Originally, a video signal is A/D converted into 6 bits, so its sync bits are all "O" digital data. However, the above-mentioned identification code ID
Considering this, as shown in Figure 7, since the identification code ID is assigned to a bit that does not affect the image, processing is performed to shift only the sync bit, and the identification code ID and This makes it possible to distinguish between the sink bit and the sink bit.

Therefore, during recording, the sync bit is shifted by l bits, and then the adder 78 adds the identification code ID. 80 is this identification code ID
It is a generator of

Digital video signal DS with identification code ID added
v is subjected to parallel/serial conversion processing in the processing circuit 82 and is the most significant bit MSB of the digital video signal DSv.
Bit inversion processing is performed on the data. This process will be described later.

Digital video signal DSv that has undergone predetermined signal processing
is converted by the format conversion circuit 84 into a format conforming to the DAT signal format, and then mixed with the digital audio signal DSa as shown in FIG. 2C and sent to the DAT side.

When the digital signal DS is reproduced, the separating means 36 separates it into a digital audio signal DSa and a digital video signal DSv. The separated digital video signal DSv is converted to the original format by the format inverse conversion circuit 88, and this is converted into the original format by the signal processing circuit 90.
Parallel conversion processing is performed, and at the same time, re-inversion processing of the most significant bit of digital video signal DSv is performed.

Thereafter, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite direction to that during recording, and returned to the original sync bits (see FIG. 7).

After that, the memory 62
．． 64, and the playback digital video signal DSv is synchronized with the bit clock BCK.
Written by K (=2fs), subcarrier fs
It is read out based on the read clock RCK (-3fsc) related to c.

The digital video signal DSv output from the output changeover switch 66 passes through the input/output monitor changeover switch 102, is converted into an analog signal by the D/A converter 5104, and is outputted to the output terminal 108 via the amplifier 106 as a video out. There is a monitor means (not shown) on the video out side.

An identification code (D) detection means 94 is provided on the output stage side of the signal processing circuit 90, and the detected identification code ID is supplied to the control circuit 100. The memory control circuits 70 and 72 are controlled by this identification code ID, and signal processing is changed based on mode information.

Now, when the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 60, only the image data is stored. At this time, the final image data is obtained when a predetermined period of time has elapsed from the first data of the image data.In order to detect this final image data more accurately, in addition to time management, a stop code E-ID is detected. However, it is preferable to judge it as the final image data when the two match. When the storage of the final image data is completed, the writing and reading modes of the memory 62, 64 are reversed, and the output selector switch 66, 68 is also switched.

On the other hand, when the playback mode of the DAT is stopped during playback of the digital video signal DSv, the playback output data input to the terminal 32 is all "O" as shown in FIG.
”. Since time management (count-up processing) for image data is performed on the signal processing device 10 side, D
Even if the AT enters the stop mode, the count-up process does not stop in conjunction with this.

Therefore, 60 stages of memory are . Since it is still in the write mode, all "0" data is stored in the corresponding memory, for example 64, as original image data.

Then, when a predetermined time elapses from the stop mode, the playback time for the final image data arrives, and the playback data at that time is always all "0", so this may be mistakenly judged as a stop code. Put it away. In that case,
Signal processing device 1 0 @. At +1, it is assumed that the final image data has arrived and the memory means 60 is instructed to write and read modes and to switch the changeover switches 66 and 68, so the memory 64 is controlled to read mode.

Then, after DAT goes into stop mode, memory 6
Since the data ``0'' written in 4 is not read out and is monitored as an image, the data ``O'' portion appears black, resulting in a very unsightly image being monitored.

To avoid this, if the most significant bit of the image data is recorded inverted and then re-inverted during playback, as shown in Figure 8, even if the playback output when stopped midway is all "O",
After re-inversion processing, the most significant bit becomes "1".

As a result, on the signal processing device 10 side, (1) there is no misjudgment that the final image data has arrived;

(2) Therefore, the memory means 60 is not controlled to switch.

Therefore, according to (2), the previous screen is always monitored in this case, and the above-mentioned drawback is eliminated.

The operation of after recording will be explained next.

Before that, this signal processing device 10 includes at least two function switches 120, as shown in FIG.
122 is provided. One is a mode switch and the other is a shirt switch.

The mode switch 120 is for selecting whether the screen to be inserted is single or continuous, and the shutter switch 122 is for selecting the screen to be inserted when the screen to be inserted is a single shot. .

When after-recording an audio signal, the insertion screen remains as it is, so put the DAT in the playback state, monitor the screen, and then switch to after-recording mode when the screen you want to perform after-recording appears.

Then, the writing and reading of the memories 62 and 64 are repeated alternately, or the switching state is fixed when performing after-recording of Audio I No. 3.

For example, if the after-recording mode is selected while image data in the memory 62 is being monitored, the image data in the memory 62 is constantly monitored, while the image data in the memory 64 is ready to be recorded on the DAT.

The image data in memories 62 and 64 do not match in most cases. On the other hand, since the operator performs the after-recording operation while looking at the monitor screen, the monitor screen during after-recording is different from the screen actually recorded by after-recording.

To eliminate this problem, it is sufficient to match the image that is not being monitored and the image that is to be recorded when in the after-recording mode.

Therefore, in terms of hardware, a changeover switch 58 for after-recording is provided.

The after recording mode will be explained with reference to FIG.

It is assumed that the changeover switches 66 and 68 are switched to the state shown in FIG. 1 (FIG. 9F).

The write enable signal W is used so that the identification code ID added to the digital video signal DSv is not stored in memory.
"llr" is output (A, C in the same figure).

When the cue code LS-ID is detected among the identification codes ID, an address clear signal is output (B in the same figure).
. When the shutter switch 122 is pressed while the memory 64 is in the writing state (D in the figure), the control circuit 100 determines that it is the after-recording mode, and the memory means 60
fixes the operation mode to the previous operation mode.

Then, the after-recording switch 58 is switched to the terminal C side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is increased from 2 fs to 3 fs.
(E in the same figure). Then, the image data in the memory 62 is supplied to the memory 64 via the after-recording switch 58, and is rewritten at high speed.

Now, the image data in the memories 62 and 64 match, and the monitor screen and the image data to be recorded match.

When writing is completed, the write enable signal WT for the memory 64 is inverted, and image data cannot be written thereafter. After recording switch 58
also automatically returns to its original state, and the terminal d{I! Switch to l (
Figure G). The after-recording mode can be canceled by pressing the shutter switch 122 again during playback or by switching the mode switch 120 to the continuous side.

Next, the so-called continuous shooting mode of the video signal will be explained.

As mentioned above, when the mode switch 120 is switched to the continuous side, the video signal applied to the terminal 50 is automatically captured into the memory means 60 at approximately 2 second intervals. On the other hand, when the mode switch l20 is switched to the single side and the shutter switch 122 is pressed, one field of video signals is captured each time. Since it takes approximately 2 seconds to read data from the memory means 60, it is necessary to provide an interval of at least 2 seconds.

However, when actually inserting a screen into an audio signal, it may be necessary to capture the screen continuously. especially,
This is because, in the case of a moving screen, it may be necessary to capture several frames of the screen before and after.

However, if the timing of capturing the video signal is set in consideration of the data readout time of the memory means 60 as described above, the above-mentioned snapshot mode becomes impossible.

Therefore, when in shooting mode, a continuous shooting mode function has been added that allows you to capture the contents of the previous and subsequent screens. The number of screens that can be captured in succession depends on the amount of memory available in the memory means 60. In this example, since two memories 62 and 64 are used, the period required to record the video signal for one screen, in other words, the readout time of the memories 62 and 64 (in this example, The maximum number of images that can be captured within a period of about 2 seconds is 2.

FIG. 10 is an example of a control program for the snapshot mode provided as an accessory to the CPU built into the control circuit 100, and will be described with reference to FIG. 11 as well.

First, a counter is set to an initial value of 1, and then single mode is checked (steps 132, 134). When not in the single mode, the transfer status of one screen's worth of image data (data reading status of the memory 62, 64) is determined, and when the image data transfer is completed, the video signal of the next screen is stored in the memory means 60. automatically written (steps 136, 138). This is a continuous mode as described above.

When the mode is single mode, the contents of the counter are determined, and if the count value is the initial value (=1), the operating state of the shutter switch 122 is checked (steps 140 and 142). When pressed, increments the counter (;=2)
, the video signal of the screen when the V ivy switch 122 is pressed is stored in the memory means 60 (144,1).
46).

Then, as shown in FIG. 11 (1), when the transfer of image data for one screen is completed, the counter is returned to the initial value and the state returns to the standby state (steps 148, 150, 1).
34).

The time to capture a video signal for one screen is 1/60 second.

In the single mode, if the shutter switch 122 is operated continuously, the count value will be "2" before the transfer of image data for one screen is completed, as shown in FIG. In this case, the operating state of the shutter switch 122 is checked in step 154 via steps 140 and 152.

When the second operation is confirmed, the counter is incremented (=3), and then the video signal of the screen at the time of the second shutter operation is written into the memory means 60 (steps 155, 156). When the second video signal transfer is completed, the counter is reset to its initial value and then enters a standby state (steps 158 and 160).

When the shutter switch 122 is operated to capture the third screen while the second screen capture is completed and the image data is being transferred, the timing of the operation is within the period required to record the video signal. Therefore, the video signal at that time is not captured (Figure 11 (I)
(see l1)).

It is during the second screen capture that step 158
．． As is clear from 160, the count value remains 3 because the counter is not reset to the initial value. Since the shirt switch 122 is pressed in this state,
This is checked in step 152 and the count value is
2", the process skips to step 158, so the third screen will not be captured.

Therefore, as described above, even if the shutter switch 122 is operated at high speed two or more times within two seconds, only the first two images are actually captured.

If you record the screen in this snapshot mode, you can monitor each screen for 2 seconds during playback.

With the above configuration, it is possible to mix the audio signal Sa and the video signal Sv while adapting them to the current audio format. In this case, although the number of quantizations of the audio signal Sa is reduced from the current 16-bit configuration to a 10-bit configuration, there is little deterioration in sound quality due to this decrease in the number of quantizations. Furthermore, since the video is a still image, 6-bit quantization is sufficient.

When the digital signal DS, which is a mixture of the audio signal Sa and the video signal Sv, is to be played back using the current DAT, that is, as shown in Fig. When the video signal DSv is reproduced as the digital audio signal DSa, there is almost no influence on the audio signal Sa.

In that case, for the audio signal Sa, the video signal Sv
is nothing but a noise component. However, as is clear from FIG. 2C, since the digital video signal DSv is inserted into the lower bit side of the digital audio signal DSa, the audio signal Sa can have a dynamic range of about 6NdB.

Therefore, as mentioned above, if the quantization number N is selected to be about 10 bits, the compact power set, Dolby B
(Trademark) The dynamic range is comparable to recording and playback. For this reason, even if the video signal Sv is played back at the same time,
There is almost no effect on the audio signal Sa, and there is little deterioration in sound quality.

If the bit combination position is reversed so that the least significant bit data 0 of the digital video signal DSV comes to the least significant bit data AO side of the digital audio signal DSa as shown in FIG. The effect is practically negligible.

The after-recording process is an example of after-recording an audio signal, but it can also be configured to after-record a video signal.
It is also possible to configure so that any one of them can be selected.

If the number of memories in the memory means 60 is three or more, the number of snapshots that can be recorded within the period required to record the video signal will be the number of memories.

In the above description, T=16, N=10, and M=6, but as mentioned above, the values of N and M are not limited to these.

[Effects of the Invention] As explained above, according to the present invention, when recording and reproducing video signals such as still images in addition to audio signals at the same time, the two are mixed in accordance with the DAT audio format. It is something.

Therefore, compatibility with the current model (DAT) can be achieved. Of course, efforts have been made to minimize deterioration in the sound quality of the reproduced audio signal.

Furthermore, it has the feature of being able to realize a quick shooting mode, and thus realizing a variety of screen insertion functions.

Therefore, this signal processing device is extremely suitable for use as an accessory device such as a DAT for events.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing an example of a signal processing device for digital signals according to the present invention, Fig. 2 is a configuration diagram showing an example of an audio format of digital signals, and Figs. 3 to 7 are explanations of identification codes, respectively. Figure 8 is an explanatory diagram of bit inversion processing of a digital video signal, Figure 9 is a waveform diagram of after-recording processing, Figure 10 is a flowchart for realizing the snapshot mode, Figure 11 is an explanatory diagram thereof, FIG. 12 is a system diagram showing an example of the current DAT. 1 0 ・ 20 ● 36 ・ 58 ◆ 60 ・ 76 ・ 80 ・ 82. 90 ・ 92 ・ 94 ・ Sa ・ DSa ・ Sv ・ DSv ・ ・Signal processing device・Mixing means・Dividing means・Dub recording switch・Video signal memory means・Sync bit shift encoder・Identification code generator・Signal processing circuit・Sink Bit shift decoder/Identification code detection circuit/Audio code/Digital audio {ε number/Video number 48/Digital video signal ↓\1); Ninny;}: Figure 5 Recorded original video data MSB inverted recording MSB inverted playback in progress Playback output MSB inversion playback when stopped

Claims (1)

[Claims] (1) A digital device in which the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this video signal is added to the audio signal or separated from the audio signal for signal processing. A signal processing device, comprising a memory means having two or more memories and a function switch for capturing a video signal at an arbitrary timing, within a period required to record the video signal for one screen. A signal processing device for digital signals, characterized in that when the function switch is operated continuously, video signals corresponding to the number of operations of the memory are captured.