JPH0314377A - Signal processor for digital signal - Google Patents

Abstract

PURPOSE:To simply correct the noncoincidence of contents between a monitor screen generated at the time of post recording processing and a screen to be rerecorded by mixing both the contents in accordance with the voice format of a DAT. CONSTITUTION:When a post recording mode is selected, a reproduced video signal is stored in the other memory and a video signal to be recorded is allowed to coincide with a monitoring video signal. Namely, if a shutter switch 122 is depressed when a memory 64 is in a writing state, a control circuit 100 judges the post recording mode and fixes the operation mode of a memory means 60 on the immediately preceding operation mode. When a post recording switch 58 is turned to the terminal (c) side an the frequency of a writing clock PCK in the memory 64 is changed from 2fs to 3fsc simultaneously, the image data of a memory 62 are supplied to the memory 64 through the switch 58 and rapidly rewritten. Consequently, the image data of both the memories 62, 64 coincide with each other and the monitor screen coincides with the image data to be recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing device for digital signals suitable for use as an adapter for a digital audio tape recorder, particularly when in an after-recording mode. The present invention relates to after-recording processing in which a video signal for monitoring is made to match a video signal for monitoring.

[Prior Art] Current digital audio table recorders (hereinafter referred to as DATs) are capable of recording and reproducing only audio signals.

However, it would be very convenient if not only audio signals but also other types of signals, such as video signals for still images, could be recorded and played back simultaneously.

Here, in order to record and reproduce video signals, it is conceivable to record each signal one channel at a time, such as recording audio signals on odd-numbered tracks and recording video signals on even-numbered tracks.

Alternatively, it may be possible to record in a format other than the current audio format.

[Problems to be Solved by the Invention] However, if an audio signal is recorded on one channel and a video signal is recorded on the other channel in the DAT audio format, unless a playback device that can also play back the video signal is used. , the video signal will also be played back at the same time.

In a DAT having only an audio signal reproducing device, when a video signal is reproduced, excessive noise is generated in the DAT, making it unusable.

If a video signal is recorded in a format other than the current audio format, it will not be compatible with the current DAT, and therefore the normal DAT will not be able to reproduce even the audio signal.

In order to solve these problems, it is necessary to be able to record and reproduce video signals without adversely affecting audio signals while maintaining compatibility with current models.

For signal processing equipment that performs the processing described in item 2 above, it is also a good idea to add a function that can perform after-recording (so-called post-recording) of audio or video signals that have not already been recorded. It will be done. In this case, it is very inconvenient if the contents of the monitor screen and the contents of the screen to be recorded do not match. This is because normally in the after-recording mode, the after-recording process is performed while monitoring the screen.

Therefore, the present invention takes these points into consideration and proposes a signal processing device that can improve after-recording processing.

[Means for Solving the Problem] In order to solve the above-mentioned problem, in the present invention, the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this video In a digital signal signal processing device that adds a signal to the audio signal or separates the signal for signal processing, when the audio signal or the video signal is immediately after-recorded while monitoring the unplayed video signal, the video signal is a memory means having at least one pair of memories functioning for time axis conversion; an external terminal for monitoring the video signal read out from the memory means; and an after-recording mode located on the input stage side of the memory means. and an input changeover switch that is operated when the input changeover switch is supplied with the video signal and the playback video signal read out from the memory means, and when the after-recording mode is selected, the playback video signal is supplied to the changeover switch. The video signal to be recorded is matched with the video signal for monitoring by loading the signal into the other memory.

[Operation] After-recording is performed while monitoring the playback video signal. When the memory 64 shown in FIG. 1 is in the writing state, when the shutter switch 122 for selecting the after-recording mode is pressed (D in FIG. 9), it is determined that the memory 64 shown in FIG. 1 is in the after-recording mode. Then, the operation mode of the memory means 60 is fixed to the immediately previous operation mode.

Then, the dubbing switch 58 is switched to the terminal C side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is changed from 2fs to 3fsc (
Figure E). Then, the image data in the memory 62 is supplied to the memory 64 via the dubbing switch 58, and is rewritten at high speed.

The image data in the memory 6-2.64 now match, and the monitor screen (video signal in the memory 62) and the image data to be recorded (video signal in the memory 64) match.

[Embodiment] Next, an example of a signal processing device for digital signals according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

FIG. 2 shows an example of the format (bit configuration) of a digital signal DS in which the audio signal No. 8 Sa and the video signal Sv are mixed.

In this invention, in consideration of both compatibility with conventional models and the playback quality of audio signals, the D
Although the number of bits of the AT original digital signal DS is used, it is divided into two parts as shown in A and B in the same figure, and the upper bit side is the digital audio signal DS.
a, and the digital video signal DSv is applied to the lower bit side, respectively.

If it conforms to the audio format, the total number of bits is T (T
is an integer), this is selected as T=16, the number of bits of the digital audio signal DSa is set to N (N is an integer), and the remaining number of bits M (=T-N) is set as the digital video signal DSv. In this case, better results can be obtained if N is selected as N times 1/2T. Among these, a practical value is about N=8 to 10 (Fig. 2A). As a result, the digital video signal DSV has a 6- to 8-bit configuration (FIG. 2B). In this example, N=10. M=6.

Then, if the digital audio decoded DSa and the digital video signal DSv are mixed so that the digital audio signal DSa is on the upper bit side, the upper 10 bits become the area of the digital audio signal DSa,
The lower 6 bits are the area of the digital video signal DSv (FIG. 2C).

When mixing the audio signal Sa with the video signal SV after applying noise countermeasures such as noise reduction, the relationship between the audio signal Sa and the video signal Sv is not limited to the above-mentioned relational expression, and the audio signal Sa It is also possible to further reduce the number of bits.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown 5) provided on the DAT, where it is recorded and reproduced.

48k as audio sampling clock fs
When using Hz, on the other hand, when the video sampling clock is 3fsc (fsc is 3.58MHz), the difference in frequency is about 112 times, so it takes about 2 seconds to record one field of video signal. be done. Furthermore, since the audio signal (narration or BGM) corresponding to the image content of the video signal is usually longer than 2 seconds, the audio signal for one image is usually recorded for 2 seconds or longer. As a result, if the audio signal is used as a reference, a plurality of images can be inserted before the audio signal ends.

Considering the later search processing and the like, it is preferable to add the video signal to the audio signal with some kind of identification code added to the video signal (image data). Signal formats are constructed from this perspective.

FIG. 3 shows an example.

An identification code ID is added before and after the video signal (image data) inserted into audio No. 48 (audio data).As shown in the figure, an identification code ID is added immediately before and after the video signal. A case will be exemplified in which the start code section S-ID is added and the stop code section E-ID is added immediately after.

Examples of how the start code section S-ID is used include (1) identification code of the video signal data, that is, the image data itself, (2) the format of the video signal, that is, whether it is a composite video, or Y Signal and C {Identification code for video number i or R, G, B component video, (3) quantization bit number of image data, (4) cue code (LS/ID) for image data, etc. It will be done. However, this is just one example.

To realize such a usage example, start code part S
- It is possible to configure the ID as follows.

Figure 4 is an example. First, as shown in the figure, a 6-bit code in which only the lowest pit is "1" is used as a start code. Similarly, a code consisting of all "O's" is used as a stop code.

Treating 6 bits as 1 block B, (4800
+1) A start code section S-I is constructed using blocks (approximately 50 asec), of which 600 blocks are made into main blocks, and the same code data is inserted into each main block. This is so that the start code section S-ID can be searched no matter where in the start code section it is played back.

The main block is divided into 20 sub-blocks of 30 blocks, of which the first 12 sub-blocks F
O to Fll are used as framing codes. Then, when the codes of each block constructing each sub-block are all start codes, "0" is set for the first time.
If all sub-blocks FO to Fil are "O", this is determined as a framing code.

Furthermore, the remaining eight subblocks DO to D7 are used as mode codes.

An example of the mode code is shown in FIG. The content of the mode code is an example.

As shown in FIG. 4, the stop code section E-ID is composed of 8 blocks (approximately 93 μsec) in this example.

Then, a certain blank period is placed in the latter half of this stop code section E-ID, and this start code section S-ID
The period from the beginning of the ID to the end of the blank period (approximately 2 seconds) is defined as one unit area of image data. The time of this unit area also corresponds to 120 times the vertical period.

Since the phase of the subcarrier fsc goes around in four fields, if the unit area is set to approximately 120 times the subcarrier fsc, the phase of the still image video signal Sv recorded before and after is always O phase, and the subcarrier fsc
sc discontinuity can be avoided.

Now, FIG. 1 shows that after processing the digital signal DS so as to adopt such a signal form, the digital signal DS recorded on the DAT and reproduced from this is converted into the original audio {tV No. Sa and video signal Sv. An example of a main part of a signal processing device for separating and processing is shown below.

The signal processing system of Audio I No. 3 Sa will be explained first.

The audio decoded Sa supplied to the audio input terminal l2 is supplied to the low-pass filter 16 via the amplifier 14 to be band-limited, and then supplied to the A/D converter 18 to be converted into a 10-bit digital audio signal DSa. converted. The audio sampling clock used at this time is fs (48kHz).

The digital audio signal DSa is supplied to the mixing means (adder) 20 constituting the mixing and separating means 86 and mixed with a digital video {No. 8 DSv, which will be described later. The mixed digital signal DS (FIG. 2C) is supplied to the digital out processing circuit 22 and converted into a digital signal in a form compliant with the audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating the bit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head via the terminal 24 and recorded.

The digital signal DS reproduced by the rotating magnetic head is supplied to a digital-in processing circuit 34 via a reproduction terminal 32, and subjected to digital-in processing.

For example, a PLL circuit (not shown) is driven to generate a master clock synchronized with the reproduced pit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the digital audio signal DSa and the digital video signal DSv are separated and outputted from the next-stage separation means 36. (Fig. 2 A, B).

Separated 10-bit digital audio signal DS
The signal a is converted into an analog signal by a D/A converter 38, limited to a predetermined band by a low-pass filter 40, and then outputted to an audio out terminal 44 via an amplifier 42.

The signal processing system for the video signal Sv has the following configuration.

The still image video signal Sv supplied to the video in terminal 50 is supplied to the A/D converter 54 via the amplifier 52, and in this example, a 6-bit digital video signal DSv is supplied to the A/D converter 54.
is converted to The sampling clock used at that time has a frequency that is an integral multiple of the subcarrier fsc,
In this example, it is 3fsc.

The digital video signal DSv is supplied to the memory means 60 via a changeover switch 56 for switching between input signal and reproduction A3 and a changeover switch 58 for after-recording.

The memory means 60 functions as a time axis conversion means for the digital video signal DSV.

In other words, in order to combine digital video signal No. 8 DSv with digital audio signal DSa, it is used for time axis expansion when reading out digital video signal DSv in synchronization with pit clock BCK, and for Used for time axis compression.

The memory means 60 has a pair of memories 62, 64, and memory control circuits To, 64 provided in connection therewith.
72, the data is controlled to be stored one field (or one frame) at a time in the corresponding memories 62 and 64.

When only one image is inserted one-shot, only one field of video signal is stored in one of the memories. If the same screen is to be inserted continuously, the stored video signal may be read out repeatedly. When inserting different screens successively, video signals are captured at predetermined time intervals and are stored alternately. memory 62
．． Since it takes about 2 seconds to read data from 64, the predetermined time is any time longer than 2 seconds.

Here, writing to the memories 62 and 64 is performed using a 3fSC clock. The reading is performed using a 2fs clock.

This is to synchronize the time axis of the digital video decoded DSv with the time axis of the digital audio signal DSa while maintaining synchronization. As shown in FIG. 6, since the digital audio signal DSa is designed to record both L and R channels sequentially, at the time of reading,
A 2fs clock is used instead of fs.

Reference numeral 100 denotes a control means for a memory, etc., to which the subcarrier fsc extracted by the subcarrier extraction circuit 110 is first supplied. Based on the subcarrier fsc, the control means 100 supplies the control II{ε to the respective memory control circuits 70 and 72.

Reference numeral 124 denotes a changeover switch that is controlled in relation to the recording mode and playback mode in the signal processing device 10, and the mode is determined based on the switching state.

The control means 100 is supplied with a bit clock BCK from the digital out processing circuit 22 and the digital in processing circuit 34. Therefore, the read clock RCK (=2 fs
) is generated by the memory control circuit 70 .
72, a predetermined control signal is supplied.

As a result, the digital audio signal DSa and the digital video signal DSv are input to the mixing means 2o in complete synchronization with this pit clock BCK.

Further, in the digital out processing circuit 22, the detailed explanation is omitted, but based on the pit clock BCK,
The bit switching signal BS of 0 bit and 6 bit is not created,
This bit switching signal BS is supplied to the mixing means 20,
A 10-bit digital audio signal DSa and a 6-bit digital video signal DSv are mixed as shown in FIG. 2C.

Reference numeral 112 denotes a vertical synchronization signal separation circuit, and the vertical synchronization signal extracted and separated from the digital video signal DSv is supplied to the control circuit tM times #i100. As a result, one field of digital video No. 3 DSv is always stored in the memories 62 and 64 on the basis of the vertical period.

A pair of output selector switches 66, 68 which are switched in conjunction with each other are provided downstream of the memories 62, 64. The output changeover switch 68 is used during signal recording, and the other output changeover switch 66 is used during No. 8 reproduction.

The digital video signals DSv alternately read out from the memories 62 and 64 by the output changeover switch 68 are supplied to the sync bit shift encoder 76, where the sync bits are shifted.

Originally, a video signal is A/D converted into 6 bits, so its sync bits are all "0" digital data. However, the above-mentioned identification code ID
Considering this, as shown in FIG. 7, since the identification code ID is assigned to the bit that does not affect the image, processing is performed to shift only the sync bit, and the identification code ID is assigned to the bit that does not affect the image. and the sync bit can be distinguished from each other.

Therefore, during recording, the sync bit is shifted by one bit, and then in addition error 78, an identification code ID is added. 80 is this identification code ID
It is a generator of

Digital video i No. 8D with identification code ID added
Sv is subjected to parallel/serial conversion processing in the processing circuit 82, and is converted into the most significant bit MS of the digital video signal DSv.
Bit inversion processing is performed on B. This process will be described later.

Digital video encoder DSv that has undergone predetermined signal processing
is converted by the format conversion circuit 84 into a format compliant with DAT No. 48 format, and then the second
As shown in Figure C, it is mixed with the digital audio signal DSa and sent to DAT@.

When the digital signal DS is reproduced, the separating means 36 separates it into a digital audio signal DSa and a digital video signal DSv. The separated digital video signal DSv is converted to the original format by the format inverse conversion circuit 88, and this is converted into the original format by the signal processing circuit 90.
Parallel conversion processing is performed, and at the same time, re-inversion processing of the most significant bit of digital video signal DSV is performed.

Thereafter, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite direction to that during recording, and returned to the original sync bits (see FIG. 7).

After that, the memory 6 is transferred via the selector switch 56+58.
2.64 and reproduced digital video signal DSv
is the write clock W synchronized with the pit clock BCK.
Written by CK (=2fs), subcarrier f
Read clock RCK related to sc (=3fsc)
is read based on.

The digital video signal DSv output from the output changeover switch 66 passes through the input/output monitor changeover switch 102, is converted into analog by the D/A converter 104, and is outputted to the output terminal 108 via the amplifier 106 as video out. . There is a monitor means (not shown) on the video out side.

An identification code (D) detection means 94 is provided on the output stage side of the signal processing circuit 90, and the detected identification code ID is supplied to the control circuit 100. The memory control circuits 70 and 72 are controlled by this identification code ID, and the process No. 43 is changed based on the mode information.

Now, when the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 60, only image data is stored. At this time, the final image data is obtained when a predetermined period of time has elapsed since the first data of the image data, but in order to detect this final image data more accurately, in addition to time management, the stop code E-ID is detected. , it is preferable to judge it as the final image data when both of them match. When the storage of the final image data is completed, the writing and reading modes of the memories 62 and 64 are reversed, and the output selector switch 66
．． 68 also switches.

On the other hand, when the playback mode of the DAT is stopped during playback of the digital video signal DSv, the playback output data input to the terminal 32 is all "O" as shown in FIG.
”. Since time management (count-up processing) for image data is performed on the signal processing device IO side, D
Even if the AT enters the stop mode, the count-up process does not stop in conjunction with this.

Therefore, since the memory means 60 is still in the write mode, all "0" data is stored in the corresponding memory, for example 64, as original image data.

Then, when a predetermined period of time has elapsed from the stop mode, the playback time for the final image data has arrived, and since the playback data at that time is always all "O", this may be mistakenly judged as a stop code. Put it away. In that case,
The signal processing device 10 side assumes that the final image data has arrived and instructs the memory means 60 to write and read modes and to switch the changeover switches 66 and 68, so the memory 64 is controlled to the read mode. Ru.

Then, after DAT goes into stop mode, memory 6
Since the data "O" written in 4 is read out and monitored as an image, the data "O" portion appears black, resulting in a very unsightly image being monitored.

In order to avoid this, if the most significant bit of the image data is recorded inverted and re-inverted during playback, as shown in Figure 8, even if the playback output when stopped midway is all rQ,
After re-inversion processing, the most significant bit becomes "1".

As a result, on the signal processing device 10 side, (1) there is no misjudgment that the final image data has arrived;

(2) Therefore, the memory means 60 is not controlled to switch.

Therefore, according to (2), the previous screen is always monitored in this case, and the above-mentioned drawback is eliminated.

The operation of after recording will be explained below.

Before that, this signal processing device 10 includes at least two function switches 120, as shown in FIG.
122 is provided. One is a mode switch and the other is a shutter switch.

The mode switch 120 is for selecting whether the screen to be inserted is single or continuous, and the shutter switch 122 is for selecting the screen to be inserted, whether it is an inserted screen or a single shot. .

When performing after-recording on Audio I No. 8, the insertion screen remains as it is, so put DA'r in the playback mode, monitor the screen, and when the screen you want to perform after-recording appears, switch to after-recording mode.

Writing and reading from the memories 62 and 64 are repeated alternately, but when performing after-recording of audio signals, the switching state is fixed.

For example, if the after-recording mode is selected while image data in the memory 62 is being monitored, the image data in the memory 62 is constantly monitored, while the image data in the memory 64 is ready to be recorded on the DAT.

The image data in memories 62 and 64 do not match in most cases. On the other hand, since the operator performs the after-recording operation while looking at the monitor screen, the monitor screen during after-recording is different from the screen that can actually be re-recorded by after-recording.

To eliminate this problem, it is sufficient to match the image being monitored with the image to be recorded when in the after-recording mode.

Therefore, in terms of hardware, a changeover switch 58 for after-recording is provided.

The after recording mode will be explained with reference to FIG.

It is assumed that the changeover switches 66 and 68 are switched to the state shown in FIG. 1 (FIG. 9F).

The write enable signal W is used to prevent the identification code ID added to the digital video signal DSV from being lost to memory.
”T is output (A, C in the same figure).

When the cue code LS/ID is detected among the identification codes ID, an address clear signal is output (B in the same figure).
. When the shutter switch 122 is pressed while the memory 64 is in the writing state (D in the figure), the control circuit 100 determines that it is the after-recording mode, and the memory means 60
fixes the operation mode to the previous operation mode.

Then, the after-recording switch 58 is switched to the terminal C side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is increased from 2 fs to 3 fs.
(E in the same figure). Then, the image data in the memory 62 is supplied to the memory 64 via the after-recording switch 58, and is rewritten at high speed.

Now, the image data in the memories 62 and 64 match, and the monitor screen and the image data to be recorded match.

When writing is completed, the write enable signal W for the memory 64 is inverted, and image data cannot be written thereafter. After recording switch 58
automatically returns to its original state, and the terminal dl! (G in the same figure). The after-recording mode can be canceled by pressing the shutter switch 122 again during playback or by switching the mode switch 120 to the continuous side.

With the above configuration, audio signal Sa and video signal 8
No. Sv can be adapted and mixed with the current audio format. In this case, although the number of quantizations of the audio signal Sa is reduced from the current 16-bit configuration to a 10-bit configuration, there is little deterioration in sound quality due to this decrease in the number of quantizations. Furthermore, since the video is a still image, 6-bit quantization is sufficient.

When the digital signal DS, which is a mixture of the audio No. 43 Sa and the video signal Sv, is to be played back using the current DAT, that is, as shown in No. 10 When the video signal DSv is reproduced as the digital audio signal DSa, there is almost no influence on the audio decoding Sa.

In that case, video {No. 8 S
v is nothing but a noise precept. However, as is clear from FIG. 2C, since the digital video signal DSv is inserted into the lower bit side of the digital audio signal DSa, the audio signal Sa can have a dynamic range of about 6NdB.

Therefore, as mentioned above, if the quantization number N is selected to be about 10 bits, compact cassette, Dolby B (
quotient! ) The dynamic range is comparable to recording and playback. For this reason, even if the video compensation code Sv is not played back at the same time, there is almost no impact on the audio compensation code Sa, and there is little deterioration in sound quality.

As in the 21st mD, the least significant bit data of the digital video signal DSv■0 is the digital audio signal DSa
If the bit combination position is reversed so that the least significant bit data AO is on the side, the influence on the audio signal Sa can be practically ignored.

The after-recording process is an example of after-recording an audio signal, but it can also be configured to after-record a video signal.
It is also possible to configure so that any one of them can be selected.

In the above description, T=16, N=10, and M=6, but as mentioned above, the values of N and M are not limited to these.

[Effect of the invention] As explained above, according to the invention, audio {
In addition to the δ signal, when recording and reproducing video signals such as still images at the same time, the two are mixed in accordance with the DAT audio format.

In that case, compatibility with the current model (DAT) can be ensured. Of course, efforts have been made to minimize deterioration in the sound quality of the reproduced audio signal.

Further, the present invention has a feature that it is possible to easily correct discrepancies in content between the monitor screen and the re-recorded screen that occur during the after-recording process.

Therefore, the signal processing device according to the present invention is extremely suitable for use as an accessory device such as a DAT for events.

[Brief Description of the Drawings] Fig. 1 is a system diagram showing an example of a signal processing device for digital signals according to the present invention, Fig. 2 is a block diagram showing an example of an audio format of digital signals, and Figs. The figures are an explanatory diagram of the identification code, Fig. 8 is an explanatory diagram of the bit inversion processing of the digital video number δ, Fig. 9 is a waveform diagram of the after-recording process, and Fig. 10 is a system diagram showing an example of the current DAT. It is. 1 0 20 36 58 60 ・ 76 ・ 80 ・ 82. 90 ・ 92 ・ 94 ・ Sa ・ DSa ・ Sv ・ DSv ・ ・Signal processing device・Mixing means・Separating means・After recording switch・Video signal memory means・Sync bit shift encoder・Identification code generator・Ig processing circuit・Sync bit shift decoder ・Identification code detection circuit ・Audio Ig number ・Digital audio signal ・Video signal ・Digital video signal

Claims (1)

[Claims] (1) A digital device in which the upper N bits (N is an integer) are used as an audio signal, the lower M bits (M is an integer) are used as a video signal, and this video signal is added to the audio signal or separated from the audio signal for signal processing. In a signal processing device for a signal, when performing after-recording of an audio signal or a video signal while monitoring a reproduced video signal, a memory means having at least one pair of memories functioning for time axis conversion of the video signal; An external terminal for monitoring the video signal read out from the memory means, and an input selector switch located on the input stage side of the memory means and operated in the after-recording mode are provided, and the selector switch is provided with an input switch for monitoring the video signal read out from the memory means. and a playback video signal read out from the memory means, and when an after-recording mode is selected, the playback video signal is stored in the other memory, and the video signal to be recorded is used for monitoring. A signal processing device for a digital signal, characterized in that the signal processing device matches a video signal.