JPH03141773A - Sample/hold circuit device - Google Patents

Abstract

PURPOSE:To widely improve the S/N of a sample/hold output signal by executing cascade connection to the two pairs of sample/hold circuit devices at least and executing the sample/hold of an input signal successively by each sample/ hold circuit device. CONSTITUTION:When gain G to be required by the whole circuit is 4, for example, the sample/hold circuit obtains two-step configuration and accordingly, gains G1 and G2 of amplifier circuits 301 and 311 are set while being equally shared like G1=2 and G2=2, for example. A signal S2, to which the sample/hold is executed by a device 31 in the rear step, is equal to four-times amplify the direct current level of a picture read signal I2. In respect to this case, for noise NZ caused by sampling clocks phiSP1 and phiSP2, only the noise NZ caused by the phiSP2 is amplified to be double. Thus, the level of the noise NZ is decreased to be half and the S/N is widely improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sample-and-hold circuit device that samples and holds an image read signal of an image sensor.

[Conventional Sampling Technique 1] Conventionally, as a sample-and-hold circuit device for sampling the DC level of the image reading signal of an image sensor, etc., a circuit as shown in the Bronk diagram of FIG. 3 has been generally used. Ru.

This circuit device 1 is synchronized with the reading timing of each reading pixel, assuming that the image sensor 2 is composed of a one-dimensional image sensor in which 11 reading pixels (11≧2) are arranged in the main scanning direction of the original image. a sampling clock generation circuit 10 that generates a sampling clock ΦSP3 generated from this circuit 10; a sample hold circuit 11 that samples and holds an image reading signal I2 of the image sensor 2 at the generation timing of the sampling clock ΦSP3 generated from this circuit 10; It is comprised of an amplification circuit 12 that amplifies the sample and hold output signal S3 and sends it to the outside as an output signal A3.

FIG. 4 is a time chart showing the human output signal waveform of each part, and from the image sensor 2, as shown in 4121(a), the broken line is the black level, the - dotted line is the white level, and the image of each read pixel is An image reading signal (2) having a DC level corresponding to the density is output in synchronization with each reading timing of the reading pixels in the main scanning direction. Note that the rectangular waveform portion RNZ where the DC level is higher than the black level shown by the broken line is a predetermined pulse for emptying the image reading signal I2 of the previous pixel accumulated as a charge in the reading element of each pixel. This is reset noise caused by a width reset signal (not shown).

In this way, the image reading signal I2 output from the image sensor 2 is output from the sampling clock generating circuit 10 at a timing that takes into account the charge accumulation time for the reading (signal 2) to reach a DC level corresponding to the density of the original. The sampling clock ΦS+"11, as shown in FIG. 4 (1), which is output at a period of
The sample is held. As a result, the sample-and-hold circuit 11 outputs a sample-and-hold output signal S3 at the DC level shown in FIG. 4(c) for each read pixel. This sample hold output f3 No. S3 increases! The width circuit 12 amplifies the quotient level output signal 'iA3 as shown in FIG. 2(d) and sends it to the outside.

[Problem to be Solved by the Invention 1] In the sample and hold circuit device as described above, if the density of the original is the same, the DC level of the image reading signal will change to the white level in proportion to the brightness of the light source illuminating the original image. It gets bigger on the side. Therefore, when a low-intensity light source such as a light-emitting light source is used as a light source in order to reduce the size and weight, the DC level of the image reading signal 9I2 will not be sufficiently high. Therefore, the gain of the amplifier circuit 12 must be made sufficiently large in order to perform stable image processing on the external device side that receives the signal A3 of the amplifier circuit 12.

This is the same even when the reading speed is increased.

In other words, when the reading speed is increased, the charge accumulation time in each pixel is shortened, so even if the original density is the same, the reading signal ■2's DC The level becomes smaller.

Therefore, when using a low-intensity light source as a light source or when performing high-speed reading, the gain of the amplifier circuit 12 must be made sufficiently large.

However, in this type of sample-and-hold circuit device 1, an impulse-like signal as shown in FIG. It is generally known that is NZ appears. Therefore, when the gain of the amplifier circuit 12 is increased, the noise NZ is also amplified by the same gain, and as shown in FIG. 4(d), it becomes too large to be ignored when performing image processing.

That is, the quality of the output signal A3 is equal to the sampling clock ΦS
There is a problem that the S/N ratio deteriorates due to the noise NZ caused by P3. As a result, in a device that receives the small force signal Aj and performs image processing, etc., a problem arises in that the reading image quality deteriorates. In order to realize luminous flux reading, a Kuto response is possible as the amplifier circuit 12.
In addition, since a 1M high-gain multiplication element is used, a problem arises in that the cost of the circuit device 1 increases.

The present invention was made in view of the problems of the prior art as described above, and its purpose is to improve the S/N ratio of the sample-and-hold output signal caused by the sampling clock in a sample-and-hold circuit device that requires high gain. It is an object of the present invention to provide a sample and hold circuit device that can perform stable signal processing such as image processing.

[Means for Solving the Problem 1] In order to achieve the second object, the sample-and-hold circuit device of the present invention includes a sample-and-hold circuit that samples the DC level of an input signal at the generation timing of a sampling clock, and a sample-and-hold circuit that samples the DC level of an input signal at the generation timing of a sampling clock. At least two sample-and-hold circuit units that operate as an amplification circuit for the output signal of the circuit are connected in cascade. Furthermore, a sampling clock generation circuit that generates a sampling clock with a phase corresponding to the phase of each sample-and-hold circuit unit is installed, and the DC level of the human input signal is sequentially sampled by each sampling circuit unit, and the final stage sampling circuit unit The configuration is such that the output number M of the 7F is sent to the outside as a sample and hold signal.

[Function] Of at least two cascade-connected sample and hold circuit units, the latter sample and hold circuit unit converts the sample and hold output signal of the previous sample and hold circuit unit into a sampling clock with a phase corresponding to the connection stage of its own unit. Hold the sample. That is, the output signal of the previous stage sample and hold circuit unit is sampled and held during the hold operation period after the sample and hold timing of the 19 stages.

As described in +iii, the noise NZ in the sample hole signal caused by the sampling clock appears at the rising and falling timings of the sampling clock. Therefore, the sample-and-hold circuit fjf5 unit in the t& stage samples and holds the output signal of the previous-stage sample-and-hold circuit unit during its hold period, so that the noise NZ contained in the previous-stage output signal is transferred to the subsequent-stage sample-and-hold circuit unit. Not carried over. Therefore, the sample bold circuit unit in the subsequent stage samples and holds only the signal component of the output signal in the previous stage.

Therefore, if the gain of the amplifier circuit in each sample-and-hold circuit unit is set to share the gain required by the entire circuit device, then from the sample-and-hold circuit unit in the subsequent stage,
Only the signal components are amplified with the required gain and output. In this case, /irNZ is also included in the output signal of the subsequent stage, but since the gain of the amplifier circuit is smaller than that of the conventional one, the level ratio to the signal component becomes significantly smaller.

This greatly improves the S/N ratio of the sample-and-hold output signal that is finally sent to the outside.

[Example 1 Examples of the present invention will be described below.

FIG. 1 is a pronk diagram showing an embodiment of the sample bold path V device according to the present invention, which is applied to a configuration in which the image reading signal Zr2 of the image sensor 2 is sampled and held in the same manner as in FIG. There is. In the same figure,
The sample bold circuit device 3 of this embodiment includes cascade-connected sample and hold circuit units 30 and 31, and sampling clocks ΦSr'l, ΦSP2 of phases corresponding to the connection stages of these circuit units) 30 and 31.
The image sensor 2's image (2 read signal 2) is input to the sample and hold circuit unit 30 at the previous stage.

Each sample and hold circuit unit 30.31 includes a sample bold circuit 30 that samples the input signal at the generation timing of the sampling clocks φspt and φSP2.
0, 310 and these circuits 300.

It is comprised of amplification circuits 301 and 31.1 that amplify output signals S 1 and S 2 of 310, respectively.

Next, read the image (by referring to the time chart in Figure 2).
The sampling operation of No. g ■2 will be explained.

First, as shown in FIG. 2(, ), the image sensor 2 has a black level indicated by a broken line and a self-level indicated by a dashed-dotted line, and an image read signal I2 having a DC level corresponding to the image density of each read pixel is transmitted during main scanning. It is output in synchronization with each reading timing of the reading pixels in the direction.

This image reading signal I2 is sent to the sample hold circuit 300 of the sample hold circuit unit 30 in the previous stage.
The sample is held at the timing of occurrence of the sampling clock φSPI shown in FIG. 2 (1)). This results in
The sample and hold circuit 300 outputs a sample and hold output signal S1 as shown in FIG. 2(c).

This sample-and-hold output signal S1 is amplified by the amplifier circuit 301, becomes an output signal AI shown in FIG.

The sample and hold circuit 310 receives the signal AI input from the sample and hold circuit unit 30 in the previous stage as shown in FIG.
Sample and hold is performed by the sampling time a7 and ΦSP2 shown in e). As a result, the sample hold circuit 310 outputs the sample rehold output signal S2 shown in FIG.

In the mini, the sampling clock ΦSP2 is generated at the timing when the generation period of the sampling clock ΦSPI for the sample and hold circuit unit 30 of the part 91 ends and before the next pixel sampling period starts. Therefore, the sample and hold circuit 310 at the subsequent stage holds the output signal A1 of the sample and hold circuit unit 30 at the previous stage during its hold operation period. That is, the sample and hold circuit 310 at the subsequent stage is 111
The output of the j-stage sample and hold circuit unit 30 (=
Regarding '+A1, h of the signal component excluding /irNZ is sampled and held.

The signal S2 sampled and held in this way increases by 1
It is amplified by the width circuit 311 and outputted to the outside as an output signal A2 shown in FIG. 2(g).

As mentioned above, sampling circuit 3] () is +1ijLl
Output No. 3 S1 of sample hold circuit unit 30
In order to sample and hold only the signal component of , the noise NZ caused by the sampling clock ΦS1]1 for the sample and hold circuit unit 30 in the previous stage is not carried over to the sample and hold circuit 310 in the subsequent stage. Therefore, the output signal A2 of the sample and hold circuit unit 31 in the subsequent stage is
The /isNZ included in is only due to the sampling clock signal ΦSPl of the current stage.

Here, if the gain G required for the entire circuit is G = 4, for example, the sample rehold circuit unit is a two-stage MIIr.
&, the amplifier circuit 3 (gain G 1 of 11,311
, G 2 are, for example, G ,= 2 , G 2=
2 will be divided equally.

Then, the sample and hold circuit unit 131''
C sample held signal S2 is image reading signal ■
The DC level of 2 is amplified by 4 times. On the other hand, the noise NZ caused by sampling clocks φSP1 and φSP2 is the same as the noise NZ caused by φS 112.
only is amplified by a factor of two. Therefore, compared to the conventional configuration, the level of noise NZ is reduced to 172, and the S/N ratio is significantly improved. In this case, the gain G1 of the sample and hold circuit unit 30 in the previous stage is set to G,=4,
If the latter stage is set as G2=1, the total gain G as a whole is G=4, but since the noise NZ at tj in the subsequent stage circuit unit 31 is only amplified by G2=1,
The level of noise NZ in the output signal A2 is 1/4 of that in the US.
decreases to

In other words, the noise NZ caused by the sampling clock
Since only the noise of the sample-and-hold circuit unit in the final stage is amplified, the S/N ratio improves as the gain distribution to the 411-stage circuit unit increases and the gain of the latter stage approaches 1. .

As a result, the output signal A2 is received and image processing etc.
In position C, the improved S/N ratio makes it possible to perform signal processing such as stable image processing and obtain high-quality read images.

In addition, in the case where high-speed reading is to be realized, by distributing and allocating the required total gain G to the amplifier circuits 301 and 311, the gain that each amplifier circuit 301 and 311 should bear becomes smaller. Therefore, even a low-speed amplifier circuit element can be operated in its high-speed operation range.

That is, since it becomes possible to use low-speed amplifier circuit elements, the cost of the circuit VC device 3 can be reduced.

If the low-speed amplifier circuit element is made of paper, it will not respond sensitively to the sampling clock ΦSPI, Φ51)2 or disturbance noise, so the output 4:'
l A 2 S/N ratio is improved.

In addition, the number of connection stages of the sample and hold circuit unit is two in the embodiment described in -, but if the number of stages is further increased, the overall gain can be increased. The variety of light sources that can be used as a light source is also richer, increasing the degree of freedom in design.

In the above embodiment, the output signal of the image sensor 2 is input as the human input signal, but the present invention is not limited to this, and can be applied to a circuit device that samples and holds the DC level of the output signal of various sensors. be able to.

Further, although the sample-and-hold circuit unit is illustrated as having two stages, three or more stages may be configured in consideration of overall gain, processing speed, etc.

[Effect of the Invention 1] As explained above, in the present invention, at least two sets of sample and hold circuit units are connected in cascade in a sampling and hold circuit that requires a high overall gain, and a human input signal is transmitted to each sample and hold circuit unit. Since the configuration is configured to sample and hold sequentially, the S/F of the sample and hold output signal caused by the sampling clock is
The N ratio can be greatly increased. In particular, S/N
The ratio can be improved as the overall gain becomes higher. In addition, it is possible to increase the gain distribution to the 114-stage sample-and-hold circuit unit side and bring the gain to the subsequent stage closer to 1.
The N ratio can be improved.

In addition, by distributing and allocating the total gain to multiple sample-and-hold circuit units, the gain borne by each circuit unit becomes smaller, so even low-speed amplifier circuit elements can be operated in the luminous flux operation region. The cost of the circuit device can be reduced by one pressure.

Furthermore, since it has become possible to use a low-speed amplifier circuit element, it no longer responds sensitively to disturbance noise, etc., so that a stable output signal can be obtained.

Furthermore, since the overall gain can be varied over a wide range, the range of DC levels of the input signal 9 that can be sampled and held is expanded, increasing the degree of freedom in design and the range of use.
This has the effect of increasing the degree of mountain.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation of the embodiment of Fig. 1, and Fig. 3 is a diagram of a conventional sample and hold circuit device. FIG. 4 is a time chart for explaining the conventional device shown in FIG. 3. 1.3...Sample and hold circuit device 2...Image sensor 30.31...Sample and hold circuit unit 32.
...Sampling black 7 generation circuit 0.3 0...Sample hold circuit 1.3 ...Amplification circuit

Claims (3)

[Claims] (1) A sample-and-hold circuit device that samples and holds the DC level of an input signal, consisting of a sample-and-hold circuit that samples the DC level of the input signal at the timing when a sampling clock is generated, and an amplifier circuit that amplifies the output of this sample-and-hold circuit. At least two sets of sample-and-hold circuit units are connected in cascade, and a sampling clock generation circuit is provided to generate a sampling clock with a phase corresponding to the connected stage of each sample-and-hold circuit unit, and the DC level of the input signal is determined by each sampling circuit unit. A sample-and-hold circuit device that samples sequentially and sends the output signal of the final stage sampling circuit unit to the outside as a sample-and-hold signal. (2) A claim characterized in that the gain of the amplifier circuit is set such that the gain of the amplifier circuit in the sample-and-hold circuit unit in the previous stage is set larger than that in the final stage, and the gain of the amplifier circuit in the final stage is set to 1. The sample-and-hold circuit device according to item 1. (3) The sample-and-hold circuit device according to claim 1 or 2, wherein an output signal of an image sensor is input as the input signal.