JPH03141670A - gate array - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 〔overview〕 Regarding gate arrays, especially their basic cells.

The purpose is to provide a basic cell structure that allows simple wiring of parallel connections and cross connections of gate electrodes.

(1) It has a basic cell of a gate array in which two device regions in which two FETs are connected in series are arranged in parallel on the substrate, and the basic cell is common to both device regions. Then, two gate electrodes are formed.

The two gate electrodes are configured to be divided at positions shifted in opposite directions from their respective centers.

(2) An auxiliary wiring pattern is provided between the two gate electrodes.

(3) It has a basic cell of a gate array in which two device regions in which two FETs are connected in series are arranged in parallel on one substrate, and the basic cell is common to both device regions. Two gate electrodes are then formed.

The two gate electrodes are configured to be divided at positions shifted in the same direction from their respective centers.

(Industrial application field) The present invention relates to gate arrays, and in particular to their elementary cells.

A gate array is a semi-custom semiconductor integrated circuit device manufactured by forming transistors on a semiconductor chip in advance and forming a wiring pattern according to the desired circuit, and has become widely used as systems become more diverse. Ta.

[Conventional technology]

As a conventional basic cell structure of a gate array, the pattern shown in FIG. 7 has been widely used.

FIGS. 7(1) to 7(3) are plan views showing examples of patterns of basic cell structures according to conventional examples.

In the figure, gate electrodes 1. IA, IB
Two sets of two FETs (QIA, QIB, and QZA+021) connected in series are formed on the board by the element regions 3 and 4 in which two FETs are connected in series, as shown by 9 dotted lines, 2, 2A, and 2B. arranged in parallel.

In FIG. 7(1), 1 and 2 are gate electrodes, and 34 is an element region.

In this cell, gate electrodes 1 and 2 are the left and right FETs, respectively.
This is a pattern in which gate electrodes are connected in parallel.

In FIG. 7 (2), LA, IB, 2 are gate electrodes.

3.4 is an element area.

In this cell, the gate electrodes IA and IB are divided into left and right FETs, and the gate electrode 2 is common to the left and right FETs.

In Figure 7 (3), IA, IB, 2A, 2
B is a gate electrode, and 3 and 4 are element regions.

Gate electrodes of this cell are formed independently for each of the four FETs.

[Problem to be solved by the invention]

In the cell shown in FIG. 7(3), it is difficult to cross-connect the gate electrodes shown in the equivalent circuit shown in FIG. 8, and as a result, the wiring on the basic cell is often complicated.

That is, when cross-connecting, conventionally, instead of crossing the gate wires, the power supply wires on one side of the FET QIA, 0.8 or 02A+021 in FIG. 8 were replaced. As a result, the wiring may become extremely complicated.

In this case, the cell wiring spacing is approximately several μm.

All wiring is done in a single layer of aluminum, and the wiring direction is inside the cell, so it is in the vertical and horizontal directions. In addition.

The gate electrode is a polysilicon film.

SUMMARY OF THE INVENTION An object of the present invention is to provide a basic cell structure that allows simple wiring of parallel connections and cross connections of gate electrodes.

(Means for Solving the Problem) The solution to the above problem is to have a basic cell of a gate array in which two element regions each having two FETs connected in series are arranged in parallel and facing each other on a substrate. , the basic cell is a gate array in which two gate electrodes are formed in common on both element regions, and the two gate electrodes are divided at positions shifted in opposite directions from the center of each, or , the basics of a gate array in which an auxiliary wiring pattern is provided between the two gate electrodes, or a gate array in which two element regions in which two FETs are connected in series are arranged in parallel and facing each other on a substrate. The basic cell has two gate electrodes formed in common on both element regions, and the two gate electrodes are divided at positions shifted in the same direction from the center of each. Achieved by gate array.

[Function] The present invention divides the two gate electrodes of the basic cell at positions offset from their respective centers, and further provides an auxiliary wiring pattern between the gate electrodes, as shown in FIG. 2.4.6. As shown, detour wiring is avoided as much as possible, and gate electrodes can be connected in parallel and cross-connected with simpler wiring than the conventional example.

〔Example〕

FIG. 1 is a plan view showing a pattern of a basic cell structure according to an embodiment of the first invention.

Similar to the conventional example shown in FIG. 7(3), gate electrodes 18, 1B, 2A, 2B shown by solid lines and element regions 3, 4 in which two PETs are connected in series, shown by dotted lines, are used. On the substrate, two sets of FETs (h+QI11 and Qza, Qzm) connected in series are arranged in parallel and facing each other.

In this case, cell gate electrodes are formed independently for each of the four FETs.

The difference from the conventional example shown in FIG. 7(3) is the gate electrode IA.

The dividing position 5 of IB and the dividing position 6 of gate electrodes 2A and 2B are shifted in opposite directions from their respective centers.

FIGS. 2(1) and 2(2) are plan views showing an example of connection of basic cells in the embodiment of the first invention.

FIG. 2(1) shows parallel connection of gate electrodes, and FIG. 2(2) shows cross-connection wiring.

As shown, parallel connections are possible as before, and cross-connections are simpler than before.

FIG. 3 is a plan view showing a pattern of a basic cell structure according to an embodiment of the second invention.

Similarly to FIG. 1, the gate electrode IA is indicated by a solid line.

Two sets of two PETs (QIA, QlB and 028,0 □8) are arranged in parallel and facing each other.

The difference from FIG. 1 is that an auxiliary wiring pattern 7 is formed at an intermediate position between gate electrodes IA, IB and gate electrodes 2A, 2B.

FIGS. 4(1) and 4(2) are plan views showing an example of connection of basic cells in the embodiment of the second invention.

FIG. 4(1) shows parallel connection of gate electrodes, and FIG. 4(2) shows cross-connection wiring.

As shown in the figure, parallel connections are possible in the same manner as before, and cross connections are made simpler than in FIG. 2 through the auxiliary wiring pattern 7.

FIG. 5 is a plan view showing a pattern of a basic cell structure according to an embodiment of the third invention.

Similar to the conventional example shown in FIG. 7(3), the gate electrodes l^, IB, 2A, 2B shown by solid lines and the element region 3.4 in which two FETs are connected in series, shown by 5-dot lines, , two sets of two FETs (Q
IA, Q + m and Q09 mouth 2. ) are arranged parallel to each other.

In this case, cell gate electrodes are formed independently for each of the four FETs.

The difference from FIG. 7 (3) of the conventional example and FIG. 1 of the first invention is that the dividing position 5 of the gate electrodes IA and IB and the dividing position 6 of the gate electrodes i2A and 2B are the same from the center of each. This is a point that is deviated in the direction.

FIGS. 6(1) and 6(2) are plan views showing an example of connection of basic cells in the embodiment of the third invention.

FIG. 6(1) shows parallel connection of gate electrodes, and FIG. 6(2) shows cross-connection wiring.

As shown, parallel connections are possible as before, and cross-connections are simpler than before.

In this way, the wiring pattern becomes simple in any of the embodiments.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a basic cell pattern in which parallel connections and cross connections of gate electrodes can be easily wired, and the wiring pattern can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a pattern of a basic cell structure according to an embodiment of the first invention. FIGS. 2(1) and 2(2) are plan views showing connection examples of basic cells in the embodiment of the first invention. FIG. 3 is a plan view showing a pattern of a basic cell structure according to an embodiment of the second invention. FIGS. 4(1) and 4(2) are plan views showing connection examples of basic cells in the embodiment of the second invention. FIG. 5 is a plan view showing a pattern of a basic cell structure according to an embodiment of the third invention. FIGS. 6(1) and 6(2) are plan views showing connection examples of basic cells in the embodiment of the third invention. FIGS. 7(1) to 7(3) are plan views showing examples of patterns of basic cell structures according to the prior art. FIG. 8 is an equivalent circuit of cross-connected basic cells. In fig. 1. IA, IB, 2.2A, 2B are gate electrodes. 3.4 is an element area where two FETs are connected in series. 5.6 is the dividing position of the gate electrode. 7 is the auxiliary wiring pattern. QIAIQII+ and 0□4,0□3 are engravings of FET drawings. Dark side σ11 Figure 3 2A Drawing ↑ 2nd release/f) and 1st jl B Third embodiment of the invention Figure 5 Procedural amendment □ l. Display of incident Getarray Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (52
2) Fujitsu Ltd. 4, Agent address: 1015-5 Kamiodanaka, Nakahara-ku, Yozaki-shi, Kanagawa Prefecture; Date of amendment order: February 27, 1990 (Shipping mortar)

Claims (3)

[Claims] (1) On a substrate, there is a basic cell of a gate array in which two element regions each having two FETs connected in series are arranged in parallel and facing each other. The basic cell is characterized in that two gate electrodes are formed in common on both element regions, and the two gate electrodes are divided at positions shifted in opposite directions from the center of each. gate array. (2) The gate array according to claim 1, further comprising an auxiliary wiring pattern provided between the two gate electrodes. (3) On the substrate, there is a basic cell of a gate array in which two element regions in which two FETs are connected in series are arranged in parallel and facing each other, and the basic cell is common to both element regions. 1. A gate array characterized in that two gate electrodes are formed, and the two gate electrodes are divided at positions shifted in the same direction from their respective centers.