JPH03137729A - Advanced control system - Google Patents
Advanced control systemInfo
- Publication number
- JPH03137729A JPH03137729A JP27691589A JP27691589A JPH03137729A JP H03137729 A JPH03137729 A JP H03137729A JP 27691589 A JP27691589 A JP 27691589A JP 27691589 A JP27691589 A JP 27691589A JP H03137729 A JPH03137729 A JP H03137729A
- Authority
- JP
- Japan
- Prior art keywords
- instruction buffer
- interruption
- instruction
- interrupt
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 claims abstract description 41
- 238000011094 buffer selection Methods 0.000 claims abstract description 19
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Advance Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は命令実行の先行制御に関し、特に割込み発生時
の先行制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to advance control of instruction execution, and particularly to a advance control method when an interrupt occurs.
従来、先行制御方式は単一レベルの命令バッファで動作
しており、割り込みが発生して割込み処理が実行された
後、割込み処理からの復帰後の処理(アプリケーション
プログラム等)実行時に命令バッファに先取りしていた
命令を消し、命令バッファに命令を取り込み直していた
。Conventionally, the preemptive control method operates with a single-level instruction buffer, and after an interrupt occurs and the interrupt processing is executed, prefetching is performed in the instruction buffer when executing a process (such as an application program) after returning from the interrupt processing. The command was deleted and the command was reloaded into the command buffer.
上述した従来の先行制御方式では、割込み発生直前に先
取りされていた命令を一度消して割込み処理後に再び取
り込むため、同じ動作を二度繰り返すことになり時間が
かかるという欠点がある。The above-mentioned conventional advance control method has the disadvantage that the instruction that was prefetched just before the interrupt occurs is erased and then fetched again after the interrupt processing, so the same operation is repeated twice, which takes time.
本発明の先行制御方式は、アプリケーションプログラム
実行中における割込みを検出する割込み検出手段と、前
記割込み検出手段によって検出された割込みに対して命
令バッファの切り替えを制御する命令バッファ切り替え
制御手段と、前記命令バッファ切り替え制御手段により
指示さた命令バッファ選択情報により複数個の命令バ・
ソファのどれを使用するかを選択する命令バッファ選択
手段と、割込み処理の終了を検出し割込み直前に使用し
ていた命令バッファへの切り替えを行うことを前記命令
バッファ切り替え制御手段に通知する割込み処理終了検
出手段とを有する。The advance control method of the present invention includes: an interrupt detection means for detecting an interrupt during execution of an application program; an instruction buffer switching control means for controlling switching of an instruction buffer in response to an interrupt detected by the interrupt detection means; Multiple instruction buffers are selected based on instruction buffer selection information instructed by the buffer switching control means.
an instruction buffer selection means for selecting which of the sofas to use; and an interrupt processing for detecting the end of interrupt processing and notifying the instruction buffer switching control means to switch to the instruction buffer used immediately before the interrupt. and end detection means.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示す説明図である、同図に
おいて先行制御方式は、主記憶部1.オペレーテイング
システム2.アプリケーションプログラム3.アプリケ
ーション用命令バッファ4、割込み検出手段5.命令バ
ッファ切り替え制御手段6.命令バッファ選択手段71
割込み処理用命令バッファ81割込み処理終了検出手段
9とから構成されている。FIG. 1 is an explanatory diagram showing one embodiment of the present invention. In the same figure, the advance control method is based on the main storage unit 1. Operating system 2. Application program 3. Application instruction buffer 4, interrupt detection means 5. Instruction buffer switching control means 6. Instruction buffer selection means 71
It consists of an interrupt processing instruction buffer 81 and an interrupt processing completion detection means 9.
主記憶部1上にはオペレーティングシステム2及びアプ
リケーションプログラム3が展開されている。また、ア
プリケーション用命令バッファ4にはアプリケーション
プログラム3の一部の命令が取り込まれている。アプリ
ケーション用命令バッファ4に取り込まれている命令を
実行中に割込み検出手段5が割込みを検出し、命令バッ
ファ切り替え制御手段6へ通知する。An operating system 2 and application programs 3 are developed on the main storage unit 1 . Further, some instructions of the application program 3 are taken into the application instruction buffer 4. Interrupt detection means 5 detects an interrupt while executing an instruction loaded in application instruction buffer 4, and notifies instruction buffer switching control means 6.
割込み検出通知を受けた命令バッファ切り替え制御手段
6はどの命令バッファに切り替えるかを示す命令バッフ
ァ選択情報を命令バッファ選択手段7に通知する。命令
バッファ選択手段7は命令バッファ切り替え制御手段6
から通知された命令バッファ選択情報に基づいて割込み
処理用命令バッファ6に切り替える0割込み処理は割込
み処理用命令バッファ8を使用して実行される。Upon receiving the interrupt detection notification, the instruction buffer switching control means 6 notifies the instruction buffer selection means 7 of instruction buffer selection information indicating which instruction buffer to switch to. The instruction buffer selection means 7 is the instruction buffer switching control means 6.
0 interrupt processing is executed using the interrupt processing instruction buffer 8, which is switched to the interrupt processing instruction buffer 6 based on the instruction buffer selection information notified from the interrupt processing instruction buffer 6.
割込み処理終了時には割込み処理終了検出手段9が割込
み処理の終了を検出し、命令バッファ切り替え制御手段
6に通知する。命令バッファ切り替え制御手段6は割込
み直前に使用していた命令バッファへの切り替え−を示
す命令バッファ選択情報を命令バッファ選択手段7に通
知する。命令バッファ選択手段7は命令バッファ切り替
え制御手段6から通知された命令バッファ選択情報に基
づいて元のアプリケーション用命令バッファ4に切り替
え、割込み発生以降のアプリケーションプログラム3を
実行する。When the interrupt processing ends, the interrupt processing end detection means 9 detects the end of the interrupt processing and notifies the instruction buffer switching control means 6. The instruction buffer switching control means 6 notifies the instruction buffer selection means 7 of instruction buffer selection information indicating switching to the instruction buffer used immediately before the interrupt. The instruction buffer selection means 7 switches to the original application instruction buffer 4 based on the instruction buffer selection information notified from the instruction buffer switching control means 6, and executes the application program 3 after the occurrence of the interrupt.
以上説明したように本発明は、アプリケーションプログ
ラム実行中に割込みが発生したとき命令バッファを切り
替えることにより、割込み処理からのアプリケーション
プログラム復帰時の実行時間が短縮され、結果としてシ
ステムの性能を向上させることができる効果がある。As explained above, the present invention switches the instruction buffer when an interrupt occurs during execution of an application program, thereby shortening the execution time when the application program returns from interrupt processing, and improving system performance as a result. It has the effect of
6・・・命令バッファ切り替え制御手段、7・・・命令
バッファ選択手段、8・・・割込み処理用命令バッファ
、9・・・割込み処理終了検出手段。6... Instruction buffer switching control means, 7... Instruction buffer selection means, 8... Interrupt processing instruction buffer, 9... Interrupt processing end detection means.
Claims (1)
出する割込み検出手段と、前記割込み検出手段によって
検出された割込みに対して命令バッファの切り替えを制
御する命令バッファ切り替え制御手段と、前記命令バッ
ファ切り替え制御手段により指示さた命令バッファ選択
情報により複数個の命令バッファのどれを使用するかを
選択する命令バッファ選択手段と、割込み処理の終了を
検出し割込み直前に使用していた命令バッフアへの切り
替えを行うことを前記命令バッファ切り替え制御手段に
通知する割込み処理終了検出手段とを有することを特徴
とする先行制御方式。an interrupt detection means for detecting an interrupt during execution of an application program; an instruction buffer switching control means for controlling instruction buffer switching in response to an interrupt detected by the interrupt detection means; an instruction buffer selection means for selecting which of a plurality of instruction buffers to use based on instruction buffer selection information; and an instruction buffer selection means for detecting the end of interrupt processing and switching to the instruction buffer used immediately before the interrupt; 1. A proactive control method comprising interrupt processing end detection means for notifying buffer switching control means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27691589A JPH03137729A (en) | 1989-10-23 | 1989-10-23 | Advanced control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27691589A JPH03137729A (en) | 1989-10-23 | 1989-10-23 | Advanced control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03137729A true JPH03137729A (en) | 1991-06-12 |
Family
ID=17576162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27691589A Pending JPH03137729A (en) | 1989-10-23 | 1989-10-23 | Advanced control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03137729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6256720B1 (en) | 1991-07-08 | 2001-07-03 | Seiko Epson Corporation | High performance, superscalar-based computer system with out-of-order instruction execution |
-
1989
- 1989-10-23 JP JP27691589A patent/JPH03137729A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6256720B1 (en) | 1991-07-08 | 2001-07-03 | Seiko Epson Corporation | High performance, superscalar-based computer system with out-of-order instruction execution |
| US6272619B1 (en) | 1991-07-08 | 2001-08-07 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6647485B2 (en) | 1991-07-08 | 2003-11-11 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6915412B2 (en) | 1991-07-08 | 2005-07-05 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6934829B2 (en) | 1991-07-08 | 2005-08-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6941447B2 (en) | 1991-07-08 | 2005-09-06 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6948052B2 (en) | 1991-07-08 | 2005-09-20 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6959375B2 (en) | 1991-07-08 | 2005-10-25 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US6986024B2 (en) | 1991-07-08 | 2006-01-10 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US7162610B2 (en) | 1991-07-08 | 2007-01-09 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
| US7487333B2 (en) | 1991-07-08 | 2009-02-03 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
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