JPH03136366A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a memory cell, which is actuated in a low current, has a high reliability, has a high efficiency and can be driven by a single power supply, by a method wherein the depth of the P-N junction of a first diffused region is made deeper than that of the P-N junction of a second diffused region. CONSTITUTION:An n<+> buried region 2 and a low-concentration n<-> region 3 are laminatedly provided in order on a p-type silicon substrate 1 and an element formation region is partitioned by a field oxide film 4 provided by oxidizing selectively the surface of the region 3. Then, a gate electrode 5 is provided through a gate oxide film provided on the surface of the element formation region, a p-type diffused region 12, which reaches the region 2 aligning to the electrode 5 and has a deep P-N junction, and a p-type diffused region 9 having a shallow P-N junction are provided and a MOS transistor, in which the regions 12 and 9 are used as a source region or drain region, is constituted. On the other hand, an n<+> diffused region 11 is provided in the region 12. Thereby, a bipolar transistor, in which the regions 2 and 3 are used as a collector region, the region 12 is used as a base region and the region 11 is used as an emitter region, is constituted to form a memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a memory cell configured by integrally combining a bipolar transistor and an MO8 transistor.

[Four conventional technologies] As an example of a semiconductor device having a conventional memory cell, 1
988 International Electron Device Meeting (InternationalEle
Paper presented at ctron Device Meeting) A Two Static Memory Cell Based on Reserve Base Current (RBC)
Effect on bipolar transistor (in N
ew 5tatic Memory Ce1l
1lased on ReverseBase
Current (RB C) Effect of
Bipolar Transistor).

FIG. 3 is an equivalent circuit diagram of a memory cell of a conventional semiconductor device, which is composed of a P-channel MO8 type transistor Q and a bipolar type transistor Q2 whose base is connected to each other.

FIG. 4 is a sectional view of a conventional semiconductor device.

As shown in FIG. 4, an N+ type buried region 2 and an N type region 3 are provided on a P type silicon substrate 1, and a field oxide film 4 is selectively provided on the surface of the N type region 3 to form an element. A gate electrode 5 is provided through a gate oxide film provided on the surface of the element formation region, and a P-type diffusion region 10 and a P-type diffusion region 9 are formed in the N-type region 3 in alignment with the gate electrode 5. established,
A MOS transistor is configured in which the P-type diffusion region 10 and the P-type diffusion region 9 serve as a source region or a drain region, respectively. On the other hand, an N++ diffusion region 11 is provided within the P-type diffusion region 10, so that the N-type region 3 is a collector region, the P-type diffusion region 10 is a base region, and the N++ diffusion region 11 is a collector region.
constitutes a bipolar transistor having an emitter region, and includes a wiring 6 connected to the N++ diffusion region 11 in the emitter region, a wiring 8 connected to the P-type diffusion region 9, and an insulating film 7 for electrically separating the wirings. ing.

The function of a memory cell is the potential between the collector and emitter of a bipolar transistor, that is, the voltage at which a large current begins to flow between the collector and emitter when the base is open.
(hereinafter referred to as BVCEO), set to a slightly lower potential than
After the base potential is forcibly set to IV or OV from the outside, when the base is opened, the base potential is automatically set to 1.
Alternatively, it is held at a value of 0 (which may be different from the forcibly applied potential) and has a memory function. Note that the MOS transistor is used to forcibly change the potential of the base region (namely, the P wall region 10) and to read the potential of the base region.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, the base region of the bipolar transistor is shared with the P-type diffusion region 10 of the MOS transistor, and like the P-type diffusion region 9, the junction depth is relatively shallow. ing. Therefore, the current amplification factor of the bipolar transistor is high, about 100. As a result, when the base potential is held near IV, the current flowing to the collector becomes 100 μA to 1 mA, and when a large-scale memory cell is configured, the total current flowing to all memory cells becomes a large current, and as a result, the consumption There is a problem in that the electric power increases and the semiconductor device generates high heat, reducing reliability or causing destruction of the semiconductor device.

For example, in a 64-bit memory device when the collector current is 100 μA, if all memory cells are held near IV, that is, at a level of 1, then the total is 64 k×100 μA = 6
．． A current of 4A will flow, a value that is almost unusable.

In addition, when using a 5■ power supply with a MOS transistor, a bipolar transistor with a conventional structure has a BVC
The disadvantage is that the RO is 8 to 10 cm and two types of power supplies must be supplied, and a single power supply of 5V cannot be used.

[Means to solve the problem]

The semiconductor device of the present invention includes a reverse conductivity type buried region having a high impurity concentration provided on a conductivity type semiconductor substrate, and a reverse conductivity type region having a low impurity concentration provided on a surface including the reverse conductivity type buried region. a field insulating film provided on the opposite conductivity type region to partition an element formation region; a gate electrode provided on a gate insulating film provided on the element formation region; A first diffusion region of one conductivity type having a deep PN junction provided in the element formation region and reaching the buried region; and a second diffusion region of one conductivity type having a PN junction shallower than the first diffusion region. and a third diffusion region of an opposite conductivity type provided within the first diffusion region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

As shown in FIG. 1, N+
A type buried region 2 and a low concentration N-type region 3 are sequentially stacked, and an element forming region is partitioned by a field oxide film 4 formed by selectively oxidizing the surface of the N-type region 3. Next, a gate electrode 5 is provided via a gate oxide film provided on the surface of the element formation region, and a shallow PN junction is formed between a P-type diffusion region 12 having a deep PN junction aligned with the gate electrode 5 and reaching the N+ type region 2. A P-type diffusion region 9 having a P-type diffusion region 12 and a P-type diffusion region 9 are provided as a source region or a drain region to constitute an MO3 type transistor, while an N++ diffusion region 11 is provided within the P-type diffusion region 12. , which gives N
A memory cell is formed by configuring a bipolar transistor in which the + type buried region 2 and the N type region 3 serve as a collector region, the P type diffusion region 12 serves as a base region, and the N++ diffusion region 11 serves as an emitter region.

FIG. 2 is a sectional view of a second embodiment of the invention.

As shown in FIG. 2, the difference from the first embodiment is that the deep P
The diffusion region having the N junction is in two stages. That is, there is a shallow PN junction and a deep PN junction. The shallow PN junction is a P-type diffusion region 13 formed with the same junction depth as the P-type diffusion region 9, but the P-type diffusion region 12, which has a deep PN junction below where the N++ diffusion region 11 is provided, is an N-type diffusion region 12.
A deep junction reaching the + type buried region 2 is formed.

In the second embodiment, compared to the first embodiment, the characteristics of the MO3 type transistor are more stable and the structure is easier to control.

〔Effect of the invention〕

As explained above, the present invention improves the base width of a bipolar transistor using the first diffusion region as a base region by making the PN junction depth of the first diffusion region deeper than the PN junction depth of the second diffusion region. can be made wider, thereby lowering the current amplification factor. In other words, the current amplification factor is reduced to 1
It can be lowered from 1/0 to 1/100. That is, in the aforementioned 64-bit memory device, if the current amplification factor is 1/10, the total current is 640 mA,
Also, if it is 1/100, it will be 64 mA.

In other words, it is possible to realize a memory cell semiconductor device that uses low current, is highly reliable, has high performance, and can be driven with a single power source.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of a memory cell, and FIG. 4 is a conventional semiconductor FIG. 2 is a cross-sectional view of the device. DESCRIPTION OF SYMBOLS 1... P type silicon substrate, 2... N+ type buried region 3... N type region, 4... Field oxide film, 5...
・Gate electrode, 6... Wiring, 7... Insulating film, 8...
・Wiring, 9゜10...P-type diffusion region, 11...N+
+diffusion region, 12.13...P type diffusion region. 1 diagram

Claims (1)

[Claims] an opposite conductivity type buried region with a high impurity concentration provided on a semiconductor substrate of one conductivity type; an opposite conductivity type region with a low impurity concentration provided on a surface including the opposite conductivity type buried region; and the opposite conductivity type region provided on a surface including the opposite conductivity type buried region. a field insulating film provided above to partition an element forming region; a gate electrode provided on a gate insulating film provided on the element forming region; and a field insulating film provided in the element forming region in alignment with the gate electrode. a first diffusion region of one conductivity type having a deep PN junction reaching the buried region; a second diffusion region of one conductivity type having a PN junction shallower than the first diffusion region; and the first diffusion region. A semiconductor device comprising: a third diffusion region of an opposite conductivity type provided within the region.