JPH03135113A - A/d converter - Google Patents

Abstract

PURPOSE:To execute the conversion of an analog voltage at a high speed by starting the conversion when a storage means stores the sampling and holding of an analog voltage and stopping the conversion when the storage means is reset. CONSTITUTION:As soon as an analog voltage is held in a converter 110, it is stored that a set-reset latch 109 is set and the analog voltage is held and a logic gate 120 outputs a logical '1'. A timing control section 126 detects it to control a reference voltage generating section 125 thereby generating a reference voltage for the conversion and the converter 110 starts the conversion. An output of the converter 110 is inputted to a selector 123 and stored in a register 124-1 in the unit of one bit and when the conversion of one analog input is finished, the timing control section 126 outputs a conversion end signal 130, the set-reset latch 109 is reset, the logic gate 120 is logical '0', the timing control section 126 detects it to stop the conversion.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an A/D conversion device.

[Conventional technology]

For a head that reads/writes data from a hard disk or floppy disk, it is usually necessary to perform servo control of the head position in order to add data to a track on the disk. This servo control detects the current head position by sampling the servo pattern recorded in advance between data areas on the track in synchronization with the end of the data area, and calculates the difference from the target dock. Judgment is made and servo control is performed. FIG. 5 shows an example of this servo control. Data tracks 501, 502, 503, 504, 5 where data is recorded
11, 512, 513, and 514 are written concentrically on the disk in advance. The servo buttons are recorded at predetermined intervals from the data area. The head positions are TI, T2. T3. It can be obtained by A/D converting the read signal from the head at timing T4. For example, if the head is at position 520 in FIG. 5 and moves on the broken line, then T
Since the servo pattern is not recorded at the I, T2, and T4 timings, the A/Di conversion result is O port (hereinafter abbreviated as ■). At the T3 timing, the servo pattern is recorded, so the conversion result is 5V. . This shows that the heads are located on tracks 503 and 513. Furthermore, even if the head is located at an intermediate position between tracks, the position can be determined by checking the A/D conversion result.

[Problem to be solved by the invention]

However, the current servo area is about several hundred microseconds, and the width of the servo pattern is about 100 microseconds, but there is a tendency for the servo area to become shorter in order to improve recording density. Therefore, even if there is a time delay in the feedback control of the actual conversion result and there is no problem, the analog voltage changes in a short period of time, so a very high-speed A/D converter (
For example, it requires a flash type A/D converter), making it impossible to use an inexpensive sequential comparison type A/D converter. Flash type A/D converters can usually perform conversion in one timing, but for example, in the case of 8-bit resolution, 28 comparators are required, which is generally very expensive and has a large chip size, making it difficult to use a single-chip microcomputer. It is difficult to incorporate it into devices such as devices. Therefore, a dedicated high-speed A/D converter is placed outside the microcomputer, and its output is received and controlled by an input port or the like. This results in an increase in board area, an increase in the cost of miring on the board, a decrease in reliability, and an unnecessary consumption of ports, resulting in a decrease in the cost performance of the applied system. Furthermore, when converting a plurality of analog inputs at the same timing, it is necessary to arrange a plurality of A/D converters in parallel, which further increases costs.

[Means to solve the problem]

The A/D converter according to the present invention includes a plurality of sample and hold devices for sampling and holding analog voltages, and a storage means for storing sample and hold information corresponding to the plurality of sample and hold devices; and timing control means for starting a conversion operation when at least one of the storage means memorizes that the analog voltage has been sampled and held, and generating a conversion end signal after a predetermined conversion time; The timing control means is set when the analog voltage sampled and held is sampled and held in the corresponding sample and hold device, and is reset in synchronization with the conversion end signal when the sampled and held analog voltage is converted. It is characterized by stopping the conversion operation when is reset.

Therefore, according to the present invention, it is possible to convert an analog voltage that changes in a short time at low cost and at high speed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a sequential comparison type A/D conversion device using the present invention. The A/D converter has analog input terminals 100, 101, 10 for analog input.
2, 103, converters 110, 112, 114, 116 with built-in sample-and-hold circuits and comparators for sampling and holding analog inputs, and set-reset latches 109, 111 for storing sampling. , 113, 115, a reference voltage generator 1 that sequentially supplies a reference voltage to the comparator in the converter;
25. Registers 124-1, 124-2, 124-3, 124-4 that store conversion results corresponding to analog inputs
, a selector 123 for selectively switching the output of the converter and supplying it to the register, a timing control section 126 for controlling the timing of the entire A/D conversion device, logic gates 117, 118, 119, 120, and a delay circuit 132. ,
an edge detection circuit 121 that generates an interrupt request 122;
A bus 127 is provided for transmitting the register output.

FIG. 2 is a detailed diagram of the converter 110 in FIG. 1, with a switch 20 for sampling the analog input 100.
2. Capacitor 200 that holds the sampled voltage
, a comparator 201 that compares the reference voltage 108 generated by the reference voltage generator 125 with a held analog voltage and outputs the comparison result as a logical output.

Since the converters 112, 114, and 116 also have the same configuration, their explanation will be omitted here. The operation of this embodiment will be described below in a state where analog voltages are not sampled and held in all converters.
A case will be described in which an analog voltage applied to 0 is converted. When the analog voltage sampling signal 104 has a logic value 1, the switch 202 is closed and the voltage is held in the capacitor 200. At the same time, the reset latch 109 is set and remembers that the analog voltage is held. - When the reset latch 109 is set, through the delay circuit 132 to prevent malfunction,
Logic gate 120 outputs a logic value of one. The timing control unit 126 detects this and controls the reference voltage generation unit 125 to generate a reference voltage for conversion and apply it to one input of the comparator 201. Comparator 201
A sampled and held analog voltage is applied to the other input of the comparator 201, and when the analog voltage is higher than the reference voltage, the comparator 201 outputs a logical value of 1. The output of the humpator 201 is input to the selector 123, and stored in a register 124-1 that stores the conversion result in units of 1 bit. The selector 123 selects the output of the converter corresponding to the set analog input from among the set-reset latches 109, 111, 113, and 115. Multiple set-transducers 110, 111, 113, 115 if reset latch is set
are prioritized and selected in this order. Since this embodiment uses a sequential comparison method of conversion, the reference voltage generator 125 first generates a voltage that is 1/2 of the reference human power 131, and compares it with the analog voltage sampled by the comparator 201. , the comparison result is transferred to bit 7 of register 124-1 via selector 123. Next, the reference voltage generator 125
generates a voltage equal to 1/4 or 3/4 of the reference input 131, performs a comparison operation, and sends the result to the register 124.
Transfer to bit 6 of -1. By repeating this operation eight times sequentially up to bit 0, the conversion result with 8-bit resolution can be stored in register 124-1. When the 8-bit conversion result is obtained, the timing control section 126 outputs a conversion end signal 130 indicating that the conversion operation of the l analog input is completed, and the set-reset latch 10
9 is reset, and the output of logic gate 120 becomes logic 0.
Therefore, the timing control unit 126 detects this and stops the conversion operation.

Next, we will explain the operation when converting analog input continuously.
This will be explained with reference to the timing chart shown in the figure. Sampling signals 104, 105, 106° and 107 generate timing for sampling analog input.
Here, it is input from outside. When the sampling signal 104 becomes a logic value 1 at timing T30 in the figure, the set-reset latch 109 is set, so the timing control unit 126 detects that the logic gate 120 becomes a logic value 1 and converts it. Start operation. When the conversion is output, the conversion result is stored in the register 124-1, and a conversion end signal 130 is output. At the same time, the set-reset latch 109 is reset, the conversion operation is stopped, and a standby state is entered. At T31 timing, sampling signal 1
Since 05 becomes the logical value l, the set-reset latch 111 is set and the conversion of the analog human power 101 is started. In addition, at the T32 timing, the sampling signal 106 becomes the logical value l, so the voltage of the analog human power 102 is held, but since the conversion of the analog human power 101 has not been completed, the conversion of the analog input 101 ends at the T33 timing. Continue to hold the voltage until T
33 timing, when the conversion by the analog human power 101 is completed, the conversion result is stored in the register 124-2, and the set-reset latch 111 is reset. The output (broken line in the figure) has a logic value of 1, so it is a logic game) 11
8 is inhibited and the set-reset latch 113 is not reset. In other words, logic gates 117, 118, 11
9 is used to prevent multiple set-reset latches from being reset at the same time. Continuing from the T33 timing, the conversion of the analog input 102 continues,
At timing T35, the conversion of the analog input 103 is completed, so the conversion result is stored in the register 124-4.
The falling edge detection circuit 121 of the set-reset latch 115 detects and generates an interrupt request 122.

When the input period of the sampling signal is longer than the conversion time, the A/D converter of the present invention stops the conversion and enters a standby state, and when the input period is short, it continues converting the sampled and held analog voltage. and stops converting once all inputs have been converted.

FIG. 4 shows a second embodiment of the present invention, in which the same input terminal 100
The analog voltage is sampled, and the detailed operation is the same as in the first embodiment, so it will be omitted, but since the number of input terminals can be reduced, it is effective when adopting a small package.

〔Effect of the invention〕

As described above, according to the present invention, analog inputs that change in a short period of time or a plurality of analog inputs at the same timing can be A/D converted at low cost. In this embodiment, the number of sample and hold circuits is set to four, but this number may be further increased and the number of analog input terminals may be increased. Further, an interrupt request is generated when conversion of all inputs is completed, but this may be done every - conversion. Furthermore, instead of inputting the sampling signal from the outside, a timer or the like may be provided in the A/D converter to generate the timing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a detailed diagram of the converter 110 in FIG. 1, FIG. 3 is a timing chart explaining the operation of the first embodiment, and FIG. FIG. 4 is a block diagram of a second embodiment of the present invention, and FIG. 5 is a diagram for explaining a conventional example. 100.101,102,103... Analog input terminal, 104,105,106,107...
・Sampling signal, 109, 111, 113° 115
...Set-reset latch, 11O111
2,114,116...Converter, 123...
...Selector, 125...Reference voltage generation section,
126...timing control section, 127...
・・Bus, 124-1.124-2, 124-3, 12
4-4...Register, 121...Edge detection circuit, 122...Interrupt request, 132...
... Delay circuit, 131 ... Reference input, 117, 118, 119, 120 ... Logic gate, 202 ... Switch, 200 ...
...Capacitor, 201...Comparator.

Claims (1)

[Claims] In an A/D converter including a plurality of sample and hold devices for sampling and holding analog voltages, at least one memory means for storing sample and hold information corresponding to the plurality of sample and hold devices; One storage means starts a conversion operation when it remembers that the analog voltage has been sampled and held;
timing control means for generating a conversion end signal after a predetermined conversion time;
The timing control means is set when the sampled and held analog voltage is sampled and held in the hold device, and is reset in synchronization with the conversion end signal when the sampled and held analog voltage is converted, and the timing control means is set when all the storage means are reset. A/
D conversion device.