JPH03132880A - Image processor - Google Patents

Abstract

PURPOSE:To convert the image memory to a small capacity and to execute the processing at a high speed by providing an image synthesis processing circuit for writing image data which is read in,nd image data existing on the image memory already in the image memory again by taking logical OR. CONSTITUTION:Whenever data of an image 9b of some unit quantity comes from an image input device, data of an image 9a in an image memory is read out by the same quantity, and stored again in the same address in which the image 9a is stored, through a hardware logical OR circuit, by which a composite image 9c of the image 9a and the image 9b is generated, transferred to a host computer 6 through a recognition controller 5, and displayed on a CRT 7. In such a way, an exclusive circuit for synthesizing image data from an image input device and image data on an image memory and storing it in the image memory again is used. Accordingly, the image memory can be converted to a small capacity, and the image synthesis processing can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device with a two-image compositing function.

[Conventional technology]

FIG. 3 is a block diagram of a conventional image processing device.

In the figure, (11 is an image input device that converts the gradation of an image into an electrical signal, and (8) is a recognition unit that performs image processing on image data sent from the image input device (1). , (31, (4), f51.

(6) controls the recognition unit (8) and displays the processed results on cRT f71.

Next, each component of the recognition section (8) will be explained. (2)
・Image memo! J, (3) is an interface circuit that writes the image data sent from the image input device (1) into the image memory (2), and (4) is an interface circuit that performs image processing on the image data on the image memory (2). A recognition processor that does.

(5) is a recognition controller that controls the above f21, (3], (41) and interfaces with the host computer (6). (9) is an image to be processed.

Next, the operation will be explained. The recognition controller (5) and recognition processor (4) in the recognition unit (8) are loaded with a system program from the host computer (6), and the recognition controller (5) is loaded with the system program from the host computer (6). ), the recognition processor (4) is waiting for an activation command from the recognition controller (5). Control of the entire system is performed from a host computer (8). An image to be processed 19) is read from the image input device (1) and written into the image memory (2) by the interface circuit (3). Then the host computer (
6) issues an image processing command to the recognition controller (5), and upon receiving the command, the recognition controller (5) causes the recognition processor (4) to perform image processing on the image data on the image memory (2). The details of the image processing are not directly related to this invention and will therefore be omitted.

The result data processed by the recognition processor (4) is sent by the recognition controller (5) to the host computer (6) and displayed on the CRT (71).

In Figure 3, the already loaded image (9a) has 2
When adding image (9b) to create image (9c).

As shown in Fig. 4, an image (9a) already read in the image memory (2) and an image (9b) read later
are combined by software in the recognition processor (4) to create two images (9C), which are transferred to the host computer (6) through the recognition controller (5) and displayed on the CRT (7).

[Problem to be solved by the invention]

Conventional image processing devices are configured as described above, so when compositing an image that has already been loaded with an image that will be loaded later, the compositing process is performed using software, which takes time, and the loading process is slow. There were problems such as an increase in memory size due to the need for image memory capacity for each image.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an image processing device that performs high-speed compositing processing and has a small capacity image memory.

[Means to solve the problem]

The image processing device according to the present invention combines the contents of image data sent from two image input devices and the contents of image data already existing in the image memory.

It is equipped with a dedicated circuit for storing data in the image memory.

[For production]

The image processing device in this invention combines image data from two image input devices and image data on two image memories,
A dedicated circuit for storing data in the image memory again reduces the capacity of the two-image memory and performs high-speed image compositing processing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (1) is an image input device that converts the gradation of an image into an electrical signal, and (8) performs image processing on the image data sent from the image input device (1).
iW Shikibu Te # (2L (31p (41p (5),
It consists of QOI. (6) controls the recognition unit (8) and displays the processed results on the CRT (71).Next, each component of the recognition unit (8) will be explained. (2) is the image memory, [ is a mode in which the image data sent from the image input device (1) is written as is into the image memory (2), and a mode in which the image data sent and the image already read in the image memory (2) are combined. (4) is the B1i recognition processor that performs image processing on the image data on the image memory (2); and (5) is the above-mentioned image synthesis processing circuit. (
2) Control of the shout (4) and host computer (6)
It is a recognition controller that interfaces with the

(9) is an image to be processed.

Next, the operation will be explained.

In Figure 2, there are two images (9al (9b)),
When creating an image (9c) as a composite image of these two images, first the image (9a) is read from an image input device and stored in an image memory. Next, the second image (9b
) is read from the input device, and the image data of a certain unit amount is stored in the image memory while calculating the logical OR for each unit amount with the image data read previously and stored in the image memory. By reading out the same amount of data of image (9a) in the two-image memory each time data of image (9b) comes, and storing it again at the same address where image (9a) was stored through a hardware logical OR circuit. Composite image of image (9a) and image (9b) @
(9c) is created, transferred to the host computer (6) via the recognition controller (5), and displayed on the CRTf71.

In the above embodiment, two images were explained.

Three or more images can also be realized by repeating the processing for two images, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, an image synthesis processing circuit is provided which performs a logical OR operation on the image data read from the image input device and the image data already existing on the image memory, and writes the resultant data back into the image memory. Therefore, the capacity of the two-image memory can be reduced and processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the operation of an image processing apparatus according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional image processing apparatus. ,
FIG. 4 is a diagram showing the contents of an image memory in the operation of a conventional image processing apparatus. In the figure, (1) is an image input device, (2) is an image memory, (3) is an input device interface circuit, and (4) 1
yo recognition processor, f5) is recognition controller, (6
) is a host computer, (7) is a CRT, +81 is a recognition unit, (9) is an image to be processed, and 00) is an image synthesis processing circuit. Note that the same reference numerals in the two figures indicate the same or equivalent parts.

Claims (1)

[Claims] An image input device that reads the target image as binary data of black and white, synthesizes the read image data and the image data on the image memory, stores it in the image memory again, and displays the contents. In the image processing device, an image to be synthesized is read again by the image input device with respect to the image data already read into the image memory by the image input device, and the image data and the image stored in the image memory are combined. An image processing device characterized by having a function of creating composite image data on an image memory by ORing data for each unit dot, and transmitting and displaying the composite image data to three host computers.