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JPH03132066A - Transistor module for power conversion device - Google Patents

Transistor module for power conversion device

Info

Publication number
JPH03132066A
JPH03132066A JP1271101A JP27110189A JPH03132066A JP H03132066 A JPH03132066 A JP H03132066A JP 1271101 A JP1271101 A JP 1271101A JP 27110189 A JP27110189 A JP 27110189A JP H03132066 A JPH03132066 A JP H03132066A
Authority
JP
Japan
Prior art keywords
terminal
transistor
conductor
container
power conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1271101A
Other languages
Japanese (ja)
Other versions
JP2580798B2 (en
Inventor
Kiyoshi Iida
飯田 清志
Yoshitaka Fujiwara
藤原 喜隆
Hiroshi Miki
広志 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1271101A priority Critical patent/JP2580798B2/en
Publication of JPH03132066A publication Critical patent/JPH03132066A/en
Application granted granted Critical
Publication of JP2580798B2 publication Critical patent/JP2580798B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To enable load to be applied on each element to be connected in parallel uniformly by performing wiring so that the length of a connection conductor, between each semiconductor element which is connected in parallel and an external terminal, is nearly constant. CONSTITUTION:Connection conductors 31A-34A and 31B-34B are fixed onto a container bottom part 11 through an insulation printed-circuit board 2. The electrode of each semiconductor chip is connected to each connection conductor. Namely, one of the conductors connecting the emitter terminal 61 to respective transistors Tr41A-41D is connected to a terminal 61 from the middle point between the points at which the emitters of both Tr41A and 41B are connected with the conductor 31A, while the other is connected to the terminal 61 from the middle point between points at which the emitters of transistors 41C, 41D are connected with the conductor 31B. In this case, these connection conductors should be of the same length. Thus, inductance from the terminal 61 to each transistor due to the connection conductor is nearly equal.

Description

【発明の詳細な説明】 ご産業上の利用分野〕 本発明は、トランジスタと、それらを保護するための非
対称素子およびコンデンサからなるスナバ回路とによっ
て構成された電力変換装置に使用されるトランジスタモ
ジュールに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor module used in a power conversion device, which is composed of transistors and a snubber circuit consisting of an asymmetric element and a capacitor for protecting the transistors. .

〔従来の技術〕[Conventional technology]

電力変換装置に用いられるトランジスタモジュールは、
トランジスタだけあるいはトランジスタと並列または1
列に接続され、トランジスタとは逆方向または同方向に
電流を流すダイオードとからなり、これらトランジスタ
とダイオードは同一の基板上に固着され、さらに一つの
容器に納められ、かつ主たる電流を流すための外部端子
とトランジスタを駆動するための端子とが容器の外周部
に設けられていた。更に、トランジスタのターンオフ時
あるいはダイオードの逆回復時に回路の浮遊インダクタ
ンスによって発生するサージ電圧が素子に印加され、素
子が破壊するのを防止するために、特願平1−8311
号lこよりトランジスタの端子間に順方向電圧降下が小
で逆方向電圧降下が大である非対称素子、例えば、定電
圧ダイオードとコンデンサの直列回路からなるスナバ回
路を並列接続する方法が提案されている。第9図はこの
回路を示す。このようなトランジスタモジュールでは、
トランジスタ21のコレクタと定電圧ダイオードnのア
ノードを導体で接続し、さらに定電圧ダイオードるのカ
ソードトランジスタ21のエミ、りとの間にコンデンサ
冴を接続していた。しかし、このような構成においては
以下の問題点があった。
Transistor modules used in power conversion devices are
Only transistor or in parallel with transistor or 1
It consists of a diode that is connected in a column and allows current to flow in the opposite direction or the same direction as the transistor, and these transistors and diodes are fixed on the same substrate and are housed in one container, and a An external terminal and a terminal for driving the transistor were provided on the outer periphery of the container. Furthermore, in order to prevent the device from being damaged due to the surge voltage generated by the stray inductance of the circuit being applied to the device when turning off the transistor or reverse recovery of the diode, Japanese Patent Application No. 1-8311
From No. 1, a method has been proposed in which an asymmetric element with a small forward voltage drop and a large reverse voltage drop between the terminals of a transistor, such as a snubber circuit consisting of a series circuit of a constant voltage diode and a capacitor, is connected in parallel. . FIG. 9 shows this circuit. In such a transistor module,
The collector of the transistor 21 and the anode of the constant voltage diode n were connected with a conductor, and a capacitor was connected between the cathode of the constant voltage diode n and the emitter of the transistor 21. However, such a configuration has the following problems.

1)定電圧ダイオードが発熱するため、これを放熱させ
なけイtばならないが、一般にスナバ回路はトランジス
タ素子のd器の上部に設けられる配線用導体に取り付け
られるため充分に放熱できず、大きなテングサイズの定
電圧ダイオード菓子を必要とする。
1) The constant voltage diode generates heat, so it must be dissipated. However, since snubber circuits are generally attached to the wiring conductor provided on the top of the transistor device, heat cannot be dissipated sufficiently, and a large prong is required. Requires constant voltage diode confectionery of size.

(2)前記の問題を解決するため、トランジスタ菓子と
同一冷却体上に定電圧ダイオード素子を散り付けた場合
、トランジスタ素子の端子との絶層が長くなり、接続の
ために別の配線用導体が必要となる。さらにコンデンサ
とトランジスタの端子との間の配線が長(なり、これら
配線のもつインダクタンス分によりスナバ回路のサージ
電圧吸収効果が小さくなる。
(2) In order to solve the above problem, when constant voltage diode elements are scattered on the same cooling body as the transistor confectionery, the distance between the terminals of the transistor elements becomes longer, and another wiring conductor is required for connection. Is required. Furthermore, the wiring between the capacitor and the terminal of the transistor becomes long, and the inductance of these wirings reduces the surge voltage absorption effect of the snubber circuit.

これに対して、%願平1−161339号によって、第
6図〜第8図に示されるトランジスタモジュールが提案
されている。第6図は前記の提案における各素子および
部品の配置図で、例えば、銅からなる容器底部11の上
に絶縁基板2を介して鋼からなる接続導体31,32,
33,34が固定されている。接続導体蕊の上には、ト
ランジスタ菓子グ41が下面のコレクタ電極により、ダ
イオードチッ142が下面のカソード電極により、定電
圧ダイオードチップ心が下面のアノード電極により固着
されている。
In contrast, transistor modules shown in FIGS. 6 to 8 have been proposed in Application No. 1-161339. FIG. 6 is a layout diagram of each element and component in the above proposal.
33 and 34 are fixed. On the connecting conductor pad, the transistor chip 41 is fixed by the collector electrode on the lower surface, the diode chip 142 is fixed by the cathode electrode on the lower surface, and the constant voltage diode chip core is fixed by the anode electrode on the lower surface.

トランジスタ菓子ズ41の上面のエミッタ電極は接続導
体31と、ペース電極は接続導体おと、ダイオードチッ
フ“42の上面のアノード電極は接続導体31と、また
定電圧ダイオードチップ43の上面のカン基U −ド電極は接続導体あとそれぞれ金属メ線5によって接
続されている。第7図は第6図に示した底板11上に側
壁12および上蓋13を組旦ててなるトランジスタモジ
ュール容器の外観で、上蓋13上には、外部端子、すな
わちエミッタ(E)端子61.コレクタ(C)端子62
.ペース(B)端子63およびカソード(K)端子−が
設けられている。図示されない文上り部を介して、エミ
ッタ端子61は接続導体31とコレクタ端子62は接続
導体!と、ベース端子口は接続導体おと、カソード端子
慣は接続導体あとそれぞれ接続されている。スナバ用の
コンデンサ7はエミッタ端子61とカソード端子−との
間に接続する。第8図はその等価回路を示す。前述の第
9図と回路上は同じである。
The emitter electrode on the top surface of the transistor candy 41 is connected to the connection conductor 31, the pace electrode is connected to the connection conductor, the anode electrode on the top surface of the diode chip "42 is connected to the connection conductor 31, and the can base on the top surface of the constant voltage diode chip 43 is connected to the connection conductor 31. The U-domain electrodes are connected to the connecting conductors by metal wires 5. FIG. 7 shows the external appearance of a transistor module container in which the side wall 12 and the top cover 13 are assembled on the bottom plate 11 shown in FIG. 6. , external terminals, that is, an emitter (E) terminal 61 and a collector (C) terminal 62 are provided on the upper lid 13.
.. A pace (B) terminal 63 and a cathode (K) terminal are provided. The emitter terminal 61 is connected to the connecting conductor 31 and the collector terminal 62 is connected to the connected conductor through a not-shown upstream portion. The base terminal port is connected to the connecting conductor, and the cathode terminal port is connected to the connecting conductor. A snubber capacitor 7 is connected between the emitter terminal 61 and the cathode terminal -. FIG. 8 shows its equivalent circuit. The circuit is the same as the above-mentioned FIG. 9.

このトランジスタモジュールの出力は使用される半導体
素子の容量により定まるが、これら半導体素子の容量の
大きさには限度があるので、トランジスタモジュールの
出力の増加のためにはこれら半導体素子を必要(Ila
l数並列に接続するようにする。
The output of this transistor module is determined by the capacitance of the semiconductor elements used, but since there is a limit to the capacitance of these semiconductor elements, these semiconductor elements are required to increase the output of the transistor module (Ila
Connect l number of devices in parallel.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

p述の電力変換装置用トランジスタモジ、−ルに2いて
、出力の増加のために各半導体素子を必要個数並列に接
続するようにするが、この場合、並列に接続された各半
導体素子とトランジスタモジュールの外部端子との位置
関係が異なるため、この間の配線のもつインダクタンス
が異なり、このためトランジスタにあっては、並列に接
続される素子間のON、OFF時刻にずれが生じその素
子の定格容量まで充分使用できない問題がある。定電圧
ダイオードにおいても、このインダクタンスのずれによ
り均等に負荷がかからず、同様定格容量まで充分使用で
きない問題がある。
In the transistor module for the power converter device mentioned above, the required number of semiconductor elements are connected in parallel to increase the output. In this case, each semiconductor element connected in parallel and the transistor are connected in parallel. Because the positional relationship with the external terminals of the module is different, the inductance of the wiring between them is different, and for this reason, in the case of transistors, there is a difference in the ON and OFF times between elements connected in parallel, and the rated capacity of that element There is a problem that it cannot be used fully. Voltage regulating diodes also have the same problem of not being able to be used up to their rated capacity because the load is not applied evenly due to this inductance shift.

本発明の課題は並列に接続された各半導体素子と外部端
子との配線のもつ各インダクタンスを等しくしたトラン
ジスタモジエールを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a transistor module in which the inductances of wirings between semiconductor elements and external terminals connected in parallel are equal.

〔課題を解決するための手段〕[Means to solve the problem]

前述の課題を解決するために、本発明にかかる一つの容
器内に収容されるトランジスタ素子基板と電流・電圧特
性の順逆非対称素子基板とが容器底板上の一接続導体上
に各素子基板の一面側の電極を下にして固定され、他面
側の電極はそれぞれ金属a縁を介して異なる接続導体と
接続され、さら(ここの異なる接続導体と、それぞれ容
器の上蓋を介して容器外に引出されてなる外部端子とが
接続導線を介して接続されてなる電力変換装置用トラン
ジスタモジュールにおいては、前記トランジスタ素子基
板と前記非対称素子基板とがそれぞれ並列に接続された
複数個からなり、前記異なる接続導体と外部端子との間
の接続導線がそれぞれほぼ等しい長さからなるようにす
る。
In order to solve the above-mentioned problems, a transistor element substrate and an asymmetric element substrate with forward/reverse current/voltage characteristics housed in one container according to the present invention are arranged on one surface of each element substrate on one connecting conductor on the bottom plate of the container. The electrodes on the side are fixed with the electrodes facing down, and the electrodes on the other side are each connected to different connection conductors via the metal a-rim, and are also connected to the different connection conductors here and each connected to the outside of the container through the top lid of the container. In a transistor module for a power conversion device in which external terminals are connected to each other via connecting conductive wires, the transistor element substrates and the asymmetric element substrates are each connected in parallel, and the different connections The connecting wires between the conductor and the external terminal should each have approximately the same length.

〔作用〕[Effect]

配線のもつインダクタンスは基本的に配線の長さに比例
する。本発明のトランジスタモジュールでは並列に接続
された各半導体素子と外部端子との間の接続導線の長さ
を大略等しくして配線をするようにしたので、そのイン
ダクタンスは大略等しくなる。なお、並列に接続される
各半導体素子と外部端子の位置関係はそれぞれ異なるた
め、接続導線は場合によっては途中で弛む場合が生じる
が、この場合はi3図に示す留め具により固定するよう
にしたので問題は生じない。
The inductance of a wire is basically proportional to the length of the wire. In the transistor module of the present invention, the lengths of the connecting wires between the semiconductor elements connected in parallel and the external terminals are approximately equal to each other, so that the inductances thereof are approximately equal. In addition, since the positional relationship between each semiconductor element and the external terminal connected in parallel is different, the connecting conductor may become loose in some cases, but in this case, it should be fixed with the fastener shown in Figure i3. So no problem will occur.

〔実施例〕〔Example〕

第1図は本発明の一実施例における並列に接続された各
半導体素子と外部端子との配線図、第2図は第1図の実
施例における各半導体素子および部品の配置を示す平面
図である。この例ではトランジスタ4個、ダイオード4
個、定電圧ダイオード2個がそれぞれ並列に接続された
場合を示している。
FIG. 1 is a wiring diagram of each semiconductor element and external terminal connected in parallel in one embodiment of the present invention, and FIG. 2 is a plan view showing the arrangement of each semiconductor element and parts in the embodiment of FIG. 1. be. In this example, there are 4 transistors and 4 diodes.
This shows the case where two constant voltage diodes are connected in parallel.

第2図において、例えば鋼からなる容器底部11の上に
絶縁基板2を介して銅からなる接続導体31A 、 3
2A 、 33A 、 34A及び31B 、 32B
 、 33B 、 34Bが固定されている。接続導体
32Aの上には、トランジスタチップ41A及び41B
がそれぞれ下面のコレクタ電極により、ダイオードチッ
プ42A及び42Bがそれぞれ下面のカソード電極によ
り、定電圧ダイオードチップ43Aが下面のアノード電
極により固着されでいる。図を見やすくするために、詳
細な図示は省略したが、トランジスタテップ41A及び
41Bの上面のエミ、り電極は接続導体31Aと、ベー
ス電極は接続導体33Aと、ダイオードチップ42八及
び42Bの上面のアノード電極は接続導体31Aと、ま
た定電圧ダイオードチップ43Aの上面のカソード電極
は接続導体34Aとそれぞれ金属細線5によって接続さ
れている。また、接続導体32Bの上にはトランジスタ
チップ41C及び41Dがそれぞれ下面のコレクタ゛電
極により、ダイオードチップ42C及び42Dがそれぞ
れ下面のカソード電極により定電圧ダイオードチップ4
3Bが下面のアノード電極により固着されている。前述
と同様に図を見やすくするために、詳細な図示は省略し
たが、トランジスタチップ41C及び41Dの上面のエ
ミッタ電極は接続導体31Bと、ペース電極は接続導体
33Bと、ダイオードテップ42C及び42Dの上面の
アノード電極は接続導体31Bと、また定電圧ダイオー
ドチップ43Bの上面のカソード電極は接続導体34B
とそれぞれ金Jlil線51こよって接続されている。
In FIG. 2, connecting conductors 31A and 3 made of copper are placed on the bottom part 11 of the container made of steel, for example, through an insulating substrate 2.
2A, 33A, 34A and 31B, 32B
, 33B, and 34B are fixed. On the connection conductor 32A are transistor chips 41A and 41B.
are fixed by the collector electrodes on the bottom surface, the diode chips 42A and 42B are fixed by the cathode electrodes on the bottom surface, and the constant voltage diode chip 43A is fixed by the anode electrode on the bottom surface. Although detailed illustrations are omitted for clarity, the emitter and rear electrodes on the upper surfaces of the transistor tips 41A and 41B are connected to the connecting conductor 31A, the base electrodes are connected to the connecting conductor 33A, and the upper surfaces of the diode chips 428 and 42B are connected to the connecting conductor 31A. The anode electrode is connected to the connecting conductor 31A, and the cathode electrode on the upper surface of the constant voltage diode chip 43A is connected to the connecting conductor 34A by thin metal wires 5, respectively. Furthermore, on the connecting conductor 32B, transistor chips 41C and 41D are connected to the constant voltage diode chip 4 by means of collector electrodes on the lower surface, and diode chips 42C and 42D are connected to the constant voltage diode chip 4 through the cathode electrodes on the lower surface, respectively.
3B is fixed by the anode electrode on the lower surface. Similar to the above, for the sake of clarity, detailed illustrations have been omitted for clarity, but the emitter electrodes on the top surfaces of the transistor chips 41C and 41D are connected to the connection conductor 31B, the space electrodes are connected to the connection conductor 33B, and the top surfaces of the diode tips 42C and 42D. The anode electrode of the constant voltage diode chip 43B is connected to the connecting conductor 31B, and the cathode electrode on the upper surface of the constant voltage diode chip 43B is connected to the connecting conductor 34B.
and are connected by gold wires 51, respectively.

第1図は1g2図に示された各接続導体と各外部端子と
の接続導線の配線図で、図中O印で示される外部端子、
すなわちエミッタ(E)端子、コレクタ(C)端子、ベ
ース(B)端子、カソード(K)端子及び制惧エミッタ
(E)端子は、図示の位置の上部のトランジスタモジュ
ールの上蓋に取り付けられている。
Figure 1 is a wiring diagram of the connecting conductors and external terminals shown in Figure 1g2.
That is, an emitter (E) terminal, a collector (C) terminal, a base (B) terminal, a cathode (K) terminal, and an emitter (E) terminal are attached to the upper lid of the transistor module at the positions shown.

太線の点線は外部端子と各接続導体との間の接続導線8
である。各接続導体には各半導体チップの′1極が接続
されている。すなわち、エミッタ端子61と各トランジ
スタ41A 、 41B 、 41C、41Dを接続す
る接続導線の内、一つはトランジスタ41A、41Bの
エミf夕が接続される接続導体31Aの両トランジスタ
の工i、夕の接続された点のほぼ中間よりエミッタ端子
61へ、他の一つはトランジスタ41c。
The thick dotted lines are the connection conductors 8 between the external terminals and each connection conductor.
It is. The '1 pole of each semiconductor chip is connected to each connection conductor. That is, among the connecting conductors that connect the emitter terminal 61 and each of the transistors 41A, 41B, 41C, and 41D, one is connected to the connecting conductor 31A to which the emitters of the transistors 41A and 41B are connected. The emitter terminal 61 is connected from approximately the middle of the connected points, and the other one is the transistor 41c.

41Dのエミッタが接続された接続導体31Bの両トラ
ンジスタのエミッタの接αされた点のほぼ中間よりエミ
ッタ端子61へ接続される。この場合、これらの接続導
線は長さの等しいものを用いる。このようにしてエミッ
タ端子61から各トランジスタへの接続導線によるイン
ダクタンスはほぼ等しくなる。同様な方法でコレクタ端
子62はコレクタの接続されている接続導体32A及び
32Bとの間を、ベース端子はベースの接続されている
接続導体:33A及び33Bとの間を、カソード端子−
は非対称素子のカソードが接続されている接続4体34
A及び34Bとの間をそれぞれ等しい長さの接続導線8
で接続している。コレクタ端子62、ベース端子63、
カソード端子劇の接続導線に見られるように、端子と各
接続導体の位置関係から、二個の接続導体の長さを等し
くすると場合によっては途中で弛む場合が生じるが、こ
の場合は第1図のP部に示すように、接続導体を保持す
るようにする。P部の詳細は第3図に示すが、図の如き
留め具8で接続導体を保持する。
The connecting conductor 31B to which the emitter of the transistor 41D is connected is connected to the emitter terminal 61 from approximately the middle of the point where the emitters of both transistors are connected to each other. In this case, these connecting conductors are of equal length. In this way, the inductances due to the connecting wires from the emitter terminal 61 to each transistor become approximately equal. In a similar manner, the collector terminal 62 is connected between the connecting conductors 32A and 32B connected to the collector, the base terminal is connected between the connecting conductors 33A and 33B connected to the base, and the cathode terminal -
is the connection 4 body 34 to which the cathode of the asymmetric element is connected.
Connecting wires 8 of equal length between A and 34B
It is connected with collector terminal 62, base terminal 63,
As can be seen in the connecting conductor of the cathode terminal, due to the positional relationship between the terminal and each connecting conductor, if the lengths of the two connecting conductors are made equal, in some cases they may become loose in the middle. In this case, as shown in Figure 1. Hold the connecting conductor as shown in the P section. Details of the P portion are shown in FIG. 3, and the connecting conductor is held by a fastener 8 as shown in the figure.

なお、本例ではトランジスタの制御用にベースCB)、
端子63と隣接して制御エミッタ(E)端子67を設け
、容器内で綴紐しである。これによって、トランジスタ
モジー−ルの外部の制御紐の配線がより容易になる。
In addition, in this example, the base CB),
A control emitter (E) terminal 67 is provided adjacent to the terminal 63 and is tied within the container. This makes wiring the control strings outside the transistor module easier.

第4図は第2図に示した容器底板11上に側壁及び上器
を組み文でてなるトランジスタモジュールの平面図であ
り、外部端子、すなわち、エミッタ(E)端子61、コ
レクタCC’)端子62、ベースCB)端子63%カソ
ード(IO端子64、制御エミッタ(E)端子67の位
置は第1図のそれと対応している。スナバ回路用のコン
デンサ7はカソード端子−とエミ、り端子61との間に
接続するようにする。
FIG. 4 is a plan view of a transistor module in which a side wall and an upper case are assembled on the container bottom plate 11 shown in FIG. 62, base CB) terminal 63% cathode (IO terminal 64, control emitter (E) terminal 67 positions correspond to those in FIG. 1. Snubber circuit capacitor 7 has cathode terminal - and emitter terminal 61 Make a connection between.

第5図はこのようにして得られたトランジスタモジュー
ルの回路図である。
FIG. 5 is a circuit diagram of the transistor module thus obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電力変換装置用モジー−ルにおいて、
各半導体素子を並列に接続する場合に、外部端子と各半
導体素子との間の接続導線の長さを等しくして、この配
線のもつインダクタンスを等しくしたので、並列に接続
される各素子壷こ均等に負荷がかかるようになり、各素
子の定格容量まで充分使用できるようになった。これに
よって従来のトランジスタモジー−ルに比して5〜8%
出力が増加した。
According to the present invention, in the power converter module,
When connecting each semiconductor element in parallel, the length of the connecting wire between the external terminal and each semiconductor element is made equal, and the inductance of this wiring is made equal, so that each element connected in parallel can be connected in parallel. The load is now applied evenly, and each element can now be fully used up to its rated capacity. This results in a reduction of 5 to 8% compared to conventional transistor modules.
Output increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における並列に接続された各
半導体素子と外部端子との配線図、第2図は第1図の実
施例における各半導体素子および部品の配置を示す平面
図、第3図は第1図のP部の拡大詳細図、第4図は第2
図の容器底板上に組み■てられた本発明にかかる電力変
換装置用トランジスタモジュールの平面図、第5図は第
4図に示した電力変換装置用トランジスタモジ、−ルの
等価回路図、第6図は従来の電力変換装置用トランジス
タモジュールにおける容器底板上の素子および部品の配
Ifを示す斜視図、第7図は@6図の容器底板上に組み
文てられた従来の電力変換装置用トランジスタモジュー
ルの斜視図、第8図は第7図に示した従来の電力変換f
c医用トランジスタモジュールの等価回路図、第9図は
特願平 1−8311号に示されるスナバ回路の回路図
である。 41A 、41B 、41C,41D・・・トランジス
タ、43A 、 43B 、 43C、43D・・・定
電圧タイオード、 61・・・エミッタ(E)4子(外
部端子)、62・・・コレクタCC)端子(外部端子う
、ω・・・ベースCB) 12iia子(外部端子)、
−・・・カソード(K)端子(外部端子)、χ 図 葛、i図 5 1 第 ム 図
1 is a wiring diagram of semiconductor elements and external terminals connected in parallel in an embodiment of the present invention, FIG. 2 is a plan view showing the arrangement of semiconductor elements and components in the embodiment of FIG. 1, Figure 3 is an enlarged detailed view of section P in Figure 1, and Figure 4 is a detailed view of section P in Figure 1.
FIG. 5 is a plan view of the transistor module for a power converter according to the present invention assembled on the bottom plate of the container shown in FIG. Figure 6 is a perspective view showing the arrangement of elements and parts on the bottom plate of a container in a conventional transistor module for power conversion equipment, and Figure 7 is a diagram of the conventional transistor module for power conversion equipment assembled on the bottom plate of the container shown in Figure @6. A perspective view of a transistor module, FIG. 8 is a conventional power conversion f shown in FIG.
c. Equivalent circuit diagram of a medical transistor module. FIG. 9 is a circuit diagram of a snubber circuit shown in Japanese Patent Application No. 1-8311. 41A, 41B, 41C, 41D... Transistor, 43A, 43B, 43C, 43D... Constant voltage diode, 61... Emitter (E) 4 children (external terminal), 62... Collector CC) terminal ( External terminal ω...Base CB) 12ia child (external terminal),
-...Cathode (K) terminal (external terminal), χ Figure 5, i Figure 5 1 Figure M

Claims (1)

【特許請求の範囲】[Claims] 1)一つの容器内に収容されるトランジスタ素子基板と
電流・電圧特性の順逆非対称素子基板とが容器底板上の
一接続導体上に各素子基板の一面側の電極を下にして固
定され、他面側の電極はそれぞれ金属細線を介して異な
る接続導体と接続され、さらにこの異なる接続導体と、
それぞれ容器の上蓋を介して容器外に引出されてなる外
部端子とが接続導線を介して接続されてなる電力変換装
置用トランジスタモジュールにおいて、前記トランジス
タ素子基板と前記非対称素子基板とがそれぞれ並列に接
続された複数個からなり、前記異なる接続導体と外部端
子との間の接続導線がそれぞれほぼ等しい長さからなる
ことを特徴とする電力変換装置用トランジスタモジュー
ル。
1) A transistor element substrate and an asymmetric element substrate with forward/reverse current/voltage characteristics housed in one container are fixed onto one connecting conductor on the bottom plate of the container with the electrode on one side of each element substrate facing down, and the other The electrodes on the surface side are each connected to different connection conductors via thin metal wires, and further connected to these different connection conductors,
In a transistor module for a power conversion device, the transistor element substrate and the asymmetric element substrate are each connected in parallel to each other in a transistor module for a power conversion device, in which external terminals each drawn out from the container through a top lid of the container are connected via a connecting conductor. A transistor module for a power conversion device, characterized in that the connecting conductors between the different connecting conductors and the external terminals have substantially the same length.
JP1271101A 1989-10-18 1989-10-18 Transistor module for power converter Expired - Lifetime JP2580798B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1271101A JP2580798B2 (en) 1989-10-18 1989-10-18 Transistor module for power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1271101A JP2580798B2 (en) 1989-10-18 1989-10-18 Transistor module for power converter

Publications (2)

Publication Number Publication Date
JPH03132066A true JPH03132066A (en) 1991-06-05
JP2580798B2 JP2580798B2 (en) 1997-02-12

Family

ID=17495363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1271101A Expired - Lifetime JP2580798B2 (en) 1989-10-18 1989-10-18 Transistor module for power converter

Country Status (1)

Country Link
JP (1) JP2580798B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2816112A1 (en) * 2000-10-31 2002-05-03 Mitsubishi Electric Corp SEMICONDUCTOR MOLD

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968958A (en) * 1982-10-12 1984-04-19 Mitsubishi Electric Corp Gate turn-off thyristor assembled body
JPS61139051A (en) * 1984-12-11 1986-06-26 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968958A (en) * 1982-10-12 1984-04-19 Mitsubishi Electric Corp Gate turn-off thyristor assembled body
JPS61139051A (en) * 1984-12-11 1986-06-26 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2816112A1 (en) * 2000-10-31 2002-05-03 Mitsubishi Electric Corp SEMICONDUCTOR MOLD

Also Published As

Publication number Publication date
JP2580798B2 (en) 1997-02-12

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