JPH0313178A - Vertical blanking signal generation circuit - Google Patents

Abstract

PURPOSE:To set the width of a vertical blanking pulse arbitrarily by providing a counter circuit to count the number equivalent to a numeric value set in advance of horizontal synchronizing signals. CONSTITUTION:A vertical synchronizing signal VS is inputted to the clear terminal of a counter 9, and the output of a counter 1 goes to a low level. Meanwhile, the horizontal synchronizing signal HS is inputted to a clock terminal after taking NAND with the inversion signal of an output signal. Therefore, when the X bits of the counter is set as the output signal, the output goes to a high level when the number of X square on 2 of times of the horizontal synchronizing signals is inputted, and hereafter, the high level is held until the next vertical synchronizing signal is inputted. In such a way, the taking out bit of the output signal is changed. Thereby, the output signal, i.e., the time width of the vertical blanking signal can be varied, and the optimum blanking time is set corresponding to a video input signal and its display timing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a raster scanning display device used for personal computers, workstations, etc., for erasing the brightness of the retrace line during the retrace period of vertical deflection. The present invention relates to a vertical blanking signal generation circuit used for.

[Summary of the invention]

The present invention calculates the blanking period according to the display period and display timing of the video signal by counting the horizontal synchronization signal for a preset value and arbitrarily setting the pulse width of the vertical blanking signal. This allows for optimal settings.

[Conventional technology]

Conventionally, a vertical blanking signal generation circuit is configured as shown in FIG. Hereinafter, conventional technical examples will be explained based on the drawings. 1 is a vertical oscillation circuit that oscillates at the cycle of the vertical synchronization signal using a vertical synchronization signal as a trigger; 2 is a vertical deflection output circuit that outputs a vertical deflection output signal synchronized with the timing of the signal output from the vertical oscillation circuit l; 3 is a vertical blanking signal generation circuit.

The conventional vertical blanking signal generation circuit 3 extracts a vertical retrace period of time width T from the vertical output signal outputted from the vertical deflection output circuit 2, and outputs the vertical blanking period through the capacitor 4 in the vertical blanking signal generation circuit 3. The signal is resistance-divided by a resistor 5.6, rectified by a diode 7, and passed through a bathophore amplifier 8 to obtain a vertical blanking signal as shown in FIG.

[Problem to be solved by the invention]

In the vertical blanking signal generation circuit as described above, the time width of the blanking signal is the same as the vertical retrace period T, and when the bank porch of the video signal is long, the electron beam is Since the scanning direction of the raster is reversed, there is a situation in which the scanning movement of the electron beam is temporarily stopped, and the brightness becomes extremely high at both ends of the raster, resulting in the observation of bright lines. Furthermore, due to the circuit configuration, the vertical blanking signal has jitter with respect to the vertical deflection output signal, resulting in fluctuations in the bright line portion.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a simple vertical blanking signal generation circuit as shown in FIG. The circuit shown in FIG. 1 is composed of digital ICs including a gate circuit and a counter circuit.

[Effect]

The horizontal synchronization signal H3 acts as a clock input signal of the counter circuit, and if the output signal is Xbtt, the blanking pulse width is set by using the fact that the output changes to H4gh level after counting 2 x east times. can.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, the vertical synchronizing signal S is input to the clear terminal of the counter 9. Therefore, the output of counter l becomes Low level. On the other hand, the horizontal synchronizing signal H3 is NANDed together with the inverted signal of the output signal and inputted to the clock terminal. Therefore, when the counter's Xbtt is used as the output signal, when 2 x east horizontal synchronization signals are input, the output becomes High level, and from then on until the next vertical synchronization signal is input, this ) () FIG. 2 shows a time chart of this embodiment in which the high level is maintained.

By changing the output signal extraction bit, the output signal,
That is, it is possible to change the time width of the vertical blanking signal, and an optimal blanking time can be set according to the video input signal and its display timing.

〔Effect of the invention〕

As described above, the present invention does not have a fixed time width as in conventional blanking signal generation circuits, but can be set arbitrarily, has no adverse effects such as a shifter, has a simple configuration using a digital IC, and has a low cost. It is possible to create a vertical blanking signal with an arbitrary time width at a low cost.

３　・・ ４　・・ 6 7・・・ 8・・・ 9　・・ lO・・ Vertical blanking signal generation circuit capacitor ・Divided resistance diode buffer amplifier counter NAND gate that's all

Claims (1)

[Claims] In raster scanning display devices that scan according to horizontal and vertical synchronization signals, the vertical blanking pulse width can be set arbitrarily by being equipped with a counter circuit that counts horizontal synchronization signals for a preset value. A vertical blanking signal generation circuit characterized by: