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JPH03130984A - Ｌｉｆｏ方式の半導体記憶装置およびその制御方法 - Google Patents

Ｌｉｆｏ方式の半導体記憶装置およびその制御方法

Info

Publication number
JPH03130984A
JPH03130984A JP1267140A JP26714089A JPH03130984A JP H03130984 A JPH03130984 A JP H03130984A JP 1267140 A JP1267140 A JP 1267140A JP 26714089 A JP26714089 A JP 26714089A JP H03130984 A JPH03130984 A JP H03130984A
Authority
JP
Japan
Prior art keywords
selection
storage means
phase
read
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1267140A
Other languages
English (en)
Other versions
JP2646032B2 (ja
Inventor
Takenori Okidaka
毅則 沖高
Yasunori Maeda
前田　安範
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1267140A priority Critical patent/JP2646032B2/ja
Priority to US07/545,797 priority patent/US5185719A/en
Priority to DE4020872A priority patent/DE4020872C2/de
Priority to KR1019900016176A priority patent/KR940006361B1/ko
Publication of JPH03130984A publication Critical patent/JPH03130984A/ja
Priority to US07/850,203 priority patent/US5206834A/en
Application granted granted Critical
Publication of JP2646032B2 publication Critical patent/JP2646032B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体記憶装置およびその制御方法に関し、
特に最後に書込まれたデータが最初に読出されるＬＩＦ
Ｏ（Ｌａｓｔ−Ｉｎ−Ｆｉｒｓｔ−Ｏｕｔ）装置および
その制御方法に関する。
［従来の技術］ 第 １ 図 第 図 アト°し又っ奎か！ 第 図

Claims (2)

    【特許請求の範囲】
  1. （１）データをそれぞれ記憶するための複数の記憶手段
    、 前記複数の記憶手段を順に選択し、その選択された記憶
    手段に外部から与えられるデータを書込むための第１の
    選択手段、および 前記複数の記憶手段を順に選択し、その選択された記憶
    手段に記憶されたデータを読出すための第２の選択手段
    を備え、 前記第１および第２の選択手段の各々は、前記複数の記
    憶手段を所定の順に選択する第１のモードと、前記複数
    の記憶手段を前記所定の順とは逆の順に選択する第２の
    モードとを交互に繰返し、かつ前記第２の選択手段によ
    る選択が前記第１の選択手段による選択に先行するよう
    に動作が行なわれる、半導体記憶装置。
  2. （２）複数の記憶手段、前記複数の記憶手段のうちデー
    タを書込むべき記憶手段を選択する第１の選択手段、お
    よび前記複数の記憶手段のうちデータを読出すべき記憶
    手段を選択する第２の選択手段を備えた半導体記憶装置
    の制御方法において、 前記第１および第２の選択手段の各々が、前記複数の記
    憶手段を所定の順に選択する第１のモードと、前記複数
    の記憶手段を前記所定の順とは逆の順に選択する第２の
    モードとを繰返すように制御を行ない、かつ前記第２の
    選択手段による選択が前記第１の選択手段による選択に
    先行するように制御を行なうことを特徴とする、半導体
    記憶装置の制御方法。
JP1267140A 1989-10-14 1989-10-14 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法 Expired - Lifetime JP2646032B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1267140A JP2646032B2 (ja) 1989-10-14 1989-10-14 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
US07/545,797 US5185719A (en) 1989-10-14 1990-06-29 High speed dynamic, random access memory with extended reset/precharge time
DE4020872A DE4020872C2 (de) 1989-10-14 1990-06-29 Halbleiterspeichereinrichtung vom LIFO-Typ und Verfahren zum Steuern einer solchen
KR1019900016176A KR940006361B1 (ko) 1989-10-14 1990-10-12 반도체 기억장치 및 그 제어방법
US07/850,203 US5206834A (en) 1989-10-14 1992-03-12 Semiconductor memory device performing last in-first out operation and the method for controlling the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1267140A JP2646032B2 (ja) 1989-10-14 1989-10-14 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法

Publications (2)

Publication Number Publication Date
JPH03130984A true JPH03130984A (ja) 1991-06-04
JP2646032B2 JP2646032B2 (ja) 1997-08-25

Family

ID=17440637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1267140A Expired - Lifetime JP2646032B2 (ja) 1989-10-14 1989-10-14 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法

Country Status (4)

Country Link
US (1) US5185719A (ja)
JP (1) JP2646032B2 (ja)
KR (1) KR940006361B1 (ja)
DE (1) DE4020872C2 (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5479640A (en) * 1990-08-31 1995-12-26 International Business Machines Corporation Memory access system including a memory controller with memory redrive circuitry
JPH0628846A (ja) * 1992-07-09 1994-02-04 Mitsubishi Electric Corp 半導体記憶装置
GB9219524D0 (en) * 1992-09-15 1992-10-28 Smithkline Beecham Plc Novel composition
US5530836A (en) * 1994-08-12 1996-06-25 International Business Machines Corporation Method and apparatus for multiple memory bank selection
US5680591A (en) * 1995-03-28 1997-10-21 Cirrus Logic, Inc. Method and apparatus for monitoring a row address strobe signal in a graphics controller
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5875454A (en) * 1996-07-24 1999-02-23 International Business Machiness Corporation Compressed data cache storage system
US5703832A (en) * 1997-02-28 1997-12-30 Etron Technology, Inc. tRAS protection circuit
US5737271A (en) * 1997-02-28 1998-04-07 Etron Technology, Inc. Semiconductor memory arrays
US5897659A (en) * 1997-03-07 1999-04-27 Advanced Micro Devices, Inc. Modifying RAS timing based on wait states to accommodate different speed grade DRAMs
US5987577A (en) * 1997-04-24 1999-11-16 International Business Machines Dual word enable method and apparatus for memory arrays
AU9798798A (en) 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
US6072746A (en) 1998-08-14 2000-06-06 International Business Machines Corporation Self-timed address decoder for register file and compare circuit of a multi-port CAM
JP3267259B2 (ja) * 1998-12-22 2002-03-18 日本電気株式会社 半導体記憶装置
US6219294B1 (en) 2000-01-13 2001-04-17 Micron Technology, Inc. Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories
US6754748B2 (en) * 2001-02-16 2004-06-22 Agere Systems Inc. Method and apparatus for distributing multi-source/multi-sink control signals among nodes on a chip
US9159383B2 (en) 2012-04-11 2015-10-13 Micron Technology, Inc. Signal management in a memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148498A (ja) * 1986-12-10 1988-06-21 Advantest Corp 自己診断機能を具備した記憶装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271483A (en) * 1977-08-04 1981-06-02 Independent Broadcasting Authority Delay circuits
JPS55135392A (en) * 1979-04-04 1980-10-22 Nec Corp Memory circuit
JPS6012718B2 (ja) * 1980-03-28 1985-04-03 富士通株式会社 半導体ダイナミックメモリ
JPS6052513B2 (ja) * 1981-12-02 1985-11-19 富士通株式会社 半導体記憶装置
JPS58155596A (ja) * 1982-03-10 1983-09-16 Hitachi Ltd ダイナミツク型ｍｏｓｒａｍ
DE3319980A1 (de) * 1983-06-01 1984-12-06 Siemens AG, 1000 Berlin und 8000 München Integrierbares busorientiertes uebertragungssystem
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPH0789435B2 (ja) * 1984-04-06 1995-09-27 株式会社日立製作所 ダイナミツク型ｒａｍ
US4618947B1 (en) * 1984-07-26 1998-01-06 Texas Instruments Inc Dynamic memory with improved address counter for serial modes
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
JPS61110394A (ja) * 1984-10-31 1986-05-28 Mitsubishi Electric Corp 半導体記憶装置
JPS61126683A (ja) * 1984-11-22 1986-06-14 Toshiba Corp 半導体メモリ装置
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
US4638462A (en) * 1985-01-31 1987-01-20 International Business Machines Corporation Self-timed precharge circuit
JPS61222089A (ja) * 1985-03-28 1986-10-02 Sony Corp イコライズ・プリチヤ−ジ回路
JPS61230697A (ja) * 1985-04-05 1986-10-14 Mitsubishi Electric Corp ダイナミツク半導体メモリ装置
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
JPS6212991A (ja) * 1985-07-10 1987-01-21 Fujitsu Ltd 半導体記憶装置
US4697108A (en) * 1986-05-09 1987-09-29 International Business Machines Corp. Complementary input circuit with nonlinear front end and partially coupled latch
US4754433A (en) * 1986-09-16 1988-06-28 Ibm Corporation Dynamic ram having multiplexed twin I/O line pairs
US4800531A (en) * 1986-12-22 1989-01-24 Motorola, Inc. Address buffer circuit for a dram
US5010519A (en) * 1987-11-17 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Dynamic semiconductor memory device formed by 2-transistor cells

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148498A (ja) * 1986-12-10 1988-06-21 Advantest Corp 自己診断機能を具備した記憶装置

Also Published As

Publication number Publication date
JP2646032B2 (ja) 1997-08-25
DE4020872A1 (de) 1991-04-25
KR940006361B1 (ko) 1994-07-18
DE4020872C2 (de) 1997-03-06
US5185719A (en) 1993-02-09
KR910008725A (ko) 1991-05-31

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