JPH0312984A - Photoelectronic integrated circuit and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To make it possible to reduce a parasitic capacity and make quick motion by injecting the electric current of semiconductor laser transversely into two adjoining grooves bored to an active layer by way of a p type electrode layer and an n type electrode layer which have made an embedded growth respectively. CONSTITUTION:This circuit comprises an Fe dope InP semi-insulation substrate 1, high resistance InP clad layers 2 and 6, a GaInAsP current guide layers 3 and 5, a GaInAs active layer 4, a non-dope GaInAs channel layer 7, an AlInAs/Si dope electric charge supply layer 8, an n type InP electrode layer 9, a p type InP electrode layer 10, a p type GaInAsP cap layer 11, an n type electrode 12, a p type electrode 13, an electric field effect transistor drain electrode, gate electrode, and source electrodes 14 to 16. The electric current of semiconductor laser is injected transversely into two adjoining grooves by way of the p type electrode layer 9 and the n type electrode layer 10 which have made an embedded growth respectively. It is, therefore, possible to reduce a parasitic capacity and operate at very fast speed as well.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an optoelectronic integrated circuit and a method for manufacturing the same, and more particularly to an optoelectronic integrated circuit that is compact and generates high-speed optical signals and a method for manufacturing the same. .

[Prior art]

Optoelectronic integrated circuits, which integrate a semiconductor laser and its drive circuit on the same semiconductor substrate, reduce parasitic capacitance and enable high-speed operation, reduce the number of parts used, increasing device reliability, and are easy to implement. It has been widely researched because it has excellent characteristics such as low price and low price.

Optoelectronic integrated circuits reported so far include, for example, O
, WADA, IEEE JOURNAI, OF
QE-22 of QUANTUM ELECTRONIC3
It is disclosed in Vol. 6, p. 805 (1986).

There was also an idea to integrate a lateral current injection semiconductor laser and a field effect transistor on the same semi-insulating substrate. For example, Journal ofApplj
ed Physjcs 6” Volume 10, Page 4933 (19
In 1987), J. Ohta et al. disclosed the idea of integrating a GaAs-based TJS laser and a field-effect transistor, and the characteristics of separately manufactured devices.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has several problems, and the actual situation is that results that demonstrate the advantages of integration have not been obtained.

The major problems in the former case are: ■ It is difficult to create a planar structure because the film thicknesses required for electronic devices and optical devices are different; and ■ Not only the film thickness, but also the layer structure Since each device is different, the active layer, which requires high quality, also needs to be regrown, making it difficult to obtain a high quality one.

In addition, even in the latter case, TJS lasers require trenches to be dug in a semi-insulating substrate and selective growth is performed in those areas, making planar structures difficult and device fabrication difficult, making integration difficult. Not yet.

The present invention has been made to solve the above problems.

An object of the present invention is to provide an optoelectronic integrated circuit in which active regions of optical devices and electronic devices are formed by continuous crystal growth and have a nearly planar structure, and a method for manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a high resistance cladding layer for a semiconductor laser, a non-doped active layer, and a high resistance cladding layer that are sequentially formed on a semi-insulating substrate, and furthermore, a field effect 1- It has a channel layer for transistors,
The most important feature of the semiconductor laser is that current is injected laterally through the n-type electrode layer, which is grown in two adjacent trenches dug up to the active layer, respectively.

Further, in the method for manufacturing an optoelectronic integrated circuit, an optical device in which a high resistance cladding layer for a semiconductor laser, an active layer, a high resistance cladding layer, and a channel layer for a field effect transistor are sequentially formed on a semi-insulating semiconductor substrate. After growing crystals for optical devices and crystals for electronic devices into a layered structure, trenches are dug below the active layer for current injection of optical devices, and layers for n-type electrodes and layers for n-type electrodes are formed by buried growth. It is characterized by

[Effect]

According to the above-mentioned means, the optical devices and electronic devices of the optoelectronic integrated circuit can have a substantially planar structure, so that a highly reliable optoelectronic integrated circuit can be manufactured with good reproducibility.

Furthermore, since it is formed on a semi-insulating substrate, parasitic capacitance is small and high-speed operation is possible.

Furthermore, since there is no need to re-grow the active layer, which requires high quality, the active layer of both optical devices and electronic devices can be made of high quality.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

[Example I]

FIG. 1 is a diagram for explaining the schematic configuration of an optoelectronic integrated circuit according to Example 2 of the present invention.

In FIG. 1, 1 is an Fe-doped InP semi-insulating substrate;
2 and 6 are high resistance InP cladding layers, 3 and 5 are wavelength 1.3
GaInAsP current guide layer for μm, 4 is wavelength 1
．． GaInAsP active layer corresponding to 55 μm, 7 is undoped GaInAs channel layer, 8 is A], InAs-
5j doped charge supply layer, 9 is n-type InP electrode layer, 10 is p-type InP electrode layer, 11 is p-type GaInAsP cap layer, 12 is n-type electrode, 13 is p-type electrode, 14 is for field effect transistor A drain electrode, 15 is a gate electrode, and 16 is a source electrode.

With such a structure, there is almost no difference in layer thickness between the optical device and the electronic device, and the step difference is much smaller than in the optoelectronic integrated circuits reported so far. Therefore, it is easy to form a thin gate electrode, and since there is no charged layer under the I-transistor, it is possible to produce a field-effect 1-transistor that operates at 10 Giga bits.

In addition, this semiconductor laser oscillates by passing a current horizontally between a pair of electrodes 12 and 13 formed on a semi-insulating substrate, and has very small parasitic capacitance, so it can operate at over 20 kigabits. It becomes possible.

Note that the p-type GaInAsP cap layer 11 has a low resistance P
A GaIn, AsP current guide layer 3.5 is provided to obtain the side electrode, and the present inventor has already proposed the same in Japanese Patent Application No. 63-259037.
This is to widen the current path and lower the resistance of the laser diode, as described in the specification.

The high-resistance InP cladding layers 2 and 6 are made of a high-purity InP layer or a Fe-doped InP layer so that the laser light is confined in the vertical direction and the current flows only through the GaInAsP current kite layers 3 and 5 and the GaInAsP active layer 4. There is a need to.

In the example of FIG. 1, the Fe-doped InP semi-insulating substrate 1 also fulfills this role, so the high-resistance InP cladding layer 2 is not necessary.

The optoelectronic integrated circuit of this embodiment I has few steps as described below, and therefore can operate stably at 10 kbit or more.

Next, the method for manufacturing the optoelectronic integrated circuit of Example I will be explained with reference to FIGS. 2A to 2E (cross-sectional views at each step). Note that in FIGS. 2A to 2E, diagonal lines representing cross sections are omitted to make the drawings easier to read.

First, as shown in FIG. 2A, high-resistance InP is deposited on a Fe-doped InP semi-insulating substrate 1 by MOVPE.
Cladding layer 2, GaInAsP current layer 1 to layer 3, Ga
InAsP active layer 4, GaInAsP current guide layer current guide layer 5P cladding layer 6, non-1 to -B GaInAs
Channel layer 7, AlInAs-3i doped charge supply layer 8
are continuously epitaxially grown. In this process, A
MOVPE lInAs-3i lcoup charge supply layer 8
It is somewhat difficult to grow at 7 m due to the narrow range of optimal conditions, so high resistance InP cladding layer 2, GaInAsP
Current layer 1 (layer 3, GaInAsP active layer 4, GaIn
AsP current guide layer current guide layer 5P cladding layer 6
It is of course also possible to grow the non-doped GaInAs channel N7 and the Al1nAs-5i doped charge supply layer 8 by the MBE method after growing by the OVPE method.

Then, using a selective etching solution that etches InAs and GaInAs but not InP,
Non-doped G other than the heterojunction field effect transistor section
After etching the aInAs channel layer 7 and the AlInAs-3i doped charge supply layer 8 (FIG. 2B), a 5-in.
2 film 21 is attached, a window is formed in a portion where the n-type InP electrode layer 9 is to be grown by a conventional method, and a groove is dug into the high-resistance InP cladding layer 2 by reactive ion etching. Then, by a growth method that allows easy selective growth, an n-type 1nP electrode layer 9 is grown only in this groove portion (second C
figure). A crystal growth method using a raw material containing chlorine (cn) is suitable for this purpose, and here, this selective growth method is
n (C2tl, )zM○V using CQ and PH3
PE growth was performed. As a result, the 5j-0□ mask was able to grow flat in the trench without forming polycrystals. After peeling off the s'o2 film 21, a p-type InP electrode layer 10 and a p-type GaInAsP cap Ill are grown using the same process (FIG. 2D).

What is important in this process is that the n-type InP electrode M9 and the p-type InP electrode
The distance d of the P electrode layer 10 needs to be 1.5 μm or less. This is fully possible if a stepper is used for photolithographic exposure. Also, n-type I
Instead of the nP electrode layer 9 and the p-type InP electrode layer 10, respectively,
If a GaInAsP layer with a higher refractive index is used, this distance d can be set to 2 μm or more, increasing the manufacturing margin.

As described above, according to the means of the present invention, a crystal for an optoelectronic integrated circuit can be produced by epitaxial growth at least three times.

Thereafter, as shown in FIG. 2E, by forming electrodes 12, 13, 14, 15, 16 by conventional means,
This integrated circuit is completed.

The optical device of the optoelectronic integrated circuit shown here is a Fabry-Perot type laser, but the first growth
After growing the InAsP current guide layer 5, the growth is interrupted and taken out, a diffraction grating is formed on the GaInAsP current guide MS, and then the high resistance nP crack layer 6 is formed.
．． Non-doped GaInAs channel layer 7, AITnAs
By growing the -8j doped charge supply layer 8, a distributed feedback laser and a field effect transistor can be integrated. The electronic device shown here also includes a non-doped GaInAs channel layer 7 and A1. InAs-8]
Although a two-dimensional electron gas heterojunction field effect transistor consisting of a topped charge supply layer 8 has been described, field effect transistors made of other materials and construction methods may be used.

[Example ■]

The optoelectronic integrated circuit of Example 2 of the present invention has the same configuration as Example I shown in FIG. 1, and has an Fe-doped InP#! :
The insulating substrate 1 is a semi-insulating GaAs substrate, and a high resistance InP
The crand layers 2 and 6 are made of high resistance AlGaAs cladding layer,
GaInAsP current guide F JW 3, 5 with high resistance A
Al with a smaller A1 composition than lGaAs clad N2,6
, GaAs current guide layer, GaInAsP active layer 4 as GaAs active layer, non-doped GaInAs channel layer 7 as non-doped GaAs channel layer, AlInAs-
The 3j doped charge supply layer 8 is made of AlGaAs-3i doped charge supply layer, and the n-type InP electrode layer 9 is made of n-type Al, GaA.
By changing the p-type InP electrode layer 10 to a p-type AlGaAs layer and the p-type GaInAsP cap layer 11 to a p-type GaAs cap layer in the s layer, the wavelength is 0.88 μm.
It is equipped with a semiconductor laser and a GaAs-based two-dimensional electron gas heterojunction field effect transistor.

[Example ■]

In the optoelectronic integrated circuit of Example H of the present invention, the GaAs active layer 4 of Example 2 is thin (as shown in FIG. 3).
70 people) In. , 3. Gao, cqAs layer 31
A semiconductor laser with a wavelength of 1.05 .mu.nl and a GaAs-based two-dimensional electron gas heterojunction field effect transistor are mounted by sandwiching the structure between aAs layers 32 and 33 (thickness: 500 layers).

11 Hereinafter, the present invention has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. .

〔Effect of the invention〕

As described above, according to the present invention, the active regions of the optical devices and electronic devices of optoelectronic integrated circuits can be formed by continuous crystal growth and can have a substantially planar structure. Integrated circuits can be created with good reproducibility.

Furthermore, since the optical devices and electronic devices of the optoelectronic integrated circuit are formed on the same semi-insulating substrate, parasitic capacitance is small and high-speed operation is possible.

Furthermore, since there is no need to re-grow the active layer, which requires high quality, the active layer of both optical devices and electronic devices can be made of high quality.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the schematic configuration of Example 2 of the optoelectronic integrated circuit of the present invention. FIGS. FIG. 3 is a diagram showing the structure of the active layer of the optical device of the optical device of the embodiment DJ of the optoelectronic integrated circuit of the present invention. In the figure, 1. Fe-doped InP semi-insulating substrate, 2°6
・High resistance InP cladding layer, 3,5-GaInAsP
Current guide layer, 4...GaInAsP active layer, 7.
Non-doped GaInAs channel layer, 8-AITnAs-
5i doped charge supply layer, 9 n-type InP electrode layer, 10.
・P-type nP electrode layer, 11-p-type GaInAsP cap layer, 12-n-type electrode, 13 p-type electrode, 14...train electrode for field effect transistor, 15-gate electrode, 16-source electrode, 21.22 -5in2 membrane, 31・
70 A thickness I no, 3sGao, 6Js layer, 32.3
3-500 eight-genus GaAs layer.

Claims (2)

[Claims] (1) A high-resistance cladding layer, an active layer, and a high-resistance cladding layer for a semiconductor laser are sequentially formed on a semi-insulating semiconductor substrate, and a channel layer for a field effect transistor is further formed on top of the high-resistance cladding layer for a semiconductor laser. An optoelectronic integrated circuit characterized in that current is injected laterally through a p-type electrode layer and an n-type electrode layer that are respectively grown in two adjacent trenches dug up to the active layer. (2) Crystals for optical devices and crystals for electronic devices in which a high-resistance cladding layer for a semiconductor laser, an active layer, a high-resistance cladding layer, and a channel layer for a field-effect transistor are sequentially formed on a semi-insulating semiconductor substrate. A claim characterized in that, after growing into a layered structure, a groove is dug to below the active layer for current injection of an optical device, and a layer for an n-type electrode and a layer for a p-type electrode are formed by buried growth. 2. A method for manufacturing an optoelectronic integrated circuit according to item 1.