JPH03129478A - Graphic processor, data processor using the same, graphic drawing method and central processing unit - Google Patents

Abstract

PURPOSE:To reduce the overhead of a software by providing an exclusive input terminal to receive control from an external part for interrupting and restarting the execution of a processing using a main memory. CONSTITUTION:When a graphic processor 100 executes slave operation, terminals A31-A2 become address input terminals for a frame buffer 205 or the internal register of the graphic processor 100 and when the graphic processor 100 executes the slave operation, terminals D31-D0 become data input terminals for writing data to the internal register of the graphic processor 100. According to a signal from the exclusive input terminal to receive the control from the external part for interrupting and restarting the execution of the processing to a main memory 203, the graphic processor 100 can detect not only the request of an emergent processing to a central processing unit 201 but also the end of the processing. Thus, the overhead of the software can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device that handles bitmap data, a central processing unit that constitutes this data processing device,
The present invention relates to a method of processing bitmap data in this data processing device and a graphic processing device constituting this processing method.

[Prior Art] In a conventional data processing device, when a data transfer device such as a direct memory access control device transfers data using a system bus, once data transfer is started,
Until the transfer process is finished.

A method that keeps the system bus occupied (burst transfer method)
The system bus occupancy rate is set in advance, and the central processing unit and data transfer device.

There was a method of using the system bus alternately (cycle steal method).

[Problem to be solved by the invention] In the above conventional technology, the burst transfer method is used.

Compared to the cycle steal method, there is less software overhead for bus arbitration and the data transfer efficiency is higher, but on the other hand, the data transfer device may be in the middle of the transfer process due to external factors or internal system factors.

One problem is that when the central processing unit needs to perform urgent processing, the central processing unit cannot perform the processing until the processing of the data transfer device is completed. Additionally, there is a method for forcibly interrupting the processing of the data transfer device so that the central processing unit acquires the system bus and executes the processing, but in this case, the central processing unit may In addition to identifying the force, it is necessary to instruct the device to resume processing after the emergency processing is completed. This is because the exception handling routine procedure becomes complicated, and
There was a problem that the bus arbitration device became complicated.

On the other hand, when data transfer is performed using the cycle steal method, the central processing unit can execute processing at any time, but the software overhead for the data transfer device to acquire the system bus is large, and compared to the burst transfer method, the data transfer There were problems in that efficiency was low and processing took time. These matters also apply when a graphic processing device is used instead of a data transfer device to execute drawing processing to the main memory or data transfer processing between the main memory and the frame buffer.

The present invention provides a graphic drawing method and a data transfer method that have low software overhead, high data transfer efficiency, and a simple configuration of a bus arbitration device.

The object of the present invention is to provide a graphic processing device and a data processing device that realize the same.

[Means for Solving the Problem] In order to achieve the above object, the graphic processing device is provided with a dedicated input terminal for receiving external control for suspending and resuming execution of processing on the main memory, and a central processing unit. The system includes means for detecting a request for emergency processing, and means for detecting that the processing has been completed.

Furthermore, in order to simplify the configuration of the bus arbitration device, the central processing unit is provided with an output terminal for communicating the completion of one exception handling to the outside. In addition, in order to cope with the case where the central processing unit does not have the above output terminal, the central processing unit should be provided with an external means for communicating the priority level of the exception handling currently being executed, or an equivalent function. This is what I did.

[Function] A graphics processing unit receives a signal from a dedicated input terminal for receiving control from the outside to interrupt and resume execution of processing on the main memory, and the graphics processing unit is able to control the interruption and resumption of processing in the main memory only when there is an emergency processing request to the central processing unit. It is also possible to detect that the process has ended. If the central processing unit has an output terminal to notify the outside of the end of exception processing, the output signal of that terminal is used for this signal, but if there is no output terminal, priority is given to the exception processing currently being executed. Deciphers and generates signals from means for communicating levels to the outside. This signal causes
The graphics processing unit can detect the occurrence and termination of emergency processing to the central processing unit, that is, high-priority exception processing, while executing processing to the main memory, and interrupts drawing processing and data transfer processing at - times. After that, the original process can be resumed without any software processing, allowing the central processing unit to quickly respond to emergency processing.

[Examples] Examples of the present invention will be described below with reference to the drawings. In each drawing, like symbols indicate the same thing.

<System Configuration> FIG. 1 shows an example of a system configuration in which the present invention is implemented.
．． It is connected to the main memory 203 via a system bus consisting of a control bus 208. The bus arbiter 202 connects the central processing unit 201 and the data transfer device 100.
Arbitrates which accesses the main memory. The frame buffer 205 is a memory that stores display data to be displayed on the display device 207.

The video signal generation circuit 206 includes a frame buffer 207
Control is performed to display data stored in the display device 207 on the display device 207. Graphic processing bag rt io.

The decoder 211 transfers data between the frame buffer 205 and the main memory 203, within the frame buffer 205, and within the main memory 300. Generates an LSI selection signal for accessing the frame buffer 205. The SUS control circuit 8212 detects an interrupt signal to the 1 MPU and
The 0 interrupt control circuit 213, which generates a signal for interrupting the use of the 0 system bus, interrupts the use of other input/output devices (
This is a priority control circuit for generating an interrupt from the MPU (not shown) to the MPU. The RTE generation circuit 214 detects that the MPU 201 has finished interrupt processing, and causes the graphic processing bag fifloo to resume using the system bus.

In this embodiment, it is assumed that one graphic processing device 100 is implemented as an LSI.

Terminal configuration> Figure 2 shows the terminal configuration of the graphic processing device 100.The total number of terminals excluding power supply (VCC) and ground (GND) is 1.
There are 39 pieces.

(1) System clock (SYSCLK) terminal 5YS
All processing of the graphic processing device 100 is executed in synchronization with the clock signal inputted to CLK.

(2) Address bus (A31-A2) terminal A31-A
2 becomes an address input terminal of the frame buffer 205 or an internal register of the graphic processing device 100 when the graphic processing device 100 operates as a slave. Also.

When the graphic processing device 100 operates as a bus master, it outputs the physical address of the main memory 203.

(3) Data bus (D31-Do) When the graphics processing device OO operates as a slave, the terminal D31-Do becomes a data input terminal when writing to the internal register of the graphics processing device 100, and when reading from the internal register. Serves as a data output terminal. Also, figure processing 1m! When 100 operates as a bus master, it becomes a data output terminal when writing to the main memory 203, and becomes a data input terminal when reading from the main memory 203.

(4) Address status (ADS#) terminal ADS#
1 When the graphics processing device 100 operates as a slave,
The graphics processing device 100 enters a high impedance state.
When the address bus (A31-A2) operates as a bus master, the data on the address bus (A31-A2) becomes an output terminal indicating that it has been determined.

(5) Quick (QUICK#) The terminal QUICK# is an output terminal that indicates whether or not to access the main memory 203 at high speed using the static column mode.

(6) Write/Read (W/R#) When the graphic processing bag faE100 operates as a slave, if a “Low” level is input to the terminal W/R#, it will write to the internal register of the graphic processing device 100. This indicates a write operation, and if a "High" level is input, it indicates a read operation from the internal register of the graphic processing device 100. Furthermore, when the graphic processing device 100 operates as a bus master, it outputs a "High" level when writing to the main memory 203, and outputs a "Low" level when reading from the main memory 203.

(7) Data ready (READY#) terminal READ
When the graphic processing bag w100 operates as a slave, Y# becomes an output terminal indicating that the data on the data bus (D31-Do) is finalized, and when the graphic processing device 100 operates as a bus master, the data・Bus (D31
-Do) serves as an input terminal indicating that the data has been finalized.

(8) Chip Select (C3#) Only when a "Low" level is input to the terminal C8#, the central processing unit 201 can access the internal register of the graphic processing bag zioo.

(9) Frame buffer select (FS#) terminal F
Only when a 'Low' level is input to S#, the central processing unit 201 inputs the address of the graphic processing unit 100.
Bus (A31-A2) and Data Bus (D31-Do)
The frame buffer 205 can be accessed via.

(10) At the bus hold request ()TOLD) terminal HOLD, the graphics processing device 100
11, a "Low" level is output.

(II) Bus Hold Acknowledge (HLDA) When a 'Low' level is input to the terminal HLDA, this indicates that the system bus 211 has been released to the graphic processing device 100. on the other hand.

Graphic processing device! If a 'High' level is input while the graphics processing device 100 is using the system bus 211, the graphics processing device 100 releases the system bus 211.

(12) Bus Master (BM#) Terminal BM# is set to “Low” while the graphics processing device 100 is the bus master and uses the system bus 211.
”The level is output.

(13) Reset (RES#) When “Low” level is input to terminal RES#2
The graphic processing device 100 is in an initial state.

(14) Suspend (SUS$t) 1 when “Low” level is input to terminal SUS#
The graphic processing bag W1oo temporarily suspends access to the main memory 203.

On the other hand, if a "High" level is input while access to the main memory 203 is temporarily stopped, access to the main memory 203 is resumed.

(15) Interwoven request (IRQ#) terminal I
RQ# indicates that the graphic processing device 100 is the central processing unit 201.
314 to request interrupt processing, n L 0wpH
The level will be output.

(16) Display ') o') (I) ISPCLK) Terminal D
The internal circuit of the graphic processing device 100, which controls the display of the CRT display device 207, operates at half the frequency of the clock input to ISPCLK.

(17) Display reference clock (CLKOUT) terminal CLK
OUT is the graphic processing device I! which controls the display of the CRT display device 1207. Operation clocks for 100 internal circuits are output.

(18) Memory 7 dollars/s (MAI L-MAO)
The frame buffer 206 (7: row address) is output to the terminal MAIL-MAO when the terminal RASf7 falls, and the column address of the frame buffer 205 is output when the terminal CAS falls 9.

(19) Memory data (MD31-MDO) terminal MD
31-MDO has frame buffer 20 when writing.
(20) Row address strobe (RAS# terminal R
The AS# output changes from “High” level to “Lo
w” level, the memory address (MAl
1-MAO) indicates that the row address of the frame buffer 205 is being output.

(21) Column address strobe (When the output of the CAS# terminal CAS# changes from the "High" level to the "Low" level, it indicates that the access is using the memot (SIlo), and the terminal DT#/○ E# is 71H
If it is the high u level, it indicates that the access is using the input/output (Ilo) of the VRAM.
When writing data to 05, write the column address.
When the strobe (CAS#) output changes from 'High' level to 'Low' level, terminal DT#/○E
# becomes #High h” level.

On the other hand, from the frame buffer 205 to the graphic processing device 100
When reading data, when the column address strobe (CAS#) output changes from “High” level to “Low” level, the terminal DT#10E
# becomes "Low" level.

(24) Output enable (OE#) terminal OE
# is an output terminal used only when DRAM is used in the frame buffer 205.
&:, 7L/- indicates that the column address of buffer 205 is being output.

(22) Write enable (WE#) column address strobe (CAS#) output is “High”
When the level changes from "H" level to "Low" level, the output of terminal WEB.

A "High" level indicates a read cycle, and a "Low" level indicates a write cycle.

(23) Data transfer/output enable (DT$t10E#) Terminal DT#/○E# is connected to the frame buffer 205 at V
This is an output terminal used only when RAM (2-point DRAM) is used. When the output of the row address strobe (RAS#) changes from "High" level to "Low" level, the output from terminal DT#10E#
When writing data from the VRAM serial input/output to the frame buffer 205, the column address strobe (C
When the output of AS#) changes from M High (M High), I+ level to "Low" level, terminal OE# becomes "High" level.
On the other hand, when reading data from the frame buffer 205 to the graphic processing device 100, the output of the column address strobe (CAS#) becomes "Hi" level.
When the level changes from "gh" level to "Low" level, terminal OE# becomes "Low" level.

(25) Display Status (DS#) A "Low" level is output to the terminal DS# only during the period when the frame buffer 205 is in the display memory cycle.

(26) Horizontal synchronization (H5YNC#) A signal for horizontal synchronization of the CRT display device 207 is output to the terminal HS Y N CR1m.

(27) Vertical synchronization (VSYNC#) A signal for vertical synchronization of the CRT display device 207 is output from the terminal VSYNC#.

(28) Display timing (DISP#) Child DIsP#
The period during which "Low" level is output is the screen display period of the CRT display device 207.

(29) Cursor data (CURD 3-CURD
O) Cursor data to be displayed on the CRT display device 207 is output to the terminals CURD3-CURDO.

(30) Cursor mask data (CURM, 3-C
URMO) Mask data for displaying a cursor on the CRT display device 207 is output to terminals CURM3-CURMO.

(31) Cursor display timing (CURDISP#)
The period in which the "Low" level is output to the terminal CURDISP$t indicates the period in which the force and the crane are displayed.

Internal Configuration> FIG. 3 shows the internal configuration of the graphic processing device 100. The graphic processing device 100 includes a drawing processing unit (DPU) 101.
．． Memory management unit (MMU>102, bus control unit (BCU) 103°CRT control unit (CCU)
104. System bus interface (SBI) 1
05. and local bus interface (LBI)
106.

The drawing processing unit 101 decodes the drawing command sent from the system bus interface 105 and calculates the address of the data to be processed. At this time, if the data to be processed is on the main memory 203, the address is transferred to the memory management unit 102 and a request is made to fetch the data to be processed. On the other hand, if the data to be processed is on the frame buffer 205, the address is transferred to the local bus interface 106 and a request is made to fetch the data to be processed. Data to be processed is transferred to the drawing processing unit 101 via the system bus interface 105 or the local bus interface 106.

The drawing processing unit 101 uses internal arithmetic units and registers to process the fetched data to be processed according to the drawing command.The zero-order drawing processing unit 101 calculates the storage address of the processed data. If the storage address is on the main memory 203, the processing data is transferred to the system bus interface 105 and the storage address is transferred to the memory management unit 102 so that the processing data is stored in the main memory 203. On the other hand, if the storage address is on the frame buffer 205.

The processing data and storage address are transferred to local bus interface 106 so that the processing data is stored in frame buffer 205 .

The memory management unit 102 is a drawing processing unit 101.
The address (virtual address) transferred from the memory management unit 102 is translated into a physical address by referring to the address translation table in the memory management unit 102.

The translated physical address is transferred to system bus interface 105. When accessing the main memory 203 using this physical address, it is first necessary to acquire the right to use the system bus 211. For this,
The memory management unit 102 is connected to the bus control unit 103.
to acquire the right to use the system bus 211. Further, when referring to the address conversion table to convert a virtual address to a physical address, if a lack of data for address conversion is detected, the memory management unit 102 sends the bus control unit 103 to the system bus 211. After obtaining usage rights, the main memory 20 is transferred via the system bus interface 105.
3, the address translation table in the memory management unit 102 is changed, and necessary address translation data is created. At this time, if it is detected that there is no page table related to the virtual address to be converted or a page frame containing data pointed to by the virtual address on the main memory 203, the memory management unit 102 , the central processing unit 201 is requested to perform page swapping.

Furthermore, when the drawing processing unit 101 writes data to a certain page frame on the main memory 203 for the first time, the memory management unit 102 writes the data in the page table entry on the main memory 203 corresponding to that page frame. An access bit indicating that the page frame has been referenced and a modification bit indicating that the contents of the page frame have been changed are set. Also, in the case of reading, the memory management unit 102 sets only the access bit in the page table entry on the main memory 203 corresponding to the page frame.

The bus control unit 103 is connected to the memory management unit 102.
System bus interface 1 at the request of
05 to obtain the right to use the system bus 211.

The CRT control unit 104 generates synchronization signals corresponding to two types of scanning modes, non-interlaced mode and interlaced sync & video mode, and controls the CRT display device 207 via the local bus interface 106. Output to. It also generates address information for refreshing the DRAM and VRAM used in the frame buffer 205. The address information is
Output from memory addresses (MA 11-MA O) via local bus interface 106. Furthermore, the cursor data defined on the frame buffer 205 is read from the memory data (Mn31-MDO) via the local bus interface 106, shifted, and then transferred via the local bus interface 106. , cursor data (CtJR
D3-CURDO) and cursor mask data (CU
RM3-CURMO). This achieves high-speed cursor display.

The system bus interface 105 supplies an internal clock for synchronizing processing execution to each unit in the graphic processing device E100, as well as an address bus (A31-A2) and a data bus (D31-A2). Do), address status (ADS#), quick (QUIC)
K#), write/read (W/R#), data ready (READY#), chip select (C8#), frame buffer select (FS#), bus hold request (HOLD), bus・Central processing unit 201 external to graphics processing unit 100 using hold acknowledge (HLDA), bus mask (BM#), reset (RES#), suspend (SUS#), and interrelated request (IRQ#) ．． main memory 20
3. Communicates with the bus arbitration device 202. It also includes a control register to synchronize processing operations in each unit and control data transfer timing.

Local bus interface 106 is a system
While synchronizing the internal clock supplied from the bus interface 105 with the display control clock input from the terminal DISPCLK,
LKOUT), memory address (MAl 1-MAO
), memory data (Mn21-MDO), row address strobe (RAS#), column address strobe (CAS#), write enable/L/ (w
E#), data transfer/output enable (DT#10E#), output enable (
○E#), display status (DS#), horizontal synchronization (H8
YNC#), vertical synchronization (VSYNC#), display timing (DISP$t), cursor data (CURD3-
CURDO), cursor mask data (CURM3
-CURMO), cursor display timing (CURD)
A frame buffer 205, a video converter 20G,
Communicates with CRT display device 1207.

<System Bus Access of Graphic Processing Apparatus 100> The graphic processing apparatus 100 uses a system bus to transfer data between the main memory 203 and the frame buffer 205. First, the procedure will be explained using FIGS. 1 and 4. Since the system bus is normally used by the MPU 201, the graphic processing device 100 outputs a bus request signal (HOLD) to the bus arbiter 202 in order to obtain the right to use the bus. The bus arbiter 202, when the HOLD signal is asserted.

Requests the MPU 201 to release the system bus. When the memory access being executed is completed, the MPU 201 releases the bus and notifies the bus arbiter that the bus has been released. The node arbiter 202 informs the graphics processing device ioo that the system bus has been released.
The graphics processing device 100 that sends the DA signal is
When the graphics processing device 100 recognizes that the system bus has been released by the HLDA signal, it starts accessing the main memory 203 and asserts the BM# signal indicating that the system bus is in use. Upon completion, the HOLD signal is negated and the right to use the system bus is returned to the MPU 201.

A problem with the process shown in FIG. 4 is that in order to improve the processing speed, it is necessary to efficiently control bus arbitration between the graphic processing device 100 and the MPU 201. M.P.
Since U201 needs to perform urgent processing, the graphic processing device 100 cannot use the system bus for a long time using the conventional burst mode. Furthermore, if the MPU 201 and the graphic processing device 100 are switched for each memory access, the arbitration time will increase and the performance will deteriorate. Generally, the emergency processing of the MPU 201 is activated by one interrupt. Therefore, in the present invention, when an interrupt signal to the MPU 201 is generated.

By a new method that allows the graphics processing device 100 to suspend use of the system bus.

A graphic processing device 100 is enabled to use a system bus continuously for a long time.

FIG. 5 shows that the SUS# control circuit 212 sends a message to the graphic processing device 100 when an interrupt to the MPU 201 occurs.
0 graphic processing device io which is a time chart showing the operation of asserting the SUS# signal.

When the 5tJS# signal is asserted, the system bus is released and the HOLD signal and BM# signal are negated.

MPU 201 can then use the system bus. M
After the emergency processing of PU201 is completed.

When the SUS# control circuit 212 negates the SUS# signal, the graphic processing device 100 can resume processing.

FIG. 6 is a time chart when the graphic processing device 100 accesses the main memory. Read and write operations are performed in 5 states, with one cycle of the internal operation clock being one state.
It is based on 4 states. The light cycle is W/
This is indicated by the R# signal going high. A read cycle is indicated by bringing the W/R# signal low. If the READY$ signal is high at the end of a read or write cycle, the cycle is extended. In Figure 6, READY is set to the fourth state of the read cycle and the next state.
Since the # signal is at a high level, a two-state wait cycle is inserted.

Next, a method for controlling the SUS# signal will be explained.

FIG. 7 shows the hardware configuration necessary for controlling the SUS# signal. 1 graphic processing device 100 and MPU 201
In addition to, SUS# control circuit 212, interrupt control circuit 2
13. 0 interrupt control circuit 2 with RTE generation circuit 214
13 performs priority processing on a group of interrupt signals from other devices (not shown), and then requests an interrupt to the MPU 201 using an INT signal. On the other hand, the MPU 210 returns a response signal to the interrupt signal as an INTA signal to the 1-interrupt control circuit 213, and the SUS# control circuit 1212 asserts the SUS# signal in response to the INT and INTA signals. The RTE generation circuit 214 is the MPU 20
The RTE signal is used to notify the SUS# control circuit 212 that the interrupt processing of No. 1 has been completed. The SUS$ control circuit 212 negates the SUS# signal using the RTE signal.

FIG. 8 is a logic diagram of the SUS# signal control circuit 212. It consists of a flip-flop 2121 which is set by the INTA signal and reset by the RTE signal, and an OR gate 2122 which takes the logical sum of the signal of the flip-flop 2121 and the INT signal. The configuration shown in FIG. 8 first generates the SUS# signal using the INT signal.
To enable a PU 201 to quickly execute interrupt processing. Here, after the INT signal is asserted, the MPU2
01 may be negated immediately before generating the INTA signal depending on the circumstances of a device (not shown). That is, even if the INT signal is generated, the MPU 201 may not execute interrupt processing. Therefore, MPU20
1 asserts the INTA signal and the flip-flop 21
Set 21. 9S shows the time chart of FIG. 8, and FIG. 10 is a flowchart showing the processing contents of the MPU 201. When the MPU 201 is performing normal processing, when an interrupt occurs due to the INT signal t, the normal processing is interrupted and emergency processing is performed.After performing the emergency processing, the processing shown in FIG. RTE generation circuit 2
14 to negate the SU]$ signal,
Return to normal processing.

As shown in Figure 10, there is not one emergency process.

There are multiple depending on the number of interrupts. Therefore, processing for negating SUS# must be provided in each interrupt routine. There is no problem if the software for the MPU 201 is created from the beginning on the premise that the graphic processing device 100 shown in this embodiment is used, but in a system where the graphic processing device 100 is added later, the SUS# for the existing software is This is a big problem because the additional parts of the negation process are wide-ranging. Therefore, a method that minimizes changes to existing software is desired. FIG. 11 shows a hardware configuration for solving such problems. This FIG. 11 shows the seventh
In contrast to the configuration shown in the figure, the interrupt signal IRQ3F from the graphic processing device 100 is connected to the interrupt control circuit 213. When the SUS# signal is asserted, the IR(l
A signal is also asserted. By doing it this way.

The processing of the MPU 201 is as shown in FIG.

After the MPU 201 finishes processing an interrupt from a device (not shown), it returns to normal processing, but is immediately interrupted by an interrupt from the graphic processing device 100.

Executes processing to negate SUS#. Therefore.

Existing software can be changed by simply adding an interrupt for the graphic processing device 100.

Next, with reference to FIG. 13, a method in which the process of negating the SUS# signal does not depend on software will be described. MPU
201 uses an interrupt ilJ control @ 1213 having a function of outputting an interrupt level signal during execution, and the RTE generating circuit 214 is configured to decode the interrupt level signal. The software in FIG. 13 is 1 graphic processing device 10.
Even in a system that does not use 0, the 1 interrupt control circuit 213 is configured to instruct the interrupt level to be executed by the MPU 201, so there is no need to change the software to negate SUS#.

As another example, in FIG.

A case will be described in which the MPU 201 has a function of outputting an RTE signal, which is a 5-interrupt processing end signal.

The interrupt control circuit 213 receives an interrupt signal from a device (not shown), determines the priority order, and then sends an interrupt signal to the MPU.
201 with an INT signal. The SUS# control circuit 212 controls the graphic processing device io by the INT signal.
Assert the SUS# terminal of o. After that, MPU20
1 executes one interrupt process and finally executes the interrupt end instruction.

Assert the RTE terminal for a predetermined period of time.

The SUS# control circuit 212 negates the SUS# signal when the RTE signal is asserted.

As described above, according to the configuration shown in FIG. 14, no software processing is required for controlling the SUS# signal.
Changes to existing software can be reduced.

According to the embodiment described above, in a system that transfers bitmap data between the main memory 203 and the frame buffer 205, interrupt processing of the MPU 201 occurs while the graphic processing device 100 is accessing the system bus. When the bus is opened, the terminal (SUS#
), the graphic processing device 100 can use the system bus continuously, thereby improving system bus usage efficiency. Therefore, it is possible to improve the processing speed. In addition, for existing systems,
Since only a few software changes are required, it is easy to add one graphic processing device 100 later.

[Effects of the Invention] According to the present invention, in a system in which one graphics processing device accesses the main memory, the graphics processing device detects that an interrupt to the MPU occurs while accessing the system bus, and also releases the system bus. In order to do - time,
After interrupting drawing processing or data transfer and letting the MPU execute the processing, it is possible to resume the single processing without requiring software intervention. It will also be possible to respond quickly to processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a system configuration according to an embodiment of the present invention, FIG. 2 is a diagram showing a terminal configuration when the graphic processing device 100 is implemented as an LSI, and FIG. 3 is an internal diagram of the graphic processing device 100. FIG. 4 is a diagram showing the configuration, and FIG. 4 is a diagram showing the arbitration timing when accessing the system bus of the graphic processing device 100.
FIG. 5 is a diagram showing the timing of temporarily releasing the system bus to the MPU using the SUS# terminal of the graphic processing device 100, FIG. 6 is a diagram showing the memory cycle when the graphic processing device 100 accesses the main memory, FIG. 7 is a diagram showing the hardware configuration for controlling the SUS# signal by software, FIG. 8 is a diagram showing the logical configuration of the SUS# control circuit 212, and FIG. 9 is a diagram showing the SUS# control circuit 2.
FIG. 10 is a diagram showing the processing flow of the MPU 201 corresponding to FIG. 7. FIG. The figure is M corresponding to Figure 11.
FIG. 13, a diagram showing the processing flow of the PU 201, shows that the interrupt control circuit 213 outputs an interrupt level signal to
PU201(7) SUS#*H#(7)'/7 A diagram showing an example of a configuration where toeware is no longer required, Figure 14 is M P
FIG. 12 is a diagram illustrating a configuration example in which software for 5usn control of the MPU 201 is no longer required by having a terminal indicating that U 20 L has finished interrupt processing. 100... Graphic processing device, 201... Central processing unit, 202... Bus arbiter, 203... Main memory, 205... Frame buffer, 206... Video signal generation circuit, 207... Display Device, 208...
Control bus, 209...Data bus, 210...
...Address bus, 211...Decoder, 212...
・SUS control circuit, 213...Interrupt control circuit, 2
14...RTE generation circuit.

Claims (1)

[Claims] 1. At least between a central processing unit that executes data processing and a graphic processing unit, and between a main memory that stores data processed by the central processing unit and the graphic processing unit. A system bus interface for enabling data exchange, and detecting the processing content from the data obtained from the system bus interface, calculating an address pointing to at least one data to be processed in the main memory, and executing the above processing. Requesting the system bus interface to read at least one data from the main memory according to an address pointing to the target data, and processing the at least one data obtained from the system bus interface as a result according to the processing contents. , in the graphic processing device having a drawing processing unit that requests the system bus interface to write the processing result to the main memory according to an address for storing the processing result, the processing using the main memory is performed. A graphics processing device characterized by having a dedicated input terminal for receiving control for suspending and resuming execution from the outside. 2. In the graphic processing device according to claim 1, bus arbitration is performed with an external bus arbitration circuit via the system bus interface to obtain access rights to the main memory, and the system bus A graphics processing device, wherein the interface includes a bus control unit that controls reading of data to be processed from the main memory and writing of processing results to the main memory. 3. Enable data exchange at least between the central processing unit that executes data processing and the graphic processing device, and between the main memory that stores data processed by the central processing unit and the graphic processing device. a local bus interface to enable data exchange between the frame buffer that stores data to be displayed on the display device and the graphic processing device; In addition to detecting the processing content, the address pointing to at least one data to be processed in the main memory and the address for storing the processing result in the frame buffer are calculated, and the address pointing to the data to be processed is calculated according to the address pointing to the data to be processed. , requests the system bus interface to read at least one data from the main memory, processes the at least one data obtained from the system bus interface according to the processing content, and stores the processing result. In the graphics processing device, the graphic processing device includes a drawing processing unit that requests the local bus interface to write the processing result to the frame buffer according to an address for interrupting and resuming execution of processing using the main memory. The graphic processing device described above has a dedicated input terminal for receiving control from the outside. 4. In the graphic processing device according to claim 3, bus arbitration is performed with an external bus arbitration circuit via the system bus interface to obtain access rights to the main memory, and the system bus A graphics processing device, wherein the interface includes a bus control unit that controls reading processing target data from the main memory and writing processing results to the main memory. 5. A main memory for storing data, a central processing unit for processing at least the data on the main memory, and at least a system bus for enabling data exchange between devices, according to instructions from the central processing unit. When processing the bitmap data existing on the main memory, the data processing device connected to the graphics processing device executes the processing of the graphics processing device on the bitmap data existing on the main memory. What is claimed is: 1. A data processing device that controls interruption and resumption of data processing using an external interrupt request signal. 6. A main memory for storing data, a central processing unit for processing at least the data on the main memory, and a system bus for enabling data exchange between devices, and a central processing unit for processing at least the data on the main memory; When processing bitmap data existing on the main memory and bitmap data existing on a frame buffer that stores data to be displayed on a display device, a graphic processing device is connected, and the system bus and In a data processing device in which the graphic processing device and the frame buffer are connected to a physically separated local bus, the graphic processing device executes processing on bitmap data existing in the main memory. A data processing device characterized in that suspension and resumption are controlled using an external interrupt request signal. 7. In a graphic drawing method using a data processing device that includes a central processing unit for data processing and a graphic processing device that processes at least bitmap data existing on the main memory, execution of exception processing by the central processing unit. At the beginning of the processing, the processing of the graphic processing device is interrupted for the bitmap data existing on the main memory, and at the end of the execution of the exception handling, the execution of the processing of the bitmap data existing on the main memory is interrupted. , a graphic drawing method characterized by performing a process of restarting execution of processing by the graphic processing device. 8. A central processing unit for data processing, characterized in that the central processing unit is equipped with an output terminal for transmitting to the outside the end of execution of exception processing. 9. A central processing unit for data processing, characterized in that the central processing unit is equipped with an output terminal for transmitting to the outside the priority level of exception processing currently being executed. 10. A central processing unit for data processing, characterized in that the central processing unit is equipped with a function for acquiring a system bus necessary for executing exception processing when an interrupt request is received.