JPH03128529A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To prevent deviation from being generated totally even in the case of preparing a frequency not to be just divided by an original clock or the clock of a frequency to be a recurring decimal by outputting a trigger every time the counted value of the clock reaches the integer of a mixed number, comparing the cumulative value of numerator in a remainder with a denominator and correcting the remainder. CONSTITUTION:Data such as an integer M1 of the mixed number, the numerator M2 of the remainder and the denominator N of the remainder in the case of dividing the frequency of the clock to be inputted with the frequency of the desired clock are inputted to a clock generating circuit and respectively fetched into a comparing register 10, remainder register 12 and divisor register 14. Every time the counted value of the clock reaches the M1, the M2 is accumulated and when the cumulative value is larger than an N, the remainder is corrected occasionally so as to output the trigger when the counted value of the clock is M1+1 (namely, while delaying timing to output the trigger by 1 clock).

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock generation circuit that generates a clock of another frequency from a clock of a certain frequency. can be created.

[Conventional technology]

In digital equipment, clocks of various frequencies are created from a master clock and used to control each part. When creating a clock with a different frequency from a certain clock, the frequency of the clock is usually divided using a counter.

[Problem to be solved by the invention]

However, when creating a clock by dividing the frequency with a counter,
The division ratio of the original clock must be an integer multiple,
If you try to create a clock with a frequency that is not divisible by the original clock frequency, the decimal point will be off and the timing will gradually shift. Increasing the bit precision can be considered to prevent such deviations, but 1/
With repeating decimal numbers such as 3° 1/7, no matter how much bit precision you increase, the discrepancy will remain.

Therefore, in the end, it was necessary to use a clock whose frequency was divisible by the clock to be created. However, with this method, for example, 44.
a PCM audio signal having a sampling frequency of 1 kll, 48 kHz, 32 kHz, etc.; 32.
25kHz MIDI (Muslcal I)
nstrumentDigital Interface
e) When synchronizing electronic sounds by control,
An extremely high frequency is required for the master clock, and high-speed processing is also required.

The present invention solves the problems in the conventional technology and creates a clock with a frequency that is not divisible by the original clock or a frequency that is a cyclic decimal, and uses a relatively slow clock to eliminate the deviation. The present invention aims to provide a clock generation circuit that can generate a clock of any frequency.

[Means to solve the problem]

This invention includes a comparison register that holds an integer of a mixed number when the frequency of a manually inputted clock is divided by a desired clock frequency, and a remainder register that holds the same number of molecules.
a divisor register that holds the same denominator, a counter that counts the input clock, and a first comparator that issues a trigger and clears the counter every time this count value reaches a value corresponding to the integer; an accumulator that accumulates the number of molecules each time the trigger is issued;
a second comparator that detects that the cumulative value has become larger than the denominator number and increases the count value for issuing the trigger by 1; and a second comparator that detects that the cumulative value has become larger than the denominator number. and a subtractor that subtracts the denominator number from the accumulated value to obtain a new accumulated value each time the accumulated value is detected, and outputs the trigger as the desired clock. It is.

[For production]

According to this invention, a trigger is issued every time the count value of the clock reaches an integer of the mixed number, and this becomes the output clock. Then, each time a trigger is issued, the remainder number of numerators is accumulated, and when the accumulated value becomes larger than the denominator number, when the clock count value becomes the integer + 1 (i.e., the timing to issue a trigger) (delayed by one clock) so that the trigger is issued, and the remaining number is extracted from time to time.

As a result, even when creating a clock with a frequency that is not divisible by the original clock or a frequency that is a repeating decimal number, there will be no deviation in total, and a relatively slow clock can be used, and the processing speed is also slow. I will come to live.

〔Example〕

An embodiment of this invention is shown in FIG. Here, the division ratio M
/N (M, N are integers, M>N) shall be created.

Replace M/N with a mixed number M1+ (M2/N). Here, Ml is an integer, M2/
N is a remainder number, M2 and N are integers, and M2<N.

Data of an integer M1, a numerator number M2 of the remainder number, and a denominator number N of the remainder number are input to the circuit shown in FIG. 1, and are taken into a comparison register 10, a remainder register 12, and a divisor register 14, respectively. /X Inoku Itose, Soto circuit 16 is upper and lower 8
Each data M1, M2 . N
is converted to the original 16-bit data and each register 10 is
, 12.14.

The original clock signal is generated by the clock generator 16, and when the counter start signal output from the 1-clock delay circuit 17 is rising, it is added to the counting power of the counter 20 via the AND circuit 18, and is counted up. do.

The comparison selector 22 selects Ml-1 (when not correcting the remainder) or Ml (when correcting the remainder),
The selected value is latched into the comparison register latch circuit 24. Comparator 26 (first comparator) is counter 2
The value of 0 is compared with the value latched in the comparison register circuit 24, and when the counter value reaches the latched value, the comparison output C1
is output, delayed by one clock in the one-clock delay circuit 28, and outputted via the NOR circuit 30. The output of this NOR circuit 30 becomes the frequency-converted clock output CL'.

Further, the output of the NOR circuit 30 is added to the manual clearing power of the counter 20 via the NOR circuit 32 to clear it. Further, the output of the NOR circuit 30 is applied to the comparison register circuit 24 via the OR circuit 34, and a new output of the comparison selector 22 is latched.

The output from the subtracter 38 is added to the numerator number of the remainder held in the remainder register 12 by an adder 36, and the added value is divided by the signal from the OR circuit 30 that is output from the OR circuit 42. It is taken into the correction accumulator 40. The output of this accumulator 40 is returned to the adder 36 via the subtracter 38 and is accumulated.

A comparator 44 (second comparator) uses the denominator of the remainder held in the divisor register 14 and the accumulator 4.
0 output, and when the output of the accumulator 40 is larger, a comparison output C2 is output. This comparison output C2 is applied to the comparison selector 22 via the AND circuit 46, and selects Ml (other than this selects M-1). As a result, correction for the remaining number is performed.

In addition, the comparison output C2 is applied to the AND circuit 48, which sends the denominator number N held in the divisor register 14 to the subtracter 38 (otherwise, the output of the AND circuit 48 is O), and corrects N from the accumulated value. Subtract that amount to get the new cumulative value.

Note that when you want to see how far the counter 20 has progressed, the counter 1 wrap circuit 50 sends a count 1 lap signal at the desired timing, latches the count value of the counter 20 at that time to 16 bits, and then outputs the next count value. It is held until the counter 1 wrap signal is given to the counter.

This allows accurate values to be read even if there is a lag between the actual latch timing and the time to read the value. In particular, when the circuit of FIG. 1 is attached to an 8-bit CPU and operated, an example of the operation of the circuit of FIG. 1 will be explained, which is effective because it has to be read twice. Here, it is assumed that the original clock CL is 100 Hz and seven clock outputs CL' are obtained. At this time, the frequency division ratio is 100/
7, and the mixed number is 14+ (2/7).

Therefore, it becomes 1-14 2-2 N 7. Each of these data Ml, M2. N is input from the outside and held in each register 10, 12.14. Initially, the counter 20 and accumulator 40 are cleared. When the operation is started, the comparison selector 22
1-1-13 is selected and latched into the comparison register latch circuit 24. When the counter start signal is raised, the counter 20 counts the clock CL.

When the count value reaches 13, the comparator 26 outputs a comparison output C1, which is delayed by one clock in the one-clock delay circuit 28, and a trigger is issued at the 14th count. This becomes the converted clock CL'.

Since the accumulator 40 is initially 0, it takes in the output value 2 of the remainder register 12 when the trigger signal is applied. The counter 20 is reset by the trigger and repeats counting again.

Similarly, a trigger is generated after 14 counts, and [output value 2 of accumulator 40]+[output value 2 of remainder register 12]-4 is newly taken into accumulator 40. After the next count of 14, there is a bird, and 4+2-6 is taken into the accumulator 40. Furthermore, after 14 counts, the bird becomes accumulator 4.
6+2-8 is taken into 0.

Then, since the comparator 44 becomes A>B,
Comparison output C2 is sent to comparison selector 2 via AND circuit 46.
2 and selects Ml-14.

When this occurs, a trigger is issued at the 15th count of the counter 20, and the remainder is corrected. Also, when this correction is performed, the AND circuit 48 is turned on and N-7 is output from the subtracter 3.
8 and 8-7-1 is output from the subtracter 38.

Therefore, next time, 1+2 is taken into the Akinimulator 40, and the comparison output C2 of the comparator 44 falls.
Comparison selector 22 again outputs Ml-1-13.

The above operations can be summarized as follows.

In this way, the trigger is applied seven times during 100 clocks of the input clock CL. In other words, no matter how many numbers are counted, the error in the count is only the amount of the input clock precision.

Note that by increasing the number of bits of the accumulator 40, more complex fractions can be handled.

〔Effect of the invention〕

As explained above, according to the present invention, each time the count value of the clock reaches an integer of the fraction, a trigger is issued to accumulate the numerator of the remainder, and when the accumulated value becomes larger than the denominator, , the trigger is issued when the clock count value reaches the above integer + 1, and the remainder is sometimes corrected, so it can also be used when creating a clock with a frequency that is not divisible by the original clock or a frequency that is a repeating decimal. There is no total deviation, a relatively slow clock can be used, and the processing speed can be slow.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 10...Comparison register, 12...Remainder register, 1
4...Divisor register, 20...Counter, 26...
- First comparator, 40... Division correction accumulator (accumulator), 44... Second comparator, 38.
...Subtractor, CL...Manual clock, CL'...
Output clock.

Claims (1)

[Claims] A comparison register that holds an integer of a mixed number when the input clock frequency is divided by a desired clock frequency, a remainder register that holds the same number of numerators, and a same denominator number. a divisor register; a counter that counts the input clock; a first comparator that issues a trigger and clears the counter each time the count value reaches a value corresponding to the integer; and a first comparator that clears the counter each time the trigger is issued. an accumulator that accumulates the number of numerators, a second comparator that detects that the accumulated value is larger than the denominator number and increases by 1 a count value that issues the trigger; a subtracter that subtracts the denominator number from the accumulated value to obtain a new accumulated value each time it is detected that the accumulated value is larger than the denominator number, and the trigger A clock generation circuit which outputs the desired clock as the desired clock.