JPH03127512A - Level shift circuit - Google Patents

Abstract

PURPOSE:To allow one circuit enough to shift both high and low levels of an input voltage by obtaining an output voltage in assuming the voltage level of a 2nd high voltage power supply as an H level, and the voltage level of a 2nd low voltage power supply is taken as an L level. CONSTITUTION:An output voltage of a logic level opposite to that of an input signal is obtained from a 1st intermediate stage circuit section B1, in which a voltage level of a 1st high voltage power supply 2 is assumed as an H level and a voltage level of a 1st low voltage power supply 4 is assumed as an L level in response to an output voltage of a 1st circuit section A. Moreover, an output voltage of a logic level opposite to that of an input signal is obtained from a 2nd intermediate stage circuit section B2, in which a voltage level of a 2nd high voltage power supply 5 is taken as a logical H level and a voltage level of a 1st low voltage power supply 3 is taken as a logical L level. Furthermore, an output voltage of a logic level the same as that of an input signal is obtained from final stage circuit sections C1, C2, in which a voltage level of the 2nd high voltage power supply 5 is assumed as an H level and a voltage level of a 2nd low voltage power supply 4 is assumed as an L level in response to the output voltage of the 1st and 2nd intermediate stage circuit sections B1, B2. Thus, one circuit is enough to shift both the high and low levels to a different level.

Description

[Detailed description of the invention] [Industrial use! ]'F) The present invention relates to a level shift circuit that converts an input terminal of a certain voltage system to a voltage level of another voltage system and outputs the voltage level.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional C-MO3 level shift circuit.

In the figure, the voltage level input to input terminal 1 is Ov
The first stage circuit section A, which receives an input terminal of ~+5V, has two inverters a and a2 connected in cascade to form a circuit 11i3c. That is, the previous stage inverter a connects the drain of the P-channel transistor Ql and the N-channel transistor Q2.
On the other hand, the source of the P-channel transistor Ql is connected to the high potential (+5V) power supply 2, and the source of the N-channel transistor Q2 is grounded, that is, the source is connected to the low potential (0■).
connected to power supply 3 respectively, and P-channel transistor Q
The gate of an N-channel transistor Q2 is connected to the input terminal 1, and the connection point between the drain of the P-channel transistor Ql and the drain of the N-channel transistor Q2 is the output terminal of the inverter a1.

Similarly, for the inverter a2 in the subsequent stage, the drain of the P-channel transistor Q3 and the drain of the N-channel transistor Q4 are connected, while the source of the P-channel transistor Q3 is connected to the high potential (+5V) power supply 2.
The source of the channel transistor Q4 is connected to the low potential (Ov) power supply 3, and the gates of the P-channel transistor Q3 and N-channel transistor Q4 are connected to the blade terminal of the inverter at in the previous stage, and the P-channel transistor Q3ty>drain. The connection point between the inverter a2 and the drain of the N-channel transistor Q4 is the output terminal 3''- of the inverter a2.

The next stage [11i1 road section B also has two inverters b, b
2, and one inverter bt has one P-channel transistor Q5 and two N-channel transistors Q and Q7.
are connected in series, and the other inverter b2 also has one P-channel transistor Q and two N-channel transistors Q, Q8.
Each of them is constructed by connecting 9 In in series.

In other words, the inverter bI is connected to the drain of the P-channel transistor Q6, and the inverter bI is connected to the drain of the P-channel transistor Q6.
While connecting the source of B and the drain of N-channel transistor Q7, the source of P-channel transistor Q5 is connected to high potential (+5 V) power supply 2, and the source of N-channel transistor Q7 is connected to low potential (-10 V) 11i source 4. The gates of the P-channel transistor Q5 and the N-channel transistor Q are connected to the above-mentioned inverter a.
The gate of N-channel transistor Q7 is connected to the output terminal r of inverter b2, which will be described later, and the connection point between the drain of P-channel transistor Q and the drain of N-channel transistor QB is connected to this inverter. It is used as the output terminal of bl. Also,
Similarly, for the other inverter b2, the drain of the P-channel transistor Q and the drain of the N-channel transistor Q9 are connected, the source of the N-channel transistor Q is connected to the drain of the N-channel transistor Q10, and the drain of the P-channel transistor The source of Q8 is connected to high potential (+5 V) power supply 2, the source of N channel transistor Q1o is connected to low potential (-10 V) J source 4, and P channel transistors Q8 and N
of channel transistor Q9. The gate is connected to the output terminal r of the above-mentioned inverter a2, and the N-channel transistor Q
10 gates are connected to the output terminal of the inverter b1, respectively, and the connection point between the drain of the P-channel transistor Q8 and the drain of the N-channel transistor Q9, which are the output terminals of the inverter b2, is as described above. N-channel transistor Q7 of inverter b1
connected to the gate.

Next, the operation of the level shift circuit will be explained.

When the signal input to input terminal 1 is at L level (-0V), P-channel transistor Ql of inverter a1 in first-stage circuit section A is turned on, and N-channel transistor Q2 is turned on.
is turned off, so the output of this inverter a1 becomes H level ("+5 V). At this time, the P-channel transistor Q3 of the next stage inverter a2 is turned off, and the N-channel transistor Q4 is turned on, so this inverter The output of a2 becomes L level (αOV).

Further, since the P-channel transistor Q8 of the inverter b2 in the next stage circuit section B is turned on, the output of the inverter b2 becomes H level (-+5 V). Therefore, the gate of N-channel transistor Q7 of inverter b1 becomes H level, and N-channel transistor Q7 is turned on.

On the other hand, P-channel transistor Q of this inverter bt
An H-level signal from the inverter a1 is applied to the gates of the tunnel transistors Q6 and 5, and the P-channel transistor Q5 is turned off and the N-channel transistor QB is turned on. Therefore, the output of inverter bI becomes L level (--10V). This output is given to a logic circuit G1 (see FIG. 4) provided at the next stage of this level shift Irjl path S1.

Next, the signal input to input terminal 1 is at H level (-+5
In the case of V), all the logic of the above-mentioned operation is reversed, and the output terminal of the next stage circuit section B, that is, inverter b
An H level (+5V) output can be obtained from the output terminal of 1.In other words, for an input voltage of OV~→-5V, -1
An output voltage of 0V to +5V will be obtained.

[Problems to be Solved by the Invention] Since the conventional level shift circuit is configured as described above, it is possible to level shift only one of the high and low potentials of the input terminal. In other words, either the high potential or the low potential will be the same as the voltage level at the time of input.

Therefore, the input voltage of Ov~←5V can be changed to ±10V, for example.
As shown in FIG. 4, the output voltage of -10V to +5V extracted from the semiconductor integrated circuit ICI including the level shift circuit S1 and the logic circuit G1 described above is transferred to another level shift circuit. A level shift circuit is required at S2 (connected to a +10V high potential power supply 5 and a -10V low potential power supply 4), and there is a problem that a two-stage level shift process is required, making the process complicated. Ta.

The present invention was made to solve these problems, and aims to provide a level shift circuit that can shift both the high potential level and the low potential level of the input terminal with one circuit. 1 target.

[Means for resolving issues]

A level shift circuit according to the present invention includes an inverter connected to a first high potential power source and a first low potential power source,
In response to an input signal, the voltage level of the first high potential power supply is set to i.
an initial stage circuit section that obtains an output voltage that sets the voltage level of the first low potential power supply to the L level; and a second low potential that is lower than the voltage level of the first high potential power supply and the first low potential power supply. It includes an inverter connected to a power supply, and responds to the output voltage of the first stage circuit section to generate an output voltage with the opposite logic to the input signal, and sets the voltage level of the first high potential power supply to H level and the second
a first middle-stage circuit section that obtains an output voltage that makes the voltage level of the low potential power supply L level; a second high potential power supply higher than the voltage level of the first high potential power supply; and a first low potential power supply. In response to the output voltage of the first stage circuit section, the output voltage is the opposite logic to the input signal, and the voltage level of the second high potential power supply is set to H level, and the voltage level of the first low potential power supply is set to H level. A second middle-stage circuit section that adjusts the output voltage to make the voltage level L level, a second high potential power supply, and a second low 1! In response to the output voltage of the first middle stage circuit section and the output voltage of the second middle stage circuit section, the input signal includes an inverter connected to a power supply. and a final stage circuit section that obtains an output voltage that sets the voltage level of the second high potential power supply to H level and the voltage level of the second low potential power supply to L level.

[Effect]

In this invention, in response to an input signal, the first crystal form α
An output voltage that sets the voltage level of the power supply at H level and the voltage level of the first low voltage (nTTi source at L level) is obtained in the first stage circuit section, and in response to this output voltage, the first middle stage circuit section It is an output voltage that sets the voltage level of the second high potential power supply to H level and the voltage level of the second low potential power supply to L level, and the output voltage has the opposite logic to the input signal, and the output voltage of the first stage circuit section In response, the second middle-stage circuit section outputs an output voltage that sets the voltage level of the second high potential power supply at H level and the voltage level of the first low potential power supply at L level, and which has the opposite logic to the input signal. Further, in response to the output voltages of the first and second middle stage circuit parts, the final stage circuit part sets the voltage level of the second high potential power supply to H level and the voltage level of the second low potential power supply to L level. An output voltage having the same logic as the input signal can be obtained, which is an output voltage of the same level as the input signal (that is, both the H level and the L level are level-shifted).

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a level shift circuit according to the present invention.

In FIG. 1, the first stage circuit section A (1
The four components are the same as the conventional circuit shown in FIG. 3, and the configuration of the first middle stage circuit section B1 is also the same as the next stage circuit section B in the conventional circuit except for the position of the output terminal r.

Here, the inverter at the front stage of the first intermediate circuit section B1 is indicated by the symbol b, and the inverter at the subsequent stage is indicated by the symbol b+2.

The second middle-stage circuit section B2 also consists of two inverters b and b like the first middle-stage circuit section B1, and the inverter b2+ of I22-)j is composed of two P-channel transistors QQ and one N-channel transistor 11'.
12 RiQ, 3'! : connected in series (5, and the other inverter b also has two P-channel transistors Q, Q22)
14 +5 and 1
Each transistor is constructed by connecting two N-channel transistors Q16 in series.

In other words, the inverter b21 is a P-channel transistor Q, which connects the drain of the transistor Q11 and the source of the P-channel transistor Q12, and connects the drain of the P-channel transistor Q12 and the drain of the N-channel transistor Q13. The source of the N-channel transistor Q13 is connected to the second high potential (+10V) power supply 5, and the source of the N-channel transistor Q13 is connected to the first low potential (OV) power supply 3.
are connected to the output terminal of the inverter b22 which follows the gate of the P channel transistor QII, and the P
The gates of channel transistor Q12 and N-channel transistor Q13 are connected to the output terminal of inverter a1, respectively, and P-channel transistor Q12
The connection point between the drain of the inverter b21 and the drain of the N-channel transistor QI3 is the output/terminal of the inverter b21. Similarly, for the other inverter b22, the drain of the P channel transistor Q14 and the P
The source of the P-channel transistor Q15 is connected to the drain of the N-channel transistor Q1B, and the drain of the P-channel transistor Q15 is connected to the drain of the N-channel transistor Q1B.
V) connect the sources of the N-channel transistors Q16 to the first low potential (Ov) power supply 3 to the fI power supply, and
The gate of the channel transistor Q14 is connected to the output terminal of the above-mentioned inverter b21, and the gates of the P-channel transistor Q and N-channel transistor Q1B are connected to the output terminal of the inverter a2. As described above, the connection point between the drain of a certain P-channel transistor Q15 and the drain of an N-channel transistor Q16 is connected to the P-channel transistor Ql of the inverter b21.
It is connected to the gate of l.

The first final stage circuit section C1 includes an inverter in which one P-channel transistor Q17 and two N-channel transistors Q Q are connected in series. That is, the final stage circuit section C1 includes the drain of the P-channel I transistor Q17 and the N-channel transistor Q.
18, and the N-channel transistor Q
18 and the drain of the N-channel transistor Q1° are connected, while the source of the P-channel transistor Q17 is connected to the second high potential (+10V) power supply 5, and the source of the N-channel transistor Q19 is connected to the second low potential (- 10
V) connected to the power supply 4, the gates of the P-channel transistor Q17 and the N-channel transistor Q18 are connected to the output terminal of the above-mentioned inverter b22, and the gate of the N-channel transistor QI9 is connected to the above-mentioned inverter b
The connection point between the drain of P-channel transistor Q17 and the drain of N-channel transistor Q18 is this final stage circuit section C.
1 output terminal.

Further, the second final stage circuit section C2 is composed of an inverter in which two P-channel transistors Q 1 and Q 2 and one N-channel transistor 2021 transistor Q22 are connected in series. That is, the final stage circuit section C2 connects the drain of the P channel transistor Q2o and the P channel transistor Q
21 and connects it to the source of P channel transistor Q2.
1 and the drain of N-channel transistor Q2□, while connecting the source of P-channel transistor Q2o to a second high potential (+1.OV) power supply 5,
The sources of N-channel transistor Q22 are connected to a second low potential (-10V) ftR source 4, respectively, and the gate of P-channel transistor Q2 is connected to the output terminal of inverter b22 as described above, and P-channel transistor Q2 is connected to the output terminal of inverter b22.
The gates of the 1 and N channel transistors Q22 are connected to the output terminals of the above-mentioned inverter b1□, respectively, and the drains of the P channel transistor Q21 and N
The I connection point with the drain of the channel transistor Q22 is the output terminal of this final stage circuit section C2.

Fig. fiS2 is a block diagram showing a configuration in which the level shift circuit S3 described above and the logic circuit G2 provided at the next stage are incorporated into one V conductor integrated circuit IC2.

Next, the operation of the level shift circuit S3 will be explained.

When the signal input to input terminal 1 is at L level (-〇V), P-channel transistor Ql of inverter al in first-stage circuit section A is turned on, and N-channel transistor Q2 is turned on.
is turned off, so the output of this inverter al becomes H level (-=+5V), the P-channel transistor Q3 of the next stage inverter a2 is turned off, and the N-channel transistor Q4 is turned on, so the output of this inverter a2 is It becomes L level (dumb OV).

At this time, in the first middle-stage circuit section B1, the P-channel transistor Q5 of the front-stage inverter bll is turned off, the N-channel transistor Q6 is turned on, the P-channel transistor Q8 of the rear-stage inverter b12 is turned on, and the N-channel transistor Q9 is turned on. It turns off. As a result, the output of inverter b12 becomes H level (=-+5V),
N-channel transistor Q7 of inverter b%1 is turned on, and the output of inverter bll is at L level (-
-10V).

On the other hand, in the second middle-stage Fit path section B2, the P-channel transistor Q12 of the previous-stage inverter b is turned off, the 1N-channel transistor Q13 is turned on, and the output of the inverter b21 becomes L level (=-OV). Furthermore, the P-channel transistors Q 1 and Q of the inverter b22 at the subsequent stage are on, and the N-channel transistor 14 1
5 transistor Q1B is turned off, and the output of its inverter b22 becomes H level (-+10V).

At this time, in the first final stage circuit section C1, the P-channel transistor Q17 is turned off, and the N-channel transistor Q17 is turned off.
Q is turned on and its output becomes L level (-10V). This output is applied to the logic circuit G2 (FIG. 2) provided at the next stage.

Furthermore, in the second final stage [+11 path section C2, the P-channel transistor QQ is off, and the N-channel transistor 20° 2
1 Register Q22 turns on, and its output also goes to L level (“-
10V). This output is also given to the logic circuit G2 (FIG. 2) provided at the next stage.

Next, the signal input to input terminal 1 is at H level (-+5v
), all the logic of the above-mentioned operation becomes an inverted operation, and the inverter bL at the rear stage of the first intermediate circuit section B1
L level ("=-10V) output is taken from 2,
An L level (-0V) output is taken out from the inverter b22 at the rear stage of the second intermediate circuit section B2. Therefore, in the final stage circuit section C1 of ml, the P-channel transistor Q17 is turned on, and the N-channel transistors 701g and Q1
9 is turned off, and an H level (-+10V) output is taken out. In the second final stage circuit section C2, P channel transistors Q and Q are on, and N channel transistor 02
1 Star Q22 is turned off and similarly high level (missing +10V
) is retrieved.

In this way, for the input terminals of 1]v to +5v,
-10V~ with shifted voltage level for both high and low potentials
An output voltage of +10v will be obtained. That is,
For example, as shown in FIG. 2, in the case of a semiconductor integrated circuit IC2 in which a level shift circuit S3 having the above configuration is provided at the front stage of a logic 11j1 path G2, OV~
The input voltage of +5V is -lO at the level shift circuit S3.
It is converted into V~+10v, processed by the logic circuit G2, and taken out from the output terminal 6 as a signal of =IOV~+10v.

〔Effect of the invention〕

As described above, according to the present invention, both the high potential level and the low m-level of the input terminal can be shifted to different voltage levels by one circuit. This eliminates the need to add another level shift circuit, and has the advantage that a logic circuit system can be constructed at low cost.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of a level shift circuit according to the present invention, FIG. 2 is a block diagram showing a configuration in which the level shift circuit and other logic circuits are combined, and FIG.
The figure is a circuit diagram showing a conventional level shift circuit, and FIG. 4 is a circuit diagram of a conventional level shift circuit, and FIG. FIG. 2 is a block diagram showing the configuration. In the figure, 1 is a human power terminal, 2 is a first high potential power supply, and 3 is a human power terminal.
is the first low potential power supply, 4 is the second Of, potential power supply, 5 is the second high potential power supply, and A is the first stage [! il 78 part, B1 is a first middle stage circuit part, B2 is a second middle stage circuit part, C1 is a first final stage circuit part, and C2 is a second final stage circuit part. Note that the same reference numerals in each figure indicate the same or relevant bones.

Claims (1)

[Claims] (1) includes an inverter connected to a first high potential power source and a first low potential power source, and sets the voltage level of the first high potential power source to an H level in response to an input signal; a first-stage circuit section that obtains an output voltage that brings the voltage level of the potential power source to an L level; and a second low potential power source that is lower than the voltage level of the first high potential power source and the first low potential power source. an inverter that responds to the output voltage of the first-stage circuit section and outputs a voltage having the opposite logic to the input signal, and sets the voltage level of the first high-potential power supply to an H level, and sets the voltage level of the first high-potential power supply to an H level. a first middle-stage circuit section that obtains an output voltage that makes the voltage level of the voltage L level, and a second high potential power supply higher than the voltage level of the first high potential power supply and the first low potential power supply connected to the second high potential power supply. and an inverter that responds to the output voltage of the first-stage circuit section to generate an output voltage having a logic opposite to that of the input signal, and sets the voltage level of the second high-potential power supply to an H level and outputs the first low-potential voltage. a second middle-stage circuit section that obtains an output voltage that makes the voltage level of the power source L level; and an inverter connected to the second high-potential power source and the second low-potential power source, the first middle-stage circuit section In response to the output voltage of the circuit section and the output voltage of the second intermediate circuit section, the output voltage is the same logic as the input signal, and the voltage level of the second high potential power supply is set to H level. and a final stage circuit section for obtaining an output voltage that makes the voltage level of a low potential power source L level.