JPH03126317A - Driver circuit capable of wired-and - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] 〔table of contents〕 overview Industrial applications Conventional technology (Figure 3) Problems that the invention aims to solve Means to solve the problem (Figure 1) Effect (Figure 1) Example (Figure 2) Effect of the invention 〔overview〕 Concerning wired and possible driver circuits.

The objective is to use a driver circuit using a resistance bias type Bi-CMOS logic circuit to configure a wired AND logic without causing element destruction.

The input terminal (two connected N-channel MOS transistors are connected in parallel, and the P-channel MOS transistor of the Bi-CMOS logic circuit In the front row of.

A delay circuit is connected to the input terminal and delays the input signal for a certain period of time, and the output of the delay circuit is used to switch.

When the Bi-CMOS logic circuit becomes a high level logic output, it becomes a high impedance output.

The configuration is such that a switch circuit is provided that forcibly sends out a high level logic signal to the P-channel MOS transistor.

[Industrial application field]

The present invention relates to a wired and capable driver circuit (more specifically, a resistive bias type Bi-CMOS
It is used when connecting multiple logic circuit driver circuits to form a wired circuit, especially without causing damage to elements such as transistors.

The present invention relates to a wired-AND capable driver circuit that is capable of configuring wired-AND logic.

[Conventional technology]

Figure 3 is a circuit diagram of a conventional example, Figure (5) shows a basic resistance bias type Bi-CMOS logic circuit, and Figure (B) shows an improved resistance bias type Bi-CMOS logic circuit. CMO
It is a diagram showing an S logic circuit.

In the figure * Qll Q2 is a P-channel MOS transistor t Q4p Qs is an N-channel MOS transistor t Q31 Qe is a bipolar transistor, IN is an input terminal, OUT is an output terminal, ■ c1 (H) is a power supply (high level), VC2 ( L) is the power supply (low level).

R indicates resistance.

The basic i-CMOS logic circuit shown in the previous page is as follows.

This is a basic circuit of a resistance bias type B1-CMOS doubly connected circuit.

MOS) transistor Q2. Q5 operates as a bias for bipolar transistors Qa and Qs.

As for the operation of this circuit, when a high level signal rHJ is input to the input terminal IN, the MOS transistor Q2 is turned off and the MOS transistor Qs is turned on.

Bipolar transistor Q3 is turned off, bipolar transistor Q6 is turned on, and when a low level signal rLJ is input to the input terminal IN, transistors Q2. Q3 is on, transistor Q5. Qe is turned off.

Therefore, when the input terminal IN is rHJ, the output terminal OU
T is rLJ, and when IN is rLJ, OUT is rHJ.

However, the above basic circuit has a drawback that the output OUT is in a high impedance state in a steady state, and when used as a driver circuit.

Noise: There are two problems.

For example, when rLJ is applied to IN and transistor Q2 is turned on, even if transistor Q3 is turned on in a transient state, the pace-to-emitter voltage VBI of transistor Q3 is sufficient in a steady state. Transistor Q3
is turned off, and the output becomes high impedance.

An improved Bi-CMOS logic circuit as shown in Figure D is known as a circuit that solves these drawbacks.

This circuit has a P-channel M
Two transistors are connected in parallel, each consisting of an O8) transistor Q1 and an N-channel MOS transistor Q4.

In this circuit, the signal applied to the input terminal IN is:

The logic is inverted and the current is amplified and transmitted to the output terminal OUT.

That is, when the input is logic rHJ, the transistor Ql,
Q2 is off, transistor Q4. Q5 is turned on.

Also, at the same time (=, transistor Q3 turns off t Qs turns on, and the output is logic "L"; two. On the other hand, when the input is logic rLJ, the above on and off are reversed, and the output is logic rHJ becomes.

Here, transistors Q2 and Qs are as described above.

Operates as a bias for transistors Q3 and Qs.

Transistors Qt and Q4 work to maintain low impedance in the steady state of the output.

That is, in a steady state, the transistor Q1 has a lower impedance than the series circuit of the transistor Q2 and the resistor R, and the transistor Q4 has a lower impedance.

It functions to have a lower impedance than a series circuit of transistor Q5 and resistor R.

Note that although the figure shows a case where each transistor Q1 to Q6 is one, it is common to connect multiple transistors in parallel in order to match the characteristic impedance of the transmission line connected to the output. 0 In this way, the logic level of the output is determined by the transistor Q
1~Q3. Or, it is guaranteed by turning on Q4 to Q6.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

(1) It was impossible to construct a wired AND logic by using multiple driver circuits using resistance bias type logic circuits as shown in Figure 3 (5) and connecting their respective output terminals. .

In other words, the terminal outputting logic rHJ and the terminal outputting logic rLJ
When connected to a terminal that outputs.

Wired AND cannot be used because not only the logic becomes unstable, but also an excessive current flows from the "H" output to the rLJ output, which may destroy elements such as transistors.

(2) It is possible to use a two-way normal AND circuit instead of a wired AND circuit, but in this case, the number of stages of logic gates increases and processing speed cannot be increased.

The present invention eliminates such conventional drawbacks and provides a driver circuit using a resistance bias type Bi-CMOS logic circuit.
The purpose is to make it possible to configure wired AND logic without causing element destruction.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention, and in FIG. 2, the same reference numerals as in FIG. 3 indicate the same parts. 1 is a basic i-CMOS logic circuit of resistance bias type, 2 is a switch circuit, 3 is a delay circuit, and SL and Sλ are switches.

The present invention (!, P-channel MOS) transistor Q2.
A basic i-CMOS logic circuit of resistance bias type consisting of N-channel MOS) transistor Qap bipolar transistor Qa* Q6# resistor R; N-channel MO8 whose input is connected)
Ransistor Q4.

Connect it in parallel with the above transistor Q5 as shown in the figure.

Furthermore, in the preceding stage of the P-channel MO8) transistor Q2, there is a delay circuit 3 between the input terminal IN and the logic level signal of the input terminal IN, which is controlled by the output of this delay circuit, and switches sl and 82. A switch circuit 2 having the following configuration is provided.

When a logic level signal "H" (high level signal) is applied to the input terminal IN, transistors Q4 to Q6 are turned on, and a logic level signal "L" (low level signal) is outputted to the output terminal OUT.

At this time, the input rHJ is delayed by the delay circuit 3 and input to the switch circuit 2. At this time, the switch circuit 2 closes the switch S1 and opens the switch S2.

Therefore, the transistor Q2 has rH of the input terminal IN.
A J level signal is input, turning off this transistor,
Transistor Q3 is also turned off.

Next, when a signal at the rLJ level is applied to the input terminal IN, the transistors Q4 to Q6 are turned off.

At this time, since the switch S1 is closed and the switch S2 is open, the rLJ level signal at the input terminal IN is transmitted to the transistor Q.
2 and turns on transistor Q2.

Therefore, transistor Q3 is turned on.

An rHJ level signal is output to the output terminal OUT.

After a certain period of time has elapsed, the output of the delay circuit 3 switches the switch circuit 2.

As a result of this switching, the switch s1 is opened and the switch S2 is closed, so the transistor Q2 is disconnected from the input terminal IN, and the high-level power supply VCI (H
) is input.

In this way, an "H" level signal is input to transistor Q2 to forcibly turn off transistor Q2, and furthermore, transistor Q3 is also turned off.

Set the output to high impedance state.

[Effect]

Since the present invention is configured as described above, when logic rHJ is applied to the input terminal IN, transistors Q4 to Q6 are turned on, and the output becomes logic rLJ, and transistors Q2. Turn off Q3.

When logic rLJ is applied to the input terminal IN from this state,
First, transistors Q4 to Q6 are turned off, and transistors Q2. Q3 turns on and outputs logic rHJ+=,
do.

Thereafter, after a certain period of time has elapsed, the output of the delay circuit 3 changes, the switch S1 is opened, the switch S2 is closed, and the logic rHJ is input to the transistor Q2, forcing the transistor Q2 to turn off.

Therefore, transistor Q3 is also turned off, and the output becomes a high impedance state.

Therefore, when a wired AND logic is configured using the above circuit, the rHJ state of the output terminal OUT and the rL
Even if the J state is connected.

In the output rHJ state, it is in high impedance (transistor Q21 Qs is off), so no current flows,
It does not cause element destruction.

〔Example〕

The following two embodiments of the present invention will be explained based on the drawings. FIG. 2 is a circuit diagram of one embodiment of the present invention.

In the figure, the same symbols as in FIG. 1 indicate the same things. Also.

G1*G2 is a gate (inverter), G7 is an N-channel MO8) transistor tQs+ Q9 is a P-channel MO8) transistor.

In this embodiment, the delay circuit 3 is made up of Gl,
The switch circuit 2 is constituted by a gate (inverter) G2, a transmission gate consisting of transistors Q7 to Q8, and a transistor Q9.

First, when the input terminal IN is at the logic rHJ, the transistors Q4 to Q6 are turned on and the output terminal OUT is at the logic "L" (2).

In this case, after a certain period of time has elapsed, the output of gate Gl constituting delay circuit 3 becomes logic rLJ, and gate G2
The output of is rHJ.

Along with this, transistor Q? , Q8 is on and e
Q9 is turned off.

Next, from this state, when the input terminal IN becomes rLJ,
This input rLJ is input to transistor Q2 via transistor Q7°G8, turning on transistor Q2, and subsequently turning on transistor Q3.

At the same time, transistors Q4 to Q6 are turned off.

After that, after a certain period of time has passed, the output of gate Gl becomes rHJ, and the output of gate G2 becomes "L".
Transistors Qy and Qs are turned off and Qs is turned on.

Therefore, transistor Q2 has transistor Q9.
A high-level power supply Vc1 (H) is applied via.

When transistor Q2 is forcibly turned off (=.

Transistor Q3 is also turned off.

Therefore, transistors Q2 to Q6 are all turned off, and the output becomes a high impedance state.

Subsequently, when the input terminal IN becomes the logic rHJ, the transistors Q4 to Q6 are turned on in the same manner as above, and the output becomes the logic rLJ.

Such output rLJ to rHJ, "H" to rL
The transition of J is performed at high speed as in the conventional example.

After the output becomes logic rHJ, a high impedance state is guaranteed.

2. Although not shown in the figure, in order to guarantee the level of the output logic rHJ, a pull-up resistor (
Needless to say, a high resistance value is required).

〔Effect of the invention〕

As explained above, the present invention has the following effects.

(1) After the output is set to logic rHJ, it is dynamically controlled to be in a high impedance state, so even if a wired AND logic is configured, element destruction due to large currents will not occur.

In the end, even if the output of the logic rHJ and the output of the logic rLJ are connected, all transistors are turned off on the output side of the logic rHJ, resulting in a high impedance state. Therefore, from this high impedance state output, logic rL
No current flows to the J side, and no large current flows through the transistor on the logic rLJ side, so element destruction does not occur.

(2) Output goes from logic level rLJ to rHJ.

Transition from rHJ to rLJ occurs at high speed as in the conventional example.

(3) It is possible to construct wired and logic.

Compared to the case where an AND circuit is used, the number of gate stages is reduced and processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a wired unwired driver circuit according to the present invention. FIG. 2 is a circuit diagram of one embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional example. Possible 1: Basic i-CMOS logic circuit. 2...Switch circuit. 3...Delay circuit.

Claims (1)

[Claims] Basic resistance bias type Bi-CMOS logic circuit (1
) constitutes an N-channel MOS transistor (Q_5
), an N-channel MOS transistor (Q_4) connected to the input terminal (IN) is connected in parallel, and the P-channel MOS transistor of the Bi-CMOS logic circuit (1) is connected in parallel.
In the preceding stage of the S transistor (Q_2), there is a delay circuit (3) which is connected to the input terminal (IN) and delays the input signal for a certain period of time, and a delay circuit (3) which is switched by the output of the delay circuit (3),
A switch circuit (2) forcibly sends a high-level logic signal to the P-channel MOS transistor (Q_2) so that when the CMOS logic circuit (1) becomes a high-level logic output, it becomes a high-impedance output. ) A wired and possible driver circuit.