JPH03126256A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make coexistent a bipolar transistor having a high voltage resistance and CMOSFET having a high resistance to punch-through and latch-up and a high integrity by using a P-type buried layer having gallium as an impurity and a P-type well containing boron as the impurity. CONSTITUTION:In regard to a P-type semiconductor substrate 1, an N-type high-concentration buried layer 2 by antimony is formed in an area wherein NPN-Tr and PNP-Tr and P-channel MOSFET are to be formed, and a P-type buried layer 3 by boron of relatively high concentration is formed in the area wherein the PNP-Tr is to be formed. Besides, a P-type buried layer 4 by implantation of ions of gallium is formed simultaneously in an area of decomposition of the NPN-Tr and an area wherein the PNP-Tr and N-channel MOSFET are to be formed, and moreover an N-type low-concentration epitaxial layer 5 is formed all over the area. Then, a P-type well 6 is formed above the P-type buried layer 4 by implanting boron ions from above the epitaxial layer 5 and it is connected electrically with the gallium-dopes P-type buried layer 4 by thermomigration.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention relates to a semiconductor device, particularly a Bi-C semiconductor device in which a high-voltage bipolar transistor and a high-speed CMOSFET coexist.
The present invention relates to an MO3 semiconductor device and a manufacturing method thereof.

[Conventional technology]

Bj-CMO3 semiconductor devices, in which a high-voltage bipolar transistor suitable for analog circuits and a high-speed CMOSFET suitable for digital circuits coexist, have been widely put into practical use in recent years.

Next, a conventional configuration example of a Bi-CMO3 semiconductor device and its manufacturing method will be explained using the manufacturing process diagram shown in FIGS. Highly doped n-type antimony is applied to the substrate 101 in regions where a vertical NPN bipolar transistor (hereinafter abbreviated as NPN-Tr), a vertical PNP bipolar transistor (hereinafter abbreviated as PNP-Tr), and a P-channel O3FET are formed. A buried layer 102 is formed and NPN-Tr
isolation region and PNP-Tr and n-channel MOSFET
An n-type buried layer 103 made of boron is formed in the area where the
Form 04.

Next, as shown in FIG. 3 (El), an n-type well 105 is formed above the n-type buried layer 103 and electrically connected to the P-type buried layer 103 by thermal diffusion.

Subsequently, as shown in No. 311iJtc+, a field oxide film 106, an NPN-Tr n-type base region 107, a PNP-Tr n-type base region 108, a gate oxide film 109, and a gate electrode 110 are sequentially formed. Then, as shown in FIG. 3 (Di), an n-type heavily doped diffusion layer 111 is formed which will become the source/drain region of the p-channel MOSFET, the collector contact region and emitter region of the PNP-Tr, and the base contact region of the NPN-Tr. and the source/drain right page area of the n-channel MOSFET, NPN-
Collector contact region and emitter region of Tr, and P
An n-type heavily doped diffusion layer 112 is formed to serve as a base contact region of the NP-Tr. Next, the B i -CMO3 semiconductor device is completed through normal interlayer insulating film and wiring layer forming steps.

[Problem to be solved by the invention]

In a Bi-CMO3 semiconductor device having such a configuration,
Analog circuit using high-voltage NPN-Tr and high-speed C
When coexisting digital circuits using MOSFETs,
In order to increase the breakdown voltage of the NPN-Tr, it is necessary to increase the thickness of the lightly doped n-type epitaxial layer 104. Furthermore, in order to suppress the upward diffusion of the highly doped n-type buried layer 102, a high-temperature, long-time thermal process cannot be used to diffuse the n-type well 105.

This makes it difficult to electrically connect the P-type buried layer 103 and the N-type well 105. If the n-type buried layer 103 and the n-type well 105 are not electrically connected, or if the n-type buried layer 103 is not formed, high-temperature and long-term heat treatment cannot be performed, so an n-channel MOSFET is formed. The P-type head area becomes shallower, reducing resistance to punch-through and latch-up.

Furthermore, when the n-type well 105 is made highly doped in order to electrically connect the n-type buried layer 103 and the n-type well 105, the parasitic capacitance with the source/drain diffusion layer 112 increases.
The high speed performance of the CMO3 circuit is impaired.

On the other hand, if the P-type buried layer 103 is highly doped, the breakdown voltage between the n-type and n-type high-concentration buried layers 102 and 103 decreases, so the two buried layers 102 and 103 are formed close to each other. Therefore, a problem arises in that the degree of integration of the device is reduced.

The present invention was made in order to solve the above-mentioned problems in conventional B i -CMO3 semiconductor devices, and uses a high-voltage bipolar transistor and a highly integrated CMOSFE transistor with high resistance to bunch-through and latch-up.
An object of the present invention is to provide a semiconductor device in which T coexists and a method for manufacturing the same.

[Means and effects for solving the problem] In order to solve the above problems, the present invention provides a vertically doped structure formed in a region in which an n-type high concentration buried layer and an n-type low concentration epitaxial layer are sequentially provided on a semiconductor substrate. NPN bipolar transistor, an n-type buried layer doped with gallium formed on the semiconductor substrate, and an n-type low concentration epitaxial layer formed on the n-type buried layer by diffusion from the upper part thereof. A semiconductor device is constituted by an n-channel MOSFET formed in a region provided with an n-type well containing boron as an impurity and electrically connected to a buried layer.

In general, gallium has low solid solubility and diffusion in oxide films is extremely large, so it is not often used as an impurity in semiconductor devices, but when used as an impurity to form a buried layer, it is necessary to increase the concentration. (Also, since the buried layer does not come into direct contact with the oxide film, there is no particular problem when using gallium to form the buried layer. Also, gallium has a higher lit coefficient in silicon than boron.) Because of their large size, thick P-wall regions can be formed with relatively low concentration implants without the use of high temperature, long duration thermal processes.

Therefore, in the present invention, p containing gallium as an impurity
By using the type buried layer and the P-type well containing boron as an impurity, electrical connection between the two can be easily obtained without requiring a high-temperature and long-time thermal process. This enables high-integration CMOSFE with high resistance to punch-through and rough drop while maintaining the high breakdown voltage of bipolar transistors.
A semiconductor device in which T coexists is obtained.

〔Example〕

Next, an example will be described. 1 to 1) are manufacturing process diagrams for explaining one embodiment of a semiconductor device and a method for manufacturing the same according to the present invention. First, as shown in the first prisoner, NPN-Tr and PNP are
- In the region where the Tr and p-channel MOSFET are formed,
An n-type high concentration buried layer 2 of antimony is formed, and PNP
- P caused by relatively high concentration of boron in the region where Tr is formed
A mold embedding layer 3 is formed. In addition, a p-type buried layer 4 is simultaneously formed by gallium ion implantation in the M region of the NPN-Tr and the region where the PNP-Tr and n-channel MOS FET are to be formed, and an n-type low concentration layer 4 is formed over the entire region. Epitaxial layer 5 is formed. At this time, the NPN formed later
- The low concentration epitaxial layer 5 is formed sufficiently thick so that the withstand voltage with respect to the base slope of -Tr is high.

Next, as shown in FIG. 1(B), a p-type well 6 made of boron is formed on the top of the p-type buried layer 4 by ion implantation from the top of the epitaxial layer 5, and a p-type well 6 made of boron is formed by ion implantation from the top of the epitaxial layer 5, and a p-type well 6 made of boron is formed by thermal diffusion. It is electrically connected to the embedded layer 4.

Next, as shown in FIG. 1C, field oxide film 7. P-type base region of NPN-Tr8. P
NP-Tr n-type base region9. A gate oxide film 10 and a gate electrode 11 are sequentially formed. Next, as shown in FIG. 1(D), a p-type cavity concentration diffusion layer 12 is formed, which becomes the source/drain region of the p-channel MOSFET, the collector contact region and emitter region of the PNP-Tr, and the base contact region of the NPN-Tr. to form an n-channel MOS
FET source/drain region, NPN-Tr collector contact region and emitter region, and PNP-T
n-type high concentration diffusion layer 13 which becomes the base contact region of r
form. Then, the Bi-CMO3 semiconductor device is completed through normal interlayer insulating film and wiring layer forming steps.

Next, the impurity concentration distribution in the depth direction of each element formed according to this example will be explained using FIGS. In addition, in Figures 2 to (C), the solid lines represent p-type and n-type
The net impurity concentration, which is the difference between the impurity concentrations of the two types, is shown, and the broken line shows the p-type impurity concentration. In addition, the signs in each impurity concentration distribution curve are Bi-CM
It shows the impurity concentration in the portions indicated by the same reference numerals in the O5 semiconductor device.

The second prisoner shows the impurity concentration distribution in the depth direction of NPN-Tr. In the NPN-Tr, the lightly doped epitaxial layer 5 is thick and the upward diffusion of the n-type heavily doped buried layer 2 is relatively small, so when a voltage is applied to the base-collector junction, the depletion layer fully extended to the sides,
As a result, high voltage resistance can be obtained.

FIG. 2(B) shows the impurity concentration distribution in the depth direction of the n-channel MOSFET. n-channel MOSFET
Since the p-type buried layer 4 is made of gallium with a large diffusion coefficient, the peak concentration is low, and boron can be easily absorbed through the thick epitaxial layer 5 by a relatively low-temperature, short-time thermal diffusion process. It can be connected to the p-type well 6 by. In this case, since the peak concentration of the p-type well 6 and the p-type buried layer 4 can be made relatively low, the parasitic capacitance with the n-type source/drain diffusion layer 13 can be reduced, and the n It is possible to increase the breakdown voltage with the mold high concentration buried layer 2. Furthermore, since the p-wall region forming the n-channel MOSFET is deep and has a relatively flat concentration distribution, resistance to latch-up and bunch-through is improved.

Furthermore, since gallium diffuses extremely quickly in the oxide film, the P-type well 6 is formed using boron, and the gallium concentration on the surface of the p-type well 6 is, for example, lXl0I5/c+d.
It is necessary to set it sufficiently low as below.

FIG. 2 (FC) is a diagram showing the impurity concentration distribution in the depth direction of the PNP-Tr. In the PNP-Tr, the P wall region connecting the p-type well 6 and the p-type buried layer 4 is used as a collector, and is electrically separated from the P-type semiconductor substrate 1 by the n-type high concentration buried layer 2. . As mentioned earlier, the collector region consisting of the p-type well 6 and the p-type buried layer 4 has a relatively low concentration and a flat concentration distribution, so when a voltage is applied between the base and collector, depletion occurs. The layer spreads sufficiently over the collector region, resulting in high breakdown voltage.

Furthermore, as shown in the figure, when a P-type buried layer 3 is formed of boron at a relatively high concentration, since boron has a smaller diffusion coefficient than gallium which forms the P-type buried layer 4, the p-type semiconductor substrate 1 It does not diffuse much from near the boundary between the epitaxial layer 5 and the epitaxial layer 5, forming a relatively high concentration p-wall region deep in the collector. Therefore, the collector resistance can be reduced without greatly reducing the withstand voltage between the collector and base, and the PNP-T
The performance of r can be improved.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, since a P-type buried layer doped with gallium and a p-type well doped with boron are used, a high breakdown voltage bipolar transistor and a punch-through Accordingly, it is possible to easily provide a semiconductor device in which CMOSFETs with high integration and high resistance to latch-up coexist.

[Brief explanation of the drawing]

Figure 1~) is a manufacturing process diagram for explaining an embodiment of the semiconductor device and its manufacturing method according to the present invention, Figure 2~(C) is Figure 1~). Figures 3 to 3 (D), which show the impurity concentration distribution in the depth direction of each element in the semiconductor device obtained by the steps shown, are diagrams showing an example of the conventional manufacturing process of the semiconductor device. In the figure, 1 is a P-type semiconductor substrate, 2 is an n-type high concentration buried layer, 3.4 is a p-type buried layer, 5 is an n-type low concentration epitaxial layer, 6 is a p-type well, and 7 is a field oxide film. , 8 is P
9 is an n-type base region, 10 is a gate oxide film, 11 is a gate electrode, 12 is a p-type high concentration expansion v1. layer,
13 indicates an n-type high concentration diffusion layer. Depth □ Depth -m-

Claims (1)

[Claims] 1. A vertical NPN bipolar transistor formed in a region where an n-type high concentration buried layer and an n-type low concentration epitaxial layer are sequentially provided on a semiconductor substrate, and a gallium layer formed on the semiconductor substrate. Boron, which is diffused from the upper part of the p-type buried layer as an impurity and an n-type low concentration epitaxial layer provided on the p-type buried layer and is electrically connected to the p-type buried layer, is used as an impurity. 1. A semiconductor device comprising: a p-type well; and an n-channel MOSFET formed in a region provided with the p-type well. 2. The semiconductor device according to claim 1, further comprising a p-type buried layer formed on the semiconductor substrate and containing gallium and boron as impurities, and an n-type low concentration epitaxial layer provided on the p-type buried layer. A semiconductor device comprising a vertical PNP bipolar transistor formed in a region including a p-type well doped with boron, which is diffused from the top of the layer and electrically connected to the p-type buried layer. . 3. The concentration of gallium on the surface of the p-type well region where the n-channel MOSFET is formed is 1×10^1^5
/cm^3 or less
The semiconductor device described. 4. In the semiconductor device according to claim 2, a p-type buried layer doped with gallium in the region where the n-channel MOSFET is formed and a p-type buried layer in the region where the vertical PNP bipolar transistor is formed. A method of manufacturing a semiconductor device, wherein the p-type buried layer containing gallium as an impurity is formed by simultaneously implanting gallium into the semiconductor substrate.