JPH03126250A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPH03126250A JPH03126250A JP26553389A JP26553389A JPH03126250A JP H03126250 A JPH03126250 A JP H03126250A JP 26553389 A JP26553389 A JP 26553389A JP 26553389 A JP26553389 A JP 26553389A JP H03126250 A JPH03126250 A JP H03126250A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- resin
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229920005989 resin Polymers 0.000 title claims abstract description 14
- 239000011347 resin Substances 0.000 title claims abstract description 14
- 229910000859 α-Fe Inorganic materials 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000007789 sealing Methods 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract description 3
- 229920000647 polyepoxide Polymers 0.000 abstract description 3
- 239000000843 powder Substances 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特にパッケージ
封止用樹脂材料を改良した樹脂封止型半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a resin-sealed semiconductor device in which a resin material for package sealing is improved.
従来、この種の半導体装置におけるパブケージ封止用樹
脂材料は、エポキシ樹脂などが使われていた。Conventionally, epoxy resin or the like has been used as a resin material for sealing the pub cage in this type of semiconductor device.
上述した従来の樹脂封止型半導体装置では、パッケージ
封入用樹脂により、パッケージ内の半導体チップを保護
することをのみを目的としていて、半導体装置の電気的
特性については考えていない。このため、ＩＧＨｚ程度
の高周波では、ボンディングワイヤー間、リードフレー
ム間での電磁波による干渉のためノイズを発生する可能
性があり、半導体装置の電気的特性が低下するという欠
点がある。In the conventional resin-sealed semiconductor device described above, the purpose is only to protect the semiconductor chip within the package using the package-encapsulating resin, and no consideration is given to the electrical characteristics of the semiconductor device. Therefore, at a high frequency of about IGHz, noise may be generated due to interference due to electromagnetic waves between bonding wires and lead frames, resulting in a disadvantage that the electrical characteristics of the semiconductor device deteriorate.
本発明の樹脂封止型半導体装置は、リードフレーム上に
固着される半導体チップと、前記半導体チップ上に設け
られるボンディングパッド電極と、リードフレームの外
部リードを接続するホンディングワイヤーと、前記ボン
ディングパッド電極を除く前記半導体チップ表面を被覆
するシリコン窒化膜として形成したパッシベーション膜
により構成される半導体集積回路において、前記リード
フレームを固定し、粉末状のフェライト （Ｍｎｗｓｚ
ｎｌｌＬ、Ｆｅ２０４）を混合した樹脂により前記半導
体チップとボンディングワイヤーとリードフレームとを
パッケージ内に封止する構造を備えて成る。The resin-sealed semiconductor device of the present invention includes a semiconductor chip fixed on a lead frame, a bonding pad electrode provided on the semiconductor chip, a bonding wire connecting an external lead of the lead frame, and the bonding pad. In a semiconductor integrated circuit configured with a passivation film formed as a silicon nitride film that covers the surface of the semiconductor chip except for the electrodes, the lead frame is fixed and powdered ferrite (Mnwsz
The package has a structure in which the semiconductor chip, bonding wires, and lead frame are sealed in a package using a resin mixed with Fe204).
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の樹脂封止型半導体装置の一実施例の断
面図である。本実施例による半導体装置は、リードフレ
ームｌ上に固着される半導体チップ２と、半導体チップ
２上に設けられるボンディングパッド電極４と、リード
フレーム１の外部リードを接続するボンディングワイヤ
ー５と、ボンディングパッド電極４を除くシリコン窒化
膜として形成したパッシベーション膜３がら構成される
半導体回路を、エポキシ樹脂を利用するパッケージ封入
用樹脂７と、このパッケージ封入用樹脂７に混入したＭ
ｎ １５ Ｚ ｎ ｏ、ｓＦ ｅ ２０４のフェライト
粉末８とでパッケージ６内に封止した構造である。FIG. 1 is a sectional view of an embodiment of a resin-sealed semiconductor device of the present invention. The semiconductor device according to this embodiment includes a semiconductor chip 2 fixed on a lead frame l, a bonding pad electrode 4 provided on the semiconductor chip 2, a bonding wire 5 connecting external leads of the lead frame 1, and a bonding pad electrode 4 provided on the semiconductor chip 2. A semiconductor circuit composed of a passivation film 3 formed as a silicon nitride film except for electrodes 4 is mixed with a package encapsulation resin 7 using epoxy resin and an M mixed in this package encapsulation resin 7.
It has a structure in which it is sealed in a package 6 with ferrite powder 8 of n 15 Z no and sFe 204.
このようなフェライトを混入したパッケージ封入用樹脂
７で封止した場合、電磁波の侵入の潤さここにωは周波
数（Ｈｚ）、σは導電率（１／Ωｍ）。When sealed with the package encapsulating resin 7 containing such ferrite, the resistance to penetration of electromagnetic waves is: where ω is the frequency (Hz) and σ is the conductivity (1/Ωm).
μは導磁率（Ｈ／ ｍ ）で、この場合それぞれω＝２
πＸＩＯ’、 σ＝１．μ＝２０００Ｘ４π×１０−
Ｔである。μ is the magnetic permeability (H/m), in which case ω=2, respectively
πXIO', σ=1. μ=2000×4π×10−
It is T.
上述したσの値は約０．３６ ｍｍとなり、ボンディン
グワイヤー間およびリードフレーム間に電磁シールド効
果を付与するのに十分な短がさとなる。The above-mentioned value of σ is about 0.36 mm, which is short enough to provide an electromagnetic shielding effect between the bonding wires and between the lead frames.
以上、説明したように本発明は、封止用樹脂に粉末状の
フェライトを混合することにより半導体装置パッケージ
内のボンディングワイヤー間の電磁シールドを行ない、
高周波動作時のボンディングワイヤー及びリードフレー
ム間の電磁波の干渉を低減でき、これにより高周波動作
時の半導体装置の電気的特性を著しく向上することがで
きる。As explained above, the present invention performs electromagnetic shielding between bonding wires in a semiconductor device package by mixing powdered ferrite into a sealing resin,
It is possible to reduce interference of electromagnetic waves between the bonding wire and the lead frame during high frequency operation, thereby significantly improving the electrical characteristics of the semiconductor device during high frequency operation.
第１図は本発明の一実施例の断面図である。
１・・・・・・リードフレーム、２・・・・・・半導体
チップ、３・・・・・・パッシベーション膜、４・・・
・・・ボンディングパッド電極、５・・・・・・ボンデ
ィングワイヤー６・・・・・・パッケージ、７・・・・
・・封入用樹脂、８・・・・・・フェライト粉末。FIG. 1 is a sectional view of an embodiment of the present invention. 1...Lead frame, 2...Semiconductor chip, 3...Passivation film, 4...
...Bonding pad electrode, 5...Bonding wire 6...Package, 7...
... Encapsulation resin, 8... Ferrite powder.
Claims (1)
導体チップ上に設けられるボンディングパッド電極と、
リードフレームの外部リードを接続するボンディングワ
イヤーと、前記ボンディングパッド電極を除く前記半導
体チップ表面を被覆するシリコン窒化膜として形成した
パッシベーション膜により構成される半導体、集積回路
において、前記リードフレームを固定し、粉末状のフェ
ライト（Ｍｎ＿０＿．＿５Ｚｎ＿０＿．＿５Ｆｅ＿２Ｏ
＿４）を混合した樹脂により前記半導体チップとボンデ
ィングワイヤーとリードフレームとをパッケージ内に封
止したことを特徴とする樹脂封止型半導体装置。a semiconductor chip fixed on a lead frame; a bonding pad electrode provided on the semiconductor chip;
In a semiconductor or integrated circuit comprising a bonding wire connecting external leads of a lead frame and a passivation film formed as a silicon nitride film covering the surface of the semiconductor chip except for the bonding pad electrode, the lead frame is fixed; Powdered ferrite (Mn_0_._5Zn_0_._5Fe_2O
A resin-sealed semiconductor device, characterized in that the semiconductor chip, bonding wires, and lead frame are sealed in a package using a resin mixed with _4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26553389A JPH03126250A (en) | 1989-10-11 | 1989-10-11 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26553389A JPH03126250A (en) | 1989-10-11 | 1989-10-11 | Resin sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03126250A true JPH03126250A (en) | 1991-05-29 |
Family
ID=17418449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26553389A Pending JPH03126250A (en) | 1989-10-11 | 1989-10-11 | Resin sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03126250A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09106998A (en) * | 1995-06-05 | 1997-04-22 | He Holdings Inc Dba Hughes Electron | Method for manufacturing encapsulated chip-on-board electronic module |
| US9768154B2 (en) | 2015-09-25 | 2017-09-19 | Tdk Corporation | Semiconductor package and manufacturing method therefor |
-
1989
- 1989-10-11 JP JP26553389A patent/JPH03126250A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09106998A (en) * | 1995-06-05 | 1997-04-22 | He Holdings Inc Dba Hughes Electron | Method for manufacturing encapsulated chip-on-board electronic module |
| US9768154B2 (en) | 2015-09-25 | 2017-09-19 | Tdk Corporation | Semiconductor package and manufacturing method therefor |
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