JPH03125520A - Converter for catv - Google Patents

Abstract

PURPOSE:To attain a highly stable modulation frequency by using a 1st PLL circuit including a 1st local oscillator so as to select a specific channel among plural input frequencies, and selecting a 2nd PLL circuit which integrates also a 2nd local oscillator and covers the entire input and output circuits. CONSTITUTION:A lock detector circuit 22 providing a PLL lock detector(LD) output and including a relay circuit to activate a changeover switch 11 is connected to a phase comparator 16. The changeover switch 11 receiving the lock detector output of the circuit 12 is thrown from the position of a contact NC-C to the position of a contact NO-C. An amplifier 12 receives the output of a 2nd IF amplifier 6, that is, a TV output through the circuit changeover resulting in forming a 2nd PLL circuit comprising a 1st mixer 3, a 1st IF amplifier 4, a 2nd mixer 5 and a 2nd IF amplifier 6. Thus, a stable conversion frequency output is obtained and the converter traces a change in a receiving wave.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an up-town converter for CATV and CCTV.

[Prior Art] This type of converter selects a desired channel from frequency signals of many types of channels input to an antenna, and obtains a television output of a specific channel frequency. A conventional converter has a circuit configuration as shown in FIG. 3, and includes a first mixer that obtains a first intermediate frequency from an antenna input and a first local oscillator output, and
It is equipped with a second mixer that obtains the second intermediate frequency from the intermediate frequency and the second local oscillator output, and only the first local oscillator side is PLL.
(Face Locked Loop) circuit was used to stabilize the conversion frequency.

[Problems to be Solved by the Invention] However, this configuration has a factor that causes instability on the second local oscillator side, and the second local oscillator side is simply set to P1. ,, When L circuits are used, channel selection becomes difficult, as will be understood from the explanation below. Also,
On the broadcasting equipment side, if low-cost products are used for the equipment, the broadcasting frequency will become unstable and change. Conventional converters cannot adequately follow changes in broadcast frequency.

The present invention solves the above problems, and by incorporating the second local oscillator side into the PLL circuit without affecting channel selection, the conversion frequency is highly stabilized, and even if there is a change in the input frequency, the second local oscillator is incorporated into the PLL circuit. , and to provide a CATV converter that can track it.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a CATV converter that selects a desired frequency signal from among many types of antenna input frequency signals and converts it into a predetermined channel output. , a first P L includes a first local oscillator, a programmable counter into which desired channel data and the output of the first local oscillator are input, and a phase comparator that performs a phase comparison between the output of the counter and the output of the reference oscillator.
L circuit, the first local oscillator, a first mixer into which the first local oscillator output and the antenna input signal are input, a first intermediate frequency signal output by the first mixer, a second local oscillator output, etc. A second mixer inputted thereto, a programmable counter inputted with desired channel data and a second intermediate frequency signal output from the second mixer, and a phase comparator configured to compare the phase of the counter output with the reference oscillator output. a second PLL circuit, and switching means for switching the circuit so that either the first PLL circuit or the second PLL circuit becomes a closed circuit, After selecting the signal, the switching means closes the second PLL circuit instead of the first PLL circuit and changes the channel data to the programmable counter.

[Operation] According to the above configuration, first, the first P1. = 1. , select the desired channel using the circuit. This P L
After obtaining the lock detector output signal of the L circuit,
The switching means is changed to replace the first PLL circuit with a second PLL circuit including a second local oscillator and a second mixer.
An L circuit is formed. In this way, by making the second local oscillator side also PLI, a stable converted frequency output can be obtained, and changes in the received wave can also be tracked.

[Embodiment] FIG. 1 shows the configuration of an embodiment of the CATV converter of the present invention. In this embodiment, compared to the conventional configuration shown in FIG. 3, a circuit surrounded by a broken line is added.

To explain the overall configuration, from the antenna input 1, the input low pass filter (LPF) 2, the first mixer (DBM: tuple balanced mixer) 3, the first intermediate frequency (IP) amplifier (also a band pass filter) 4, the second mixer 5
, and a second intermediate frequency (IP) amplifier 6 to reach the TV output cuff.

The first mixer 3 is supplied with the output of a first local voltage controlled oscillator (VCO) 8 via a buffer 9, and the second mixer 5 is supplied with the output of a second local oscillator (VCO).
O3C) 10 outputs are given. 20th - Cal 0
By using the 8CIO1 second mixer 5, it is possible to improve the image ratio, ■F rejection, spurious interference, etc.

The output of the 10th Calvcos is inputted to the phase comparator (φD) 16 via the contact N(, -C, amplifier 12, LPF 13, grease scaler 14, and programmable counter 15 of the changeover switch 11, and the PLL reference frequency (Reference) The output of O8CI7 is inputted to the phase comparator 16 via the frequency divider 18.The output of this phase comparator 16 is then passed through the PLL- LPF 19.
As the tuning control voltage, the 10th Cal■
C08, and the first PI-recircuit is formed by the closed circuit. Note that the programmable counter 15 stores desired channel data (L: load, D:
Data (C: clock) is applied via a shift register 20 and a data latch 21.

On the other hand, the phase comparator 16 receives a PLi-lock detector (LD) output, and a lock detector circuit 2 including a relay circuit for operating the changeover switch 11.
2 are connected. Based on the lock detector output of the circuit 22, the changeover switch 11 switches the circuit from the contacts NC, -C to the connection of the contacts N0-C. By this circuit switching, the output of the second IP amplifier 6, that is, the TV output, is input to the amplifier 12. With that, the first mixer 3
, a second PLL circuit including a first IF amplifier 4, a second mixer 5, and a second IP amplifier 6 is formed.

The operation of the above circuit configuration will be explained below. Now, when a 445.25 MHz signal is given to antenna 1, it is sent to the T"V output terminal for 1 channel 91.25 MHz.
Considering the case where it is desired to convert to a frequency signal of z, the frequency division ratio of the programmable counter 15 is set to 1/N to 1/21. ．． 16
Set to 0. Note that by changing this, it is possible to select one wave from among a plurality of frequency signals input to the antenna, convert the frequency, and obtain a TV output. In order to achieve the above frequency division ratio, predetermined PLL data may be serially inputted to the channel data input terminal in synchronization with the data clock to provide a load input. As a result, the data is applied from shift 1 to register 20 to latch 21, and the frequency division ratio based on the data is held in programmable counter 15 until the next data is input. Now, if the frequency division ratio of the prescaler 14 is 1/8, PL
A frequency divider of 1/169,280 will be included in the L circuit.

On the other hand, PLL reference 08C17 is 3.2MHz
When the frequency divider 18 oscillates and the frequency division ratio of the frequency divider 18 is 11512, a reference frequency signal of 6.25KH2 is given to the phase comparator 16.

Now, assuming that the 10th Cal Vcos is free running, its frequency fx passes through the buffer 9 and the contact NCC of the changeover switch 11, and reaches the amplifier 12.
It passes through the LPF 13, the prescaler 14, and the programmable counter 15, resulting in a frequency of fx/169.280=fD, which is then given to the phase comparator 16, where the above 6
．． Compared to 25KHz. The phase comparator 16 has three output states, and as shown in FIGS. 2(a), (b), and (c), if fD is lower than 6.25 KHz,
It outputs a pulse in the + (plus) direction with a width corresponding to the phase difference, and when fD is -6.25KHz, there is no output and it becomes a high impedance (open state), and when fD is higher than 6.25KHz. If the frequency is the same, a pulse in the - (minus) direction with a width corresponding to the phase difference is output.

The above output is converted into a DC voltage by the PLL LPF 19 (active type active filter), and the 10th-cal vcos
applied to the voltage control terminal of In the VCO 8, when the voltage applied to the terminal increases, the bias voltage of a varactor diode (not shown) forming the VCO 8 increases, the capacitance decreases, and the resonance frequency with the coil increases through the coupling capacitor. I want to, ■C
As the DC voltage (tuning control voltage) applied to O8 increases, its oscillation frequency increases, and conversely, as the voltage decreases, the oscillation frequency decreases.

Therefore, the oscillation frequency fx of vcos is 1.058 where the output of the phase comparator 16 is as shown in FIG. 2(b).
Fixed at MHz. The output of the VCO 8 is given to the first mixer 3 through the buffer 9, and its output, that is, the first intermediate frequency is 1,0.
58-445.25=612.75 M I-I z, and the first. The signal passes through an IP amplifier 4 and is applied to a second mixer 5. The second mixer 5 has a frequency of 91.2 which is the difference from the frequency of 704 MHz of the 20th Cal O3C10.
5MHz is output and sent to the TV through the second IP amplifier 6.
Output to the output cuff.

When the phases match, the phase comparator 16 enters a high impedance floating output state as shown in FIG. 2<b>, and at the same time makes the lock detector (LD) output high (to I) level. Therefore, the transistor Q1 of the circuit 22 is turned on, the relay RY is activated, and the relay contact RYS of the changeover switch 11 is switched to the NC side. Further, a device (not shown) that sets channel data detects that the lock detector (LD) output becomes high (H) level, and changes the channel data. As a result, N of the programmable counter 15 becomes "' 18
Make it 25”.

As a result, 91.25MHz of the TV output cuff is connected to contact N〇-C of changeover switch 1], amplifier 12, and LPF.
13. After passing through the prescaler 14 and the programmable counter 15, the 1/N output of the counter 15 is 91.25MHz x (1/8) x (1/1825)6
．． 25 KHz, which is applied to the phase comparator 16. This matches the 6.25 KHz given to the phase comparator 16 by the PLL reference 08c17.

Thus, the first mixer 3, the first IF amplifier 4, the second mixer 5, the 20th-Cal 08 CIO 1 the second IP amplifier 6
A second PLL circuit is now formed, and the drift of the oscillation frequency of the 20th caloscto can also be controlled. Therefore, even if the antenna input 445.25MHz changes within the lock range, the T
A stable output of 91.25 MHz is always obtained from the V output cuff. In the figure, P is an AM modulated image signal, and S is an FM modulated audio signal.

In addition, when the relay contact of the changeover switch 11 is switched from NC to No, the lock detector (L
D) The output becomes low (L) level, but this instantaneous LD
In order to prevent the relay contact from returning to the NC side due to a change in the output, for example, a time constant is added to the relay circuit using a resistor R1 and a capacitor C1, so that the instantaneous L
When the D output changes, the transistor Q1 is not turned on or 0FFL. In the embodiment shown in FIG. 1, a relay is used to switch the PLL circuit to simplify the explanation, but it is more common to use a semiconductor switch.

Also, contact No.C becomes conductive and the TV output is 91.2.
When 5M1-Iz is input to the programmable counter 15 via the amplifier 12, LPF 13, and prescaler 14, if N of this counter 15 remains 21,160, the phase comparator 16 outputs an output, causing an inconvenience. Therefore, the output side of the phase comparator 16 and P
Inserting a switching circuit that momentarily opens the circuit on the LPF 19 side for L L, or when converting the relay concave 3 circuits to electronics, after contact NC-C is open, the programmable counter 15 is The contact No. C may be closed after waiting for lt 1 /N to switch. Although there is a question as to whether the oscillation frequency fx of 1,058 MHz of VCOS does not change when these are switched, in reality, when the phase comparator 16 is at high impedance, the output of the PLL LPF 19 changes slowly. Therefore, there is no problem.

Next, temperature change characteristics will be explained. The temperature change of the 10th Cal CO of the conventional converter is ±100KHz.
(TYP), that of the 20th Cal O8C is ±300
KHz (TYP), total ±400KHz (T
YP) was boat fishing.

On the other hand, in this embodiment, the total frequency is ±100KHz.
(TYP). This stability depends on the precision of the crystal of the 3.2 MHz oscillation frequency of the PLL reference 03C17. Regarding deviations in the antenna input frequency, when relay contact 4 No-C'h' becomes conductive and a second P I-L circuit is formed, tracking control becomes possible automatically.

Next, costs will be explained. The 20th Cal O8C has conventionally been a component that affects stability, and moreover, P L
It is not in the L circuit, and has a high frequency of 704M1→Z, and if it is not a low distortion oscillation circuit, it will deteriorate the quality of the video signal, and it is extremely expensive, but it can be used with surface acoustic wave (SAW) resonators. It used an element called

In contrast, in this embodiment, the temperature characteristics are automatically controlled as long as the distortion is small, so that an inexpensive LC oscillation circuit often used in tuner circuits can be used. therefore,
In this embodiment shown in FIG. 1, the configuration of the part surrounded by the broken line is added, but this additional part is the 20th-cal O8 as described above.
Since a cheap material can be used as C, this is sufficiently offset.

As described above, in the embodiment of the present invention, it is necessary to switch the PLL circuit and provide different channel data before and after switching. Now, if the relay contacts N0-C remain conductive without switching the PI3LL circuit, it would be impossible to select a desired channel. The reason for this will be explained below. Now, when the first VCO 8 is free running and various types of broadcast waves are coming to the antenna 1, the first mixer 3 sends various frequencies mixed with the VCO 8 to the first IF amplifier 4. If all the frequencies are outside the band of the first IF amplifier 4, there will be no signal going to the second mixer 5. If by chance there is a signal close to 612.75 MHz, the PLL circuit will lock onto it as long as it is within the capture range, even if it is not the desired channel. Further, if the first IF amplifier 4 is of a wide band type, various signals will reach the grease guar 14, and the programmable counter 15 will not know which signal to divide, and furthermore, the image ratio,
Various performance deteriorations such as spurious interference and IF rejection occur.

Hereinafter, in order to better understand that there is a problem if the 20th Cu 08C10 and the 2nd mixer 65 are simply placed in the PLL loop, it will be explained with reference to the drawings.

FIG. 4 is a simplified block diagram of the conventional converter shown in FIG. 3, and its operation will be explained first.

Now, the oscillation frequency of the reference oscillator (Re f, 08C) is 4MHz, and the frequency division ratio is 1. /400, the reference frequency for phase comparison is 10 KHz. here,
By variously changing the frequency division ratio 1/N of the programmable counter, the frequency of the antenna input can be converted and the output can be obtained as a TV output.

First, when setting N=60,000, if the VCO frequency is fx=700MHz, then fx/N:
>10 KHz, the phase comparator φD outputs a pulse in the negative direction. This is the PLL LPF, which converts it into direct current, so that the CO control voltage Vc becomes lower than the current level, and the VCO changes to a lower oscillation frequency. For example, when the VCO drops to 600MHz, 7 f x/N = 600M/60,0OO = 10KHz, which matches the reference frequency of 10KHz, so the phase comparator φD no longer outputs pulses, and the LPFPF6
It becomes a constant direct current. Here, due to the response characteristics of the LPF for boat fishing, the controller 1~roll voltage VC becomes too low,
The oscillation frequency of the VCO will be lower than 600 MHz.

Then, fx/N<10KHz, the 17N output becomes lower than the reference frequency l0KI-Iz, a positive pulse is output from the phase comparator φD, the DC output voltage VC from the LPF becomes higher than the current value, and vCO The oscillation frequency fx also becomes a little higher.

In this way, the LPFPF6 oscillates attenuated until the input phases of the phase comparator φD match, and finally fx=60
It stabilizes when it reaches 0MHz.

This is the state in which PLL loop A is locked.

Currently, there are three types of antenna inputs: ■500MHz,
■4. If OOM Hz and ■300MHz are present at the same time, the mixer output will be as follows.

8 ■600M-500M=100MHz ■600M-4. OOM=200MHz■600M-3
00M=300MHz The mixer output has a center frequency of 1. Since an OOMHz band pass filter (BPF) is connected, lQQM
Only Hz passes through. If you don't do it, antenna human power ■ 5
Only 00MHz is converted to 100MHz and output to TV output.

Similarly, if we set N=40,000, f x
= 400 MHz the P L I-loop is locked. So, 400M-300M=100MHz
So, the input is only 300 MHz or 100 MHz.
It passes through the BPF of M 1-I z.

However, in this case, the 500 MHz input
-400M=1. Since it is OOMHz, 100 M
Passes through the Hz BPF. This is called an image interference wave. In the above explanation, image interference appears in the calculations, but in reality, in design, the frequencies of the fx and the bandpass filters of the first and second IP amplifiers are made higher, so that the image waves are much higher than the receivable frequency. It is set to a high frequency. The receivable frequency is determined by the input LPF, and the image wave is discarded here.

Next, FIG. 5 is a simplified block diagram when the 20th-Cull oscillator and the second mixer are placed in the second PLL loop in the embodiment of the present invention described above.

In the figure, the 20th-cal oscillator and the second mixer are not shown.

In the circuit shown in FIG. 4 described above, the programmable counter 1
The /N input always came from the ■CO output, but in Figure 5, depending on the frequency of vCO, fx is undetermined until it locks, so there may be no input to 1/H. , 100MHz as there are broadcast waves and jamming waves.
It is also possible that two waves come within the BPF band of .

First, set N=10,000. The reference frequency is 10 KHz, the same as in the previous example. And by chance, VCOf
Assume that fifx=600MHz. Then, among the antenna power ■～■, only ■ is 100MHz BPF.
(because 600M0 500M=100MHz). The programmable counter 1/N output becomes 100M/10,0OO=10KHz, and the PLL loop B tracks and locks to the 500MHz of the input (2). However, the VCO is fx
= 500MHz, 500M [VCO]-40
0M [Since the antenna input is 100MHz, PLL loop B is 40MHz of antenna input
Lock to 0 M 1-I z. This means that it is uncertain which channel to lock to depending on the VCO at that time.

Also, if the VCO is fx=700MHz, ■700M-500M=200MHz ■700M-400M=300MHz ■700M-300M=400MHz, and both antenna inputs are 100MHz BPF.
programmable counter 1/
There is a problem that there is no input to N, the PLL loop B1 remains open and does not lock, and the VCO free runs.

Figure 6 is a combination of the above-mentioned Figures 4 and 5.
FIG. 1 is a schematic diagram corresponding to FIG. 1 of the embodiment of the present invention. In the figure, the operation when it is desired to select 500 MHz of the antenna inputs, convert the frequency, and output 100 MHz to the TV output is as follows.

(1) First, when loading the first channel data into programmable counter 1/H, N1=60.000
Before the switch SWI 86 is turned on,
Assume that N1=60.000.

(2) PLL route A turns on, fx=600Ml
-(becomes z.

(3) Lock detector (LD) output changes from L” to H’
° (however, H is locked and L is unlocked).

(4) When the LD output becomes 'H', turn switch SW2 to
FF and switch SWI between a and c are also turned OFF2.

(5) Input the second channel data and N2=1
0,000.

(6) After N2=10,000, switch SW2
Turn on the switch SWI, and turn on the switch SWI between b and 6.

<7) Note that the VCO is fx = 600MHz, the mixer output is: ■600M-500M=100MHz ■600M 400M=200MHz ■600M-3
There are three types: 00M=300MHz.

(8) Therefore, the output of a 100MHz BPF is:
500MHz of antenna was selected and 10
It is converted to 0MHz and output to TV output. At this time, PLL loop B is in a locked state.

(9) Even if the 500 MHz of antenna power (■) drifts by ±△f, in PLL loop B, the output pulse of the phase comparator φD is converted into DC by the LPF, and this causes a change in the Vc control voltage to vCo. Since fx of vCo changes, the lock state is maintained in loop B within the lock range, and 100 MI (z) is output to the TV output.

(10) If the antenna input is turned OFF for some reason, the lock is released and the LD output becomes L'', which automatically repeats (1) to (9) above. This can be performed using the CPU or control IC, etc. In the above, Nl, N2
The data was loaded into the programmable counter in two parts, but in reality, N1 and N2 were loaded all at once.
Inside the PLL IC, first, the N1 data is used to lock the loop A, and then the N2 data is used to lock the loop 1B.

Next, points to be noted in design will be explained.

(A) In (4) above, switch SW2 is turned OFF when loop A is turned OFF and the 1/N input of phase comparator φD is turned OFF. Here, fx=
This is because 600 MHz must be changed. In the case of a type in which no output is output from φD, this switch SW2 is unnecessary.

(B) The first loop A becomes OFF, and the second loop B becomes OFF.
If loop A is locked while the loop is turned on, the output of the phase comparator φD will be in a high impedance (open) state, and in that case, the fx of the VCO will change very slowly, but both loops AB and By designing so that the OFF state is short, the problem of fx change can be solved.

(C) After switching to loop B, the 20th-cal oscillator and second mixer, which are not in loop A, enter, so
A frequency deviation (deviation from the phase comparator φD large input of 10 KHz) occurs in the programmable counter 1/N input.

Therefore, when the loop 1B becomes a closed loop, the input of the phase comparator φD also shifts in frequency through 1/N. P.L.
The L loop B pulls in and locks in the direction of correcting the erroneous frequency. In this case, there is a limit to which it can be locked, and that limit frequency width is called the capture range.

Therefore, either the capture range is designed to be wide, or conversely, a second V near-cal oscillator is installed within the capture range.
It is necessary to design it so that the width of the second mixer can be accommodated.

(D) In (10) above, if the antenna input frequency shifts while P I-L is locked, either change the fx of the VCO to always output a constant frequency of 1゛■, or
Since there are upper and lower limits to the frequency variable width, control cannot be performed beyond these limits. This limit is called the lock-in range. The lock-in range is wider than the capture range.

[Effects of the Invention] As described above, according to the present invention, the first PLL circuit including the first local oscillator selects a specific channel from among a plurality of input frequencies, and then selects the second local oscillator. The PLL circuit is also switched to a second PLL circuit that includes the entire input and output circuit.

As a result, whereas in the past, expensive elements were used to stabilize the second local oscillator, there was a limit to the stability of Takayasu 6. However, by simply selecting the reference oscillator for the PLL, It is possible to achieve even higher stability, and also to perform tracking control for deviations in the input frequency, and to obtain a stable conversion frequency output without being affected by broadcast frequency changes on the broadcasting device side. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a CATV converter according to an embodiment of the present invention, FIGS. 2(a), (b), and (C) are diagrams explaining the operation of a phase comparator in the converter, and FIG. 3 is a conventional Block configuration diagram of the CATV converter, Part 4
5 and 6 are simplified block configuration diagrams for explaining the present invention in detail. 1... Antenna input, 3... First mixer, 4...
-1st IF amplifier, 5...2nd mixer, 6...2nd IP amplifier, 7...TV output, 8...1st local oscillator, 11...changeover switch, 15...Programmer bull counter, 16...phase comparator, 17...PL
L reference frequency oscillator, 1...LPL for PLL, 22
...Lockde 2 Fitector circuit.

Claims (1)

[Claims] (1) In a CATV converter that selects a desired frequency signal from among many types of antenna input frequency signals and converts it into a predetermined channel output, the first local oscillator, the desired channel data, and the first local oscillator a first PLL circuit comprising a programmable counter to which an output is input; and a phase comparator that performs a phase comparison between the counter output and a reference oscillator output; the first local oscillator; a first mixer to which the antenna input signal is input; a second mixer to which the first intermediate frequency signal output and the second local oscillator output from the first mixer are input; and desired channel data and the second mixer. a second PLL circuit comprising a programmable counter into which a second intermediate frequency signal output is input; a phase comparator that performs a phase comparison between the counter output and the reference oscillator output;
and a switching means for switching the circuit so that either the PLL circuit or the second PLL circuit becomes a closed circuit, and after selecting a desired frequency signal in the first PLL circuit, the switching means A converter for CATV, characterized in that the second PLL circuit is a closed circuit instead of the first PLL circuit, and the channel data to the programmable counter is changed.