JPH03125394A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce input/output terminals and to miniaturize a package by connecting a switching circuit to a specified terminal and using it as a common terminal for the input of an address signal and the output of a data signal. CONSTITUTION:In figure applied to a dynamic RAM, a clock generators 5a-5c generates signals with which respective circuit blocks are actuated in specified order based on address strobe signals, the inverse of RAS and the inverse of CAS and a read and write control signal, the inverse of WE. A row address buffer 6a and a column address buffer 6b form a complementary address signal based on an address signal from the outside and supply it to address decoders 12 and 13. In such constitution, the buffers 6a and 6b, a data-out buffer 3 and a data-in buffer 4 are connected to a common address/data input and output terminal 8 through a switching circuit 7 such as a multiplexer. Any one of the circuits is connected to the terminal 8 based on the signals from the generators 5a-5c by the circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory technology and technology that is effective for use in input/output methods for address signals and data signals, and in particular to a dynamic RAM with a large capacity of IM bits or more. Concerning effective techniques that can be used.

[Prior Art] In conventional semiconductor memories, dynamic RAM uses an address multiplex system, but in both cases, address signals and data signals are input and output using separate terminals, and they are input and output independently of each other inside the chip. (For example, see "IC Memory Data Book JC8-746V," published by Hitachi, Ltd., or "Electronic Materials," November 1984 issue, published by Kogyo Chosenkai.)

[Problems to be Solved by the Invention] As described above, in conventional semiconductor memories, the address signal input terminal and the data signal input/output terminal are completely separate. On the other hand, the storage capacity of semiconductor memories continues to increase, and as the memory capacity increases, the number of address signals increases, and the number of terminals for inputting them must increase.

Therefore, as the capacity of semiconductor memories increases, the external dimensions, that is, the dimensions of the package, increase, and there is a problem in that high-density mounting on printed circuit boards becomes increasingly difficult.

In order to prevent such an increase in the number of address input terminals, an address multiplex is used in which the address signal is divided into three parts: Inventions related to dynamic RAMs have also been proposed.

However, the method of inputting only the address system three times has the disadvantage that the memory access speed becomes slow.

The present invention has been made in view of the above-mentioned problems, and its purpose is to reduce the number of input/output terminals of semiconductor memory, prevent the increase in the size of the package due to the increase in capacity, and reduce the size of printed circuit boards, etc. The goal is to improve the packaging density of

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

A switching circuit is provided on the semiconductor memory chip to switch between an address input signal and a data input/output signal and transmit the signal from the terminal to the memory array section or from the memory array section to the terminal, so that the address input terminal and the data input/output terminal are shared. It is intended to do so.

[Function] The dimensions of a semiconductor memory package depend on the number of its external terminals, but according to the above-mentioned means, the total number of terminals is reduced by sharing address input terminals and data input/output terminals, so the package can be made smaller. It becomes possible to convert into

In addition, in semiconductor memory, address input signals and data input/output signals are not necessarily input/output at the same time; these are signals that appear in time series, so even if these signals are handled in a multiplex system, the address input signal The memory access speed will not be much slower than when only multiplexing is used.

[Embodiment] FIG. 1 shows a block diagram in which the present invention is applied to a dynamic RAM as an example. Although not particularly limited, each circuit block in the figure is formed on a single semiconductor chip such as single crystal silicon using a known semiconductor manufacturing technique.

In FIG. 1, ■ is a memory array section, and in this memory array section 1, a plurality of memory cells are arranged in a matrix, and selection signal lines (word lines and data lines) are arranged on each memory cell in a direction orthogonal to each other. In addition to the memory array 11 in a narrow sense, which includes a memory array 11, a row-system address decoder circuit 1 and a column-system address decoder circuit 1 each selecting one of the selection signal lines.
2, 13, a sense amplifier row 14 for amplifying signals on the data lines, a column switch row 15 for selectively transmitting the amplified data signals to the main amplifier 2, and the like. The read data signal supplied to the main amplifier 2 is output to the outside via the data in buffer 3. On the other hand, a write data signal supplied from the outside is converted into a signal suitable for internal use by the data-in buffer 4 and sent to the memory array unit 1 via the main amplifier 2.

In FIG. 1, 5a, 5b, and 5c operate each circuit block inside the memory in a predetermined order based on the address strobe signal nK2 and the read/write control signal W lower 1 supplied from the outside. A clock generator that generates timing control signals.

Furthermore, 6a and 6b are a row address buffer and a column address buffer that form complementary address signals based on address signals supplied from the outside and supply them to the address decoder.

In this embodiment, the address buffer 6a.

6b, data out buffer 3, and data in buffer 4 are connected to a common address/data input/output terminal 8 via a switching circuit 7 such as a multiplexer, and the switching circuit is connected to a common address/data input/output terminal 8 by a timing control signal from clock generators 5a to 5C. 7 switching is performed to connect any one circuit to the common terminal 8.

Note that when switching address signals and data signals in this way using the multiplex method, the number of address signals and the number of data signals do not match, and generally the number of data signals is smaller, so it is difficult to input data signals. When outputting, unused pins are generated at the common terminal 8. In that case, the signal states of unused pins may be ignored during data input, and the unused pins may be brought into a high impedance state during data output.

Next, the operation of the above memory will be explained.

FIG. 2 shows the timing when reading data, and FIG. 3 shows the timing when writing data.

During standby, the switching circuit 7 is configured to supply the common terminal 8 to the address buffers 6a and 6b, and when the address strobe signal RAS falls in this state, the signal is input to the common terminal 8a. The address signal is supplied to the row address buffer 6a and latched. Subsequently, when the address strobe signal falls to the low level, the address signal input to the common terminal 8 at that time is supplied to the column address buffer 6b and latched. Also, at this time, the level of the write enable signal WE is detected, recognizing that it is a data read cycle, and switching the switching circuit 7 to the data input/output side.Then, the data of the memory cell selected by the address signal latched in the address buffers 6a, 6b is transferred to the memory array. 1 and is read out from the common terminal 8 by the data out buffer 3 through the switching circuit 4.
Output to. When the output of the data signal is completed, the switching circuit 4 is switched to the address buffer side.

On the other hand, when writing data, as shown in FIG. 3, signals are first taken in in the order of row address and column address in the same way as when reading. Then, when the column address strobe signal CAS falls, the write enable signal W
It detects the level of π, recognizes that it is a write cycle, switches the switching circuit 7 to the data input/output side, and activates the data in buffer 4. Then, following the capture of the column address, the write data input to the common terminal 8 is supplied to the data in buffer 4, and when the write enable signal W rises to high level, the write data is sent to the memory array section l. Data is stored in the memory cell selected at that time.

According to the above embodiment, if the memory array section l has a storage capacity of 1M bits and the number of bits of data input/output in parallel is 8 bits, there will be 18 address signals, so the common terminals will be 9. It is sufficient to provide 14 terminals in total including other control terminals and power supply terminals.

Therefore, a dynamic RAM with a capacity of 1 Mbit (but 1 bit output) which is currently widely available on the market has a capacity of 18
Compared to the case with wooden terminals, the number of bottles can be reduced by four, thereby making it possible to reduce the size of the package itself by more than 20%.

In addition, since the address input terminal and data input/output terminal can be used in common, it is possible to output 8-bit data, which is not available in conventional dynamic RAM, even in a package that is smaller than conventional semiconductor chips and has fewer terminals. becomes. Therefore, by incorporating a parity circuit in the memory, it is possible to include parity pits in the memory array. In this case, the result of the parity check can be output using the bin with extra space.

This eliminates the need for an external parity circuit, which has been conventionally required in the implementation of memory systems, etc., and external parity circuits have advantages such as circuit simplification and hardware reduction. The same effect can be obtained by using EC instead of a parity circuit.
This can also be obtained when a C (error correction code) circuit is employed.

In the above embodiment, address buffers are provided for each row system and column system, but by providing a second switching circuit between the address buffer and the address decoder, the address buffer can also be shared. can.

Furthermore, switching between row and column addresses may be performed by using a common input signal to the row address buffer and column address buffer and changing the latch timing, instead of using a switching circuit.

As explained above, in the above embodiment, a switching circuit is provided on a semiconductor memory chip to switch between an address input signal and a data input/output signal and transmit the signal from the terminal to the memory array section or from the memory array section to the terminal. Since the terminals and data input/output terminals are shared, the total number of terminals is reduced, making it possible to downsize the package.

In addition, in semiconductor memory, address input signals and data input/output signals are not necessarily input/output at the same time; these are signals that appear in time series, so even if these signals are handled in a multiplex system, the address This has the effect that the memory access speed is not much slower than when only signals are handled in a multiplex manner.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the address signals are divided into row and column signals, but the address signals may be multiplexed only with the data signals, or the address signals may be multiplexed with the X-system,
It may be divided into three systems, Y system and Z system, and data signals may be input and output from these systems in a multiplex system.

The above explanation will mainly focus on the field of application of the invention made by the present inventor, Dynamic RAM.
Although the present invention has been described as being applied to a ROM, it is not limited thereto, and can be applied to ROM (read-only memory), static RAM, and other raw conductor memories in general.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, it is possible to reduce the number of input/output terminals of a semiconductor memory, prevent the package from increasing in size due to an increase in capacity, and improve the mounting density on a printed circuit board or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a dynamic RAM, FIG. 2 is a timing diagram when reading data in the memory of the above embodiment, and FIG. A timing diagram when writing is shown.

Claims (1)

[Claims] 1. A signal switching circuit is connected to a predetermined terminal, and the switching circuit is switched by an external control signal, and the terminal is connected to at least an address signal input and a data signal input. A semiconductor memory device characterized in that it is used as a common output terminal. 2. A claim characterized in that the address signal is divided into two, a row system and a column system, and the signals of these two systems and the data signal are selectively input and output by the switching circuit. 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 1 or 2, wherein the switching circuit is provided between the common terminal and each input/output buffer circuit of two or more signal systems.