JPH031237A - Assembling device for fuzzy processor and max circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Summary of the Invention A fuzzy processor with a simple configuration is disclosed in which the antecedent part of an implication (control law) is represented by fuzzy and the consequent part is represented by a singleton (non-fuzzy). A plurality of parallel connected switches are provided to connect the fuzzy signal of the antecedent part to the singleton signal of the consequent part, and the desired switches are selectively turned on.

Singleton signals are realized by weighting the selected switches.

BACKGROUND OF THE INVENTION This invention relates to a fuzzy processor and MAX circuit assembly apparatus.

The great human brain has the concept of stored programs,
He created a digital computer by combining pool algebra and stable binary hardware. This continuous operation has made it possible to develop deep logic and perform deep processing of data. Digital computers are highly reliable due to their stable operation, and digital computer systems are becoming increasingly large. As long as the program does not contain information on a human mental level, it is possible to program a digital computer with the intention of doing so, and in this respect it can even be called a general-purpose machine.

With the realization of digital computer systems, human life and society are undergoing major changes.

Another great human brain considered how humans think about fut and how they communicate with each other, and created the very important concept of ``fuzziness.'' In 1965, L. A. Zadah proposed the concept of fuzzy sets. Since then, many papers have been published on fuzzy theory, but there have been very few reports on its application, and the reality is that it has only been done with the help of binary digital computers.

In fuzzy 1F research, a person's knowledge is based on accumulated experience that should be summed up with linguistic information, like the know-how of an expert. That is emphasized. This linguistic information generally comprises ambiguity, ambiguity, uncertainty, incompleteness or indecision, and is characterized by a membership function. The size of membership is represented by a numerical value in the QCR range from 0.0 to 1.0 and varies within this range.

When linguistic information is handled by digital computers, membership magnitudes (values) are represented by binary codes. The values represented by this binary code are stored, transferred, and operated on in binary electronic circuitry over and over again according to the stored program. Therefore, there is a problem in that it takes a long time to process fuzzy information by digital systems. Additionally, binary coded values require an incredibly large number of storage and computing devices. Although digital computers are general-purpose machines as described above, they are not necessarily optimal for processing fuzzy information in real time. Here.

There is a need to explore other types of machines that can process fuzzy information efficiently and quickly.

SUMMARY OF THE INVENTION The present invention aims to provide a nodeware system suitable for processing fuzzy information, particularly a system called a fuzzy processor (which can be easily configured).

This invention also. fuzzy controller.

The goal is to realize the MAXM path in a very simple (one-step) construction, which is particularly useful in fuzzy inference arithmetic devices or fuzzy processing devices called fuzzy combinations, fuzzy combinations, and fuzzy blouses.

The fuzzy processor according to the present invention includes at least one membership function circuit that outputs a signal representing a membership function according to an input signal, and a plurality of switches connected in parallel to each other on the output side.
Furthermore, the present invention is characterized in that it includes a plurality of control law circuits provided for each control law, and a weighting circuit that applies weighting to each switch of the control law circuit.

As a result, a fuzzy processor with a simple configuration is realized in which the antecedent part of an implication (control law) is represented by fuzzy words, and the consequent part is represented by a singleton (non-fuzzy). A plurality of parallel connected switches are provided to connect the fuzzy signal of the antecedent part to the singleton signal of the consequent part, and any switch is selectively turned on. Singleton signals are realized by mounting selected switches.

A fuzzy processor according to the present invention includes at least one membership function circuit that outputs a signal representing a membership function according to an input signal, and a variable resistance circuit connected to the output side of the circuit for providing a weight, It is characterized by comprising a plurality of control law circuits provided for each control law, and an addition circuit that adds output signals of the control law circuits.

As a result, a simple fuzzy process or sosa is realized in which the antecedent part of an implication is represented by a fuzzy and the consequent part is represented by a singleton. Furthermore, the weight of the singleton can be arbitrarily adjusted using a variable resistor.

A MAXM path assembly device according to the present invention includes: a plurality of fuzzy inference circuits that perform predetermined fuzzy inference for each implication or control law; a MAX circuit that performs a MAX operation on output signals of the plurality of fuzzy inference circuits;
It is composed of a subsequent circuit that processes or outputs the calculation results. Each fuzzy inference circuit is provided on one first substrate, and the subsequent circuit is provided on a second substrate. MAX
The circuits are each provided on a first substrate, and the output of the fuzzy inference circuit is given to the base and the emitter or output terminal of the first substrate is a transistor, and the transistor is provided on the second substrate and connected to its input side terminal. By connecting the t[m source and the output terminal of the first board to the input terminal of the second board by connectors, a wired O of 11η is formed.
It is composed of R.

Therefore, MAX circuits of corresponding circuits on a plurality of first substrates can be realized simply by connecting the first substrate to the second substrate, and the MAX calculation result can be sent to the subsequent circuit on the second substrate side. Furthermore, attachment and detachment of any first substrate does not have any adverse effect on the MAX circuit.

Description of Examples (1) Concepts of Fuzzy Reasoning and Fuzzy Computers and Fuzzy Controllers The simplest human rule of thumb is ``If X is A, then y is B''(It' x is A, then
y is B). here.

"If X is A" is the antecedent part.
).

"y is B" is called a consequent. A and B are ``tall'' and ``older.''

Ambiguous linguistic information such as "small positive value" can be characterized by membership functions as described above. In other words, A and B are fuzzy sets (in the explanation of the specific circuit described later, A
, B, etc. indicate voltage signals representing membership functions)
.

The above proposition is simple +, B X-A-44/Tomi B It is expressed as

Humans often make inferences that include fuzzy expressions in the antecedent and consequent parts. This type of reasoning cannot be performed on four legs using exclusive pool logic.

Consider the following form of reasoning.

Implication:
x -A-4y -B Premise: x-A' Conclusion: y -B
'This form of reasoning, i.e. inferring a conclusion from a given blemish when an implication exists, is called '-membranized Modus Bonens (gener
alized modus ponens) J.

There may be multiple implication rules, such as:

Implication 1: x-A →y-B else or an Implication 2: x-A −+y-B else or an
(1 implication r: x −A −y −B.

Blemish: x=A' Conclusion: y-B# Many implications are else (otherwise) or a
They are connected by nd (and).

[fuzzy relation from A to B
ionrrom A to B) J, and this is expressed as RAB (hereinafter, +11- is abbreviated as R).

In general, A −(a, a2.−, a,, ..., a
1ll11 B-fb, b, ..., b, ..., b
When 11 J n,
There is a fuzzy relation R from A to B. Considering A and B as membership functions, the above equation corresponds to the case where the membership functions are sampled and described as vectors.

When a blemise (x-A') is given for one implication dispute rule (y=8), the inference synthesis rule (COn+pOSIttOnalr) is used when inferring a conclusion (y-B') from these.
ule orinl'erence) J is. It is expressed as follows using the fuzzy relation R.

B' - A' *R - [a', a', ..., a, , ..., a'
]12 m rlj-al■bj is opened.

The operation ■ expressing the fuzzy relationship will be explained later.
,b',...Ura. ,...,b']■ ・2
J nb, - ■ (``1
j■a, ) michi■I(a ■b
．． )■a. + (2) I J
Various operations have been proposed to express the I fuzzy relation. For details, see Masaharu Mizumoto and I.
Ia n s-HaJrgcn Zlmmer III
ann. Compar1son or Fuzz
yReasoning Methods, Fuz
zy 5ets and Systems Vol.
, 8. No. 3.1) I), 253-283. (1
982).

Typical fuzzy relationships that have already been proposed include the following.

rlj-ajAbj MIN operation rule r
,' −(a jAb J ) v(l a i)
M^X rule J to r -1 (17a tΔbj) Arithmetic rule j The above old N arithmetic rule is the most well-known.

Since its effectiveness has been proven in industrial applications, the old N arithmetic rule is adopted in the specific circuit example described below. However, many other performances! Needless to say, Rule 5 is also applicable.

Various operations have also been proposed for the operation of * (ie, the operations of ■ and ■) in the above equation. For example, the old N/MAX operation, one algebraic product/M^X operation, etc. are used. In the specific circuit example described below.

The most commonly used MIN/MAX operation is used as the * operation. In other words, +4 A as the operation of ■
Replace the X operation with ■ and adopt the old N operation.

Therefore, the conclusion is based on the rules of inferential synthesis.

is expressed as 9th order using the old N/MAX operation as the * operation and the old NS calculation rule as the fuzzy relationship.

b J ′ −v l (a Δb,)Aa′
l (3-1) 1 [J I −+b, △ (a Aa, ') 1 1 J ] I Ib, △ [V (a Aa) l (3-2
) J II From the above equation, it will be understood that the fuzzy inference engine or fuzzy inference synthesis circuit is mainly constructed using the old N circuit and +, I A X circuit.

Before explaining the configuration of the fuzzy computer and fuzzy controller, we will briefly explain the membership function.

In boat fishing, the membership function is often expressed as a single curve, as shown in Figure 1 (^). However, whether or not it should be expressed as an 8-curve is not essential for the membership function. A more important feature of the membership function is that it takes continuous values from 0 to 1.

On the other hand, from the point of view of circuit design, it is easier to represent the membership function as a straight broken line, as shown by MF and MF2 in Figure 1 (I3), and it is easier to handle with a small number of parameters. The membership function can be characterized as follows, and the design is also simplified. Moreover, even if the membership function is represented by a broken line, the above characteristics will not be lost.

Basically, a triangular membership function MF shown by a solid line in FIG. 1(B) and a trapezoidal membership function MF2 shown by a chain line can be considered. The triangular membership function MF is the function μ(X)
- Value x1 of variable X at peak value P (not necessarily peak value -1). (this is called a label) and a gradient. Trapezoidal membership function MF
2 is basically.

It is characterized by a variable xt representing the center of its upper base (also called a label) and a slope.

Note that the variable X of the membership function μ(X) and the variable y of the function l1(y) that will appear later are x in the inference format described above.
, although the same symbol is used as y.

There is no particular relationship between them. This specification follows the convention of using such symbols.

As shown in Figure 1 (C), when the variable (X) is small, the function μ(X) takes a value of 1, and at a certain variable XL, the function μ(X) decreases at a constant slope and finally reaches O. The function MF3 (this is called the Z function).

and a function M F 4 (
This is called the S function). In addition, various forms of membership functions are possible.

The membership functions described above may be implemented in various forms. One of them is to express it by electrical signals (voltages or currents, but only voltage signals will be considered here) distributed on multiple (for example, 25) signal lines 1, as shown in Figure 2. be. The variables of the membership function μ(X) take discrete values, and these variables are assigned to each signal line. The signal lines are numbered (1-25 in FIG. 2) corresponding to the assigned variables. The plurality of signal lines constitute a type of bus.

The label XL is represented by the number of the signal line on which the peak voltage appears.

Another method is to express the variable X of the membership function μ(X) on the time axis. That is, the variable becomes time t (for convenience of explanation, this time t is distinguished from the overall time 17UT). Such a membership function μ(X
) is required to generate a sweep signal. The sweep signal may have a certain waveform (for example, a sawtooth wave, a triangular wave, a sine wave, a full-wave rectified sine wave, etc.), but here we will use a sawtooth waveform as shown in Figure 3. will be explained using an example.

In Fig. 3, the sawtooth wave sweep No. 1J SW changes linearly from -E to +E with a constant period τ, and then returns to -E at 1 (1■) for a short time (retrace period). The point in time at which the sweep signal SW crosses zero corresponds to, for example, x-0 of the membership function μ(X).The label X indicates the sweep signal S at the point in time corresponding to this value Xt.
It is expressed as the voltage Vb of W.

Figure 4 shows a parallel type fuzzy computer that performs calculations using membership functions distributed on the bus line shown in Figure 2, and is applied when one implication exists. It shows the concept of The fuzzy computer has a membership function A distributed on the bus line shown in FIG.

Three membership function generation circuits that output A' and B, respectively 11.12.13. and these circuits 11,
12.13 output signal is given, and the above-mentioned modus
Ponence's fuzzy inference operation (specifically, for example, the first (
3-1) and (3-2)), and the inference result B
It consists of a fuzzy inference engine that outputs .

The membership function generation circuits 11, 12 and 13 are provided with a label LA that defines the membership function to be output.
, LA', and LB are given, respectively. If it is necessary to obtain a deterministic result from a fuzzy computer, that is, a non-fissy output, a fuzzy inference engine 14 is used.
A differential gear I5 is connected to the rear stage.

An example of the configuration of the above-mentioned fuzzy inference engine I4 is shown in FIG. This is to perform the calculation expressed by equation (3-2). The voltages representing the members DA and A' distributed over m signal lines respectively are applied to the C-old N circuit (corresbondence old N circuit) 21, where a, Aa (i -1 ～m) old N
The calculation is performed. C-Old N circuit 2■ is the old N circuit with two-person car output.
This includes: The m output voltages of the C-old N circuit 21 are the E-MAX circuit (unsample M A X circuit) 22
Enter. The output of this E-MAX circuit 22 is va
Aa,' is represented. E-MAX circuit has m +-t I
+ is used to perform unsample MAX/ijr calculation of the input signal. The output of the E-MAX circuit 22 is given to the truncation circuit 23 as a truncation input a. On the other hand, voltages (b-, j-1 to n) representing a fuzzy membership function B distributed on n signal lines are input to the truncation circuit 23. The truncation circuit 23 is a circuit in which all inputs on one side of the C-old N circuit are made common. In the end, the truncation circuit 23 finally performs the calculation of equation (3-2), and the analog voltages distributed on the n output lines are
The conclusion B' of fuzzy inference as a set of ' can be obtained.

FIG. 5 shows the concept of a parallel type fuzzy computer that is effective when there are r implications. Three membership function generation circuits 11
13 and fuzzy inference engines 14 are provided. Subscripts 1 to r are attached to the labels LA and LB given to the membership function generation circuits for each implication. It is not necessary to provide a membership function generating circuit 12 for each of these sets, and one circuit 12 can be shared by all sets. You can do J. Concatenation of implications (else or also
) is realized by the MAX circuit 1B. That is, the outputs of all the fuzzy inference engines 14 are given to the MAX circuit 16, and the 1M^X circuit 16 obtains the final inference result B'. Of course, the concatenation may be performed using an operation other than MAX.

FIG. 7 is a sweep type fuzzy computer that uses the membership function expressed on the time axis shown in FIG. 3, and shows the concept of a fuzzy computer when one implication exists. . A sweep type fuzzy computer has three membership function circuits 31 and 32 that output membership functions A, A', and B expressed on a time axis, respectively.
33, a fuzzy inference synthesis circuit 34 which is given the output signals of these circuits 31, 32, and 33, performs the above-mentioned modus ponens fuzzy inference calculation, and outputs the inference result B'. and membership function circuit 31.8
2.33 is provided with a sweep signal SW as its input signal, and a timing circuit 35 is provided which provides a fuzzy inference/synthesis circuit 34 with a predetermined timing signal synchronized with this sweep signal.

Needless to say, not only the membership functions A, A', and B but also the inference result B' are expressed by voltages appearing on the time axis. Membership function circuit 31.32.
33 is a label (label m pressure) LA that defines the membership function to be output.

LA' and LB are given respectively. If it is necessary to obtain a definitive result, that is, a non-fuzzy output, from the fuzzy computer, a defassifier 36 is connected after the 1-synthesizing circuit 34. A constant voltage signal (constant at least during one cycle τ of the sweep signal) is obtained from the defassifier 36.

FIG. 8 shows the concept of a sweep type fuzzy computer that is effective when there are r implications. By comparing it with the basic form of the parallel type fuzzy computer shown in FIG. 5 and the sweep type fuzzy computer shown in FIG. It's easy to understand.

The fuzzy inference engine 14 described above to aid understanding
FIG. 9 schematically shows the inference according to equation (3-2) as an example of the fuzzy inference executed by the fuzzy inference synthesis circuit 34. This is multiple (r pieces)
It is assumed that there is an implication of Also shown is a triangular membership function. No. (3-
In equation 2), membership functions A, A' B, etc. are elements a of the fuzzy set.1. a l', b-, etc., but in Fig. 9, the horizontal axis is the variable X or y.
(or time t) as the function μ(X) or μ(y)(
or μ(t)).

Referring to the graph on the left side of the top row of FIG. 9, the old N operation result AlΔA' of the membership functions A[ and A' is indicated by diagonal lines. The maximum value a maxi of this old N operation result
(Truncating input a shown in FIG. 6) is obtained. A membership function 81 is shown in the center of the top row of FIG. 9, and the old N
The calculation results are indicated by diagonal lines Sl. This shaded part S
l is the inference result for one implication, which is output from one fuzzy inference engine 14 or fuzzy inference synthesis circuit 34.

Inferences are made in a similar manner for other implications. The inference results are expressed as 82°S.

``MAX operation of these inference results (Circuit 16 or Circuit 3
The result B' of 7) is shown on the right side of FIG. Many methods have been proposed for defuzzifying the inference results, one of which is the centroid method. According to this method, the center of gravity y is Yw−fμ(y) ・y dy/j”μ(y)dy
It is determined by That is, the purpose is to find the y drift (time t) that divides the area shown by hatching into left and right halves. The thus determined yl is output from the differential assifier 15 or 36 as a final value. Both the fuzzy inference engine and the fuzzy inference synthesis circuit in the fuzzy computer mentioned above perform inference where only one fuzzy proposition exists in the antecedent part of the implication. Sometimes it is necessary to make an inference that includes two fuzzy propositions in the antecedent part. This is called extended fuzzy inference. The antecedent part of an implication is [
and/or joined by J. Either “and” or “or” is selected.

Implications: If X is A and/or y is B, then 2 is C (Irx is A andlor y is B,
tben z Is C) Premises: X is A' or y is B'Conclusion; 2 is C'.

This is expressed symbolically as follows.

Implications: x-A andlor y-B-+z-C Premises:
x-A'andlory-B'Conclusion =
Extended fuzzy inference in a 2-C parallel φ type fuzzy computer is performed by an extended fuzzy inference engine. The concept of an extended inference engine is illustrated in the TSLO diagram. The inputs are membership functions A, B, C, A' and B', and a join selection C to select the "and/or" combination. The output is a membership function C' representing the conclusion. Membership functions A, A' are m
By the voltage distributed on the main signal line.

B and B' are respectively represented by voltages distributed on m' signal lines, and C is represented by voltages distributed on 0 signal lines.

FIG. 11 shows the configuration of this expanded inference engine, which is obtained by slightly modifying the basic inference engine configuration shown in FIG. Membership function A, l! :A', a C-old N operation is performed (C-old N circuit 21A), and an E-MAX calculation of m voltages representing the result is performed (E-MAX circuit 22A). Membership functions B and B' and Nitsuite also C
- Old N and E-MAX calculations are performed (C-old N circuit 21B, E-MAX circuit 22B). combination [and (a
nd) J is realized in this example by a DIN operation, and ``orJ'' is realized by a MAX operation, respectively.
A condord MIN-MAX circuit 24 is used.

The Condroldo old N-MAX circuit 24 has the old N calculation function and the M
It is possible to switch between the AX calculation function and the AX calculation function. 2
The calculation result of E-14AX is this Condroldo old N
- input to the MAX circuit 24; A combination selection input signal C for selecting "and" or "or" is applied as a control input to the condorold old N-MAX circuit 24. Membership function C is truncation circuit 23
The output a of the condorold old N-MAX circuit 24 is given as the truncation signal.

The truncation circuit 23 provides the voltage distribution of the fuzzy membership function representing the conclusion C'.

Next, the concept of a fuzzy controller will be explained.

In general, a controller receives a control amount obtained from a controlled object as input, and outputs a manipulated variable to the controlled object in order to perform desired control. Both the controlled amount and the manipulated amount are definite values. The fuzzy controller also receives a deterministic value as input, performs fuzzy inference, and then outputs a deterministic value. On the other hand, for example, if there is one fuzzy proposition in the antecedent part of an implication, in the above-mentioned fuzzy computer, the input is given by a fuzzy set or membership function A', and the fuzzy set or membership Function B' (definite value in some cases)
Output.

An implication (control law) of fuzzy inference in a fuzzy controller is compared with Fig. 9.
The case of (there is also one fuzzy proposition in the antecedent part) is graphically represented as shown in Figure 12. For an implication containing membership functions A and B,
The fuzzy inference result when the definite value XA is given is B', which is indicated by diagonal lines. By defuzzifying this inference result, a definite inference result B' can be obtained.

FIG. 13 shows a case where the antecedent part of the implication (control law) has two fuzzy propositions.

Old N or MAX of function 1 direct al, aB when definite values X and yB are given to two membership functions A and B in the antecedent part of implication, respectively.
(corresponding to the combination "and" or "0") is taken, and the result of the old N operation between this operation result aM and the membership function C becomes the fuzzy inference result (C' shown with diagonal lines).This inference result C' is By doing so, a definite inference result Cw can be obtained.

It is applied to fuzzy reasoning in which there are multiple implications (control laws) and each implication has two fuzzy propositions in its antecedent. An example of the configuration of a parallel type fuzzy controller using fuzzy membership functions distributed on a bus line is shown in FIG.

This will be explained in comparison with FIG. 5 and FIG. 11 showing its fuzzy inference engine.

The control law is expressed as follows.

Implications: Control law 1 x-A1. andlor y-Bl→
z-CL control law 2 x = A2 andlor y −
82→ z-C2 Control law r x-Ar andlor y-Br
→z-Cr Conclusion: z-C' The fuzzy inference engine 14 is replaced with the fuzzy inference synthesis circuit 14a. Since the two inputs are given as a definite fax, x, a circuit 1112 generates a membership function distributed over the bus line B.
etc. are no longer necessary, and instead, membership function circuit 3
1a and 31b are provided. These fuzzy inference synthesis circuit 14a, membership function circuits 31a, 31b, etc. are provided for each control law, and the labels LA and LB of the membership function circuits 31a, 31b are given subscripts corresponding to the number of the control law. ing. Control law 1 will be described below as a representative example.

Membership function circuits 31a and 31b have input variables X
A1
＾ru. The outputs of these circuits 31a, 31b are given to the old N or MAX circuit 24a. This old N or MAX
The circuit 24a corresponds to the old Condrold N-14AX circuit 24, and may be replaced with this circuit 24.

The output of circuit 24a becomes truncation input aMl. On the other hand, the output of the membership function generation circuit 13 that generates the membership function Ct as a voltage distribution appearing on the bus line (multiple signal lines) is given to the truncation circuit 23, and the old N operation with "Ml" is performed. 1
The result of this old N operation is 01'.

02 to C' are obtained in the same way for (r-1) control laws, and their M A X operation result "(M^X circuit 16) becomes the fuzzy inference result C'.

A defuzzified result C' is obtained.

FIG. 15 shows a configuration example of a sweep type fuzzy controller in which there are a plurality of implications (control laws) (the number of fuzzy propositions in the antecedent part of an implication is one). In contrast to FIG. 8, since the input is given as a definite value X^, the circuit 32 (MF C2 in the computer) that outputs the membership function A' is unnecessary. Membership function AI
X^ is given as an input to the circuit 31. This circuit 3
The output of 1 is given to the old N circuit 38 to which the output Bl of the membership function circuit 33 is input. A sweep signal is applied to the circuit 33 as its input. Old N circuit 3
The output Bl' of 8 is input to the MAX circuit 37. The above circuit is provided for a plurality of implicature circuits, and the outputs Bl' to Br' of all the old N circuits 38 are input to the MAX circuit 37. A final value Bw is determined from the output B' of the MAX circuit 37 by the defassifier 36 and output.

When there are two fuzzy propositions in the antecedent part of an implication (control law), as shown in Figure 16, 2
one membership function circuit 31a.

31b is provided, and definite inputs X and X are provided to these circuits 31a and 31b. The outputs of circuits 3La and B 51b are given to MIN or MAX circuit 24a. The MIN calculation result C' of the output of this circuit 24a and the membership function C which is the output of the membership function circuit 33c to which the sweep signal is supplied is the MIN circuit 38.
is output from. Since this inference result C' is a fuzzy function, its definitive value is determined by a defassifier.

A fuzzy controller that handles cases where there are three or more propositions in the antecedent part of an implication (in both parallel type and sweep type)
It goes without saying that the above idea can be extended and configured.

(2) A case where there is a plurality (one) of implications (control laws) having two fuzzy propositions in the fuzzy processor antecedent part will be considered with reference to FIG. Regarding the first implication, there are two membership functions At,
When definite value inputs X and yB are respectively given to Bl, a function value aAt' ant is obtained. Let the old N operation (or MAX operation) result of this function value be aMl.

For other implications, definite value inputs XA, Y are given in the same way, and the result aMl(i-2~r)
is obtained.

The membership function CI (i-1~r) in the consequent part of the implication is defined by its label position ZL, (i
A single function CS that extends to the peak at ""1 to ")
Let it be expressed as L (i-1 to r). This function is called a singleton and is a non-fuzzy quantity. The old N operation between the above old N operation result and singleton C (corresponds to the above truncation, but the old N operation is unnecessary as described later) is the thick arrow CS □ (i-1 ~ " ).

In the following explanation, to simplify the symbology, we will use “Li” as “Z”.
(i-1~r), C is V, (t-1~l
s z + r).

The final fuzzy inference result when the i1 number of implications is concatenated by MAX operation is shown in the form of a graph on the right side of FIG. 17. In order to defuzzify such inference results, the centroid method described above is used here. The center of gravity C (referred to as Z and Sv w ) is given by the following equation.

The numerator of equation (4) can be calculated by a weighted addition circuit as shown in FIG. 18, and the denominator can be calculated by a simple addition circuit as shown in FIG. 19.

In FIG. 18, the 9-weighted addition circuit includes operational amplifier 4
1, input resistors R1, .
Therefore, the output V of this weighted addition circuit
. 1 is given by the following equation.

■ −−Σ (R/R) ・V ・・・(
5) ot +-t [' t zl
Here, Rf/R, -Z, ... (6
), the formula (5) represents the numerator of the formula (4) (the sign is reversed).

From equation (6), the label of the singleton Csl representing the membership function Ct is the input resistance R1 and the feedback resistance R
It will be understood that this is achieved by 1.

As shown in FIG. 20, N L (Negative
e small: "small negative value") to P L (
Positive large: When considering a membership function or singleton expressed by seven labels up to ``positive large value'', these labels are defined by resistance R (i-1 to r) and resistance Rr. be done. In Figure 20, N in NL, NM, NS, etc. is Neg.
At lye, P of FS, PM, PL etc. is Po5it
ive, L is large, 1M is medium+,
S represents small, and ZR represents zero.

In FIG. 19, the simple addition circuit consists of an operational amplifier circuit 45, an input resistor R8 of equal value connected in parallel, and a feedback resistor R of the same value as the 0 input resistance (not necessarily the same value). and the voltage Vzl~v at one end of the input paper resistor
2r are given respectively.

Therefore, the output V of this simple adder circuit. 2 is the following formula % formula % This represents the denominator of formula (4) (the sign is reversed).

The fuzzy Brosse and Sossa diagrammatically shown in Figure 17 are:
As with the fuzzy controller, a definite input X,
It is characterized in that it is given XB, performs fuzzy inference based on a predetermined control law, and outputs a determined value (center of gravity Z). In addition, in fuzzy inference in this fuzzy processor, a fuzzy function is used in the antecedent part of the implication (control law), but the consequent part is also expressed by a non-fuzzy quantity (singleton). . Then, the old N calculation result aH□(i-1~
Since the value of r) represents the calculation result of the control law, there is no need for a truncation circuit as in the above-mentioned fuzzy computer or fuzzy controller.

The final output (center of gravity Z 2 ) is obtained by weighted addition of the calculation results of a plurality of control laws (the weight represents the label of the singleton of the consequent as described above). Of course, the above-mentioned simple addition is also necessary, but the
4) Division in the equation can be omitted as described later. The specific configuration of a fuzzy processor having several of these features will be described below, but before that, the old N circuit and MAX circuit, which are basic arithmetic circuits, will be explained.

n input configured using bipolar transistors -
An example of the old N circuit for output is shown in FIG. Assuming that the input voltage is Xl + X2 + . . . , x and the output voltage is 2, this circuit performs the calculation of 2-ΔXI.

That is, it generates an output voltage equal to the lowest input voltage.

This old N circuit is composed of a comparator (comparison circuit) and a convencator (compensation circuit). The comparator is composed of n PNP transistors Qll "12 "13'...Q1□ whose emitters are coupled to each other, and a current source C81 of a current I for driving these transistors.

Input side terminals X1-xn are applied to the bases of transistors Q1, -Qln, respectively. Transistor Q1, ~Q
The lowest input child (v, ) in
m+n
If given to its base, it becomes conductive, so
The other transistors are turned off. Therefore, the emitter has a voltage that is the sum of the emitter/base voltage of the transistor that is in a conductive state and VEB, that is, ■mi
n+VEB-↑xl+V, B appears (vEI3 is 0
．． (about 7v). If the two input voltages are equal and lower than the other input voltages, a current of Il/2 flows through the transistors to which these two input voltages are input, so
Same result. The same applies if three or more input terminals are equal and lower than the other input voltages.

The convencator compensates for the voltage vEB appearing as a MIN calculation error in the output of the comparator. This convencator is composed of an NPN transistor Q 1 and a current source C82 of current I 2 for current driving this transistor Q 1 . The emitter of transistor Q1 is connected to the output terminal of this old N circuit.

The base/emitter voltage vI3E of transistor Q2 is subtracted from the output voltage of the comparator, resulting in an output voltage of 2
will represent △X. Preferably, the currents of currents gcs1 and C8 are I-12.

FIG. 22 shows an example of a MAX circuit. This MAX
The circuit also consists of a comparator and a convencator. The comparator has input voltages x, x,'...
, X is base controlled by 1 2
It consists of NPN transistors Q, Q,...2n whose emitters are connected to each other, and a current source C81 for driving these transistors with current.The highest transistor among the transistors Q21-Q2□ Only the transistor to which the input voltage (this is V) is applied becomes conductive, and V is applied to the emitter.
A voltage of VBH appears. This -VI3B+
As a result of the error in nax being compensated for by the convencator consisting of the PNP transistor Q2 and the current source C82, an output max,n voltage 2 of V-X is obtained at the output terminal.

Since all the transistors in the comparators of the old N circuit and MAX circuit described above are mutually coupled at the emitter, this circuit is named an emitter-coupled fuzzy logic gate (CCFL gate).

The old N circuit described above, the MAX circuit, can be thought of as a cascade of two emitter followers driven by a current source. Therefore, they exhibit very high input impedance and very low output impedance. This fact shows that these circuits are resistant to external noise and signal crosstalk, and means that many circuits can be connected in subsequent stages.

Furthermore, since the old N circuit and MAX circuit described above are driven by a current source, saturation does not occur in each transistor. That is, the accumulation effect of minority carriers in the base region does not occur. Therefore, these circuits exhibit very fast calculation speeds. According to experiments, the response speed was 10 nsec or less.

Furthermore, the overall human/output static characteristics of the nine circuits are unaffected by opening one or some of the input terminals of the circuits described above.

Furthermore, in the above-described circuit, it is also possible to replace the PNP and NPN transistors with p-channel and n-channel MO3PEI', respectively.

The above applies not only to the old N circuit and MAX circuit described above, but also to all the circuits described below.

FIG. 23 shows the overall configuration of a fuzzy processor that performs the operations shown in FIG. 17. In order to perform fuzzy inference including r implications (control laws), r rule boards 50 are provided, and each rule board 50
Inferences are made about each implication.

In each rule board 50 (typically using the sign of the first rule board), there are two fixed value inputs X +
VB is given to the membership function circuits 31a and 31b, respectively, and their outputs a and a are the old N (
or At BI MAX ) circuit 24a, and the old N calculation result aMl is obtained. The above configuration is the same as the fuzzy controller shown in FIG.

As mentioned above, the fuzzy processor does not require a truncation circuit. The output of old N circuit 24a is provided to switch array 52.

Switch array 52 is for selecting the weighting described above. In this embodiment, the NL shown in FIG.
- 7 singleton labels of PL are adopted. Therefore, the switch array 52 includes seven switches SNL'=SPL, and the calculation result aMl is applied to one terminal of each of these switches. The switch SNL"' SPL is preferably one that can be turned on and off manually, such as a dip switch. The other terminal of the switch SNL"-" PL is connected to a C transistor Q31-Q3□ whose collector is connected to the power supply +V. and their emitters are connected to the output terminal.

In each rule board 50, a switch array 52
Any one of the seven switches is selectively turned on. For example, in the first Lulu board, the switch SNL is turned on and the weighting of NL is selected. In the second rule board, the switch SPM is turned on and the PM weighting is set. When a particular rule board is not in operation, all switches on that board can be turned off.

There is a board (not specifically labeled) containing a defassifier, and the board has seven inputs corresponding to labels NL to PL. Each of these input children is connected to each rule board 50 by a connector 53.
The corresponding output terminals of are connected. For example, label N
The output terminal (emitter of transistor Q3□) corresponding to the switch SN of all the rule boards 50 is connected to the input terminal of L. This results in a wired OR connection of all rule board outputs for each label.

7 input side children NL on the defassifier board
-PL is the corresponding input resistance R of the 1-weighted addition circuit 42
""' R7 and each input resistor R of the simple addition circuit 46, respectively. The weighted addition circuit 42
It is the same as that shown in Figure 8, and is set to r-7. Weighting of NL-PL is performed depending on the value of each input resistor R1 to R7. The simple adder circuit is the same as that shown in FIG.

7 input side children NL-PL of the defassifier board
are also connected to transistors Q4□-Q47, which serve as current sources. These transistors Q4□
~Q4□ constitutes a multi-current mirror with the transistor Q4o constituting the current source 49, and a constant value of current determined by the current source 49 flows through each of the transistors Q41 to Q47.

The transistor on the output side (Q31 = one of Q37) corresponding to the switch belonging to the same label in the switch array 52 of each rule φ board 50 and the corresponding transistor as a current source in the defassifier board (Q4 □ to Q4□) and the corresponding wired OR in the connector 53 between the output terminal of each rule board 50 and the input side child of the defassifier board constitute a MAX circuit, respectively. ing. For example, to clarify the relationship with FIG. 22, the transistor Q3□ of the first rule board is marked (Q21) in FIG. 23, and the r-th rule board is marked (Q2n). Transistor Q31 on the board, transistor Q41 marked with (C3■) on the defassifier board, and connector 5 that connects them.
The input/output terminals labeled NL in 3 constitute one MAX circuit.

In this way, the output terminals of the plurality of rule boards 5o and the input side of the defassifier board.

Since the MAX circuit is constructed by simply connecting the corresponding circuits using the connector 53 so that they are wired OR connected, the construction is simple.

Further, even if one or more rule boards 50 are removed, the input impedance at the defassifier board does not change because a constant current is caused to flow by the current sources (Q4° to Q4□).

The correct input side is added to the adder circuits 42 and 46. Also,
Since the current source only needs to be provided on the defassifier board and does not need to be provided on each rule board 5a, each rule board 50 can be simplified.

In the circuit of FIG. 23, the compensator shown in FIG. 22 is omitted.

The configuration of the MAX circuit described above is also applicable to the MAX circuits 16 and 37 shown in FIGS. 5, 8, 14, and 15.

In FIG. 23, each switch S of the switch pot array 52 is
Transistors Q31 to Q37 are connected to the output side of S.
Although these transistors and switches are connected in the same manner as shown in FIG. 41, the order in which these transistors and switches are connected may be reversed. In this case, only one transistor (reference numeral Q3) is required to be controlled by the output of the MIN circuit 24a, and the switch array 52 is connected to the emitter of this transistor Q31.

Further, as shown in FIG. 42, the current source 49 of the defassifier board and the transistors Q4□ to Q47 driven by this current source 49 are omitted, and each rule is
A current source 49A is provided on the board 50, and a transistor Q31
It may be connected to the emitter of

Furthermore, as shown in FIG.
It is preferable to use an al Throw (single pole double throw) switch. This 5PDT switch is, of course, constructed from a semiconductor switching element. One of the two input terminals of this 5PDT switch is grounded.

The switches in the switch array shown in FIGS. 41 and 42 can also be replaced with such 5PDT switches.

Output voltage V of simple adder circuit 46. 2 is a voltage adjustment circuit 48
It is input to the non-inverting input side of the operational amplifier 47 via the resistor R14. A resistor R is connected to the inverting input side of the operational amplifier 47.
11 via a constant reference voltage V. is given, and the output voltage is fed back via the feedback resistor R1°. The resistor R11 is set to be sufficiently larger (for example, about 10 to 100 times) than the feedback resistor R1°. The non-inverting input side terminal is grounded via a resistor R13. This resistor R13 is not necessarily required.

The voltage adjustment circuit 48 is the output V of the simple addition circuit 46. 2 is a voltage representing the fuzzy logic j1i1.0, and this is used to control the peak value (grade) of the membership function of the membership function circuits 31a and 31b of each rule board 50. This is fed back to the grade control circuit 51. In this example, the fuzzy logic values 0.0-1.0 correspond to voltages Ov-5v. Since this voltage is inverted by the operational amplifier 45 of the simple addition circuit 46, -5V is applied to the inverting input side of the voltage adjustment circuit 48 as the reference voltage V.

As a result, the output voltage V of the simple addition circuit 46. 2 is always -5V (corresponding to fuzzy logic straight 1), so the denominator of the above equation (4) becomes 1, and eventually.

Output voltage V of the weighted addition circuit 42. 1 represents the center of gravity of the fuzzy inference result. Weighted addition circuit 42
The output is inverted by an inverting amplifier circuit 43 and becomes a final non-fuzzy output as a positive voltage.

Next, the specific configuration of the rule board 50 will be explained with reference to FIG. 24, taking the first rule board as an example. Since this circuit includes membership function circuits 31a, 31b that generate membership functions expressed in voltage, their labels LA,.

L B t is given by a voltage (let these label voltages be v , v , respectively), and if the inputs X , VB are given by A LB A voltage signals (the input side child signals are V ,
). The membership function circuits y 31a and 31b output voltage signals representing the above-mentioned triangular membership function MF1.

Since the two membership function circuits 31a and 31b have exactly the same configuration, only one circuit 31a will be described.

The membership function circuit 31a includes two differential circuits 61.
62, the operation of these circuits will first be described with reference to FIGS. 25 and 26, taking the differential circuit 62 as an example.

In FIG. 25, a differential circuit 62 includes two transistors Q 1 and Q 2 , and a variable resistor R22 is connected between the emitters of these transistors. The base of one transistor Q61 (which becomes the input side child of the membership function circuit) has an input side V (when used in a sweep type fuzzy computer, a sweep signal SW is given to this input side side child). is applied, and a voltage VLA representing a label is applied to the base of the other transistor QB2. Current ■ is current source Q
54 to the emitters of both transistors Q 1 and Q 2 .

The current flowing through the transistor Q is 1, and the transistor et
If the current flowing through the 61 resistor Q is 16□, then Fig. 26 (
As shown in A), when v<vLA, a current of l62-I flows through the transistor QB2, and no current flows through the transistor Q (161-0).When the input voltage V exceeds the label VLA, the current of the transistor Q ■
6° decreases linearly, and the current I6□ flowing through the transistor Q increases linearly from 0. And V=
When V LA + R221, I -0
, I6. -1, and this state is maintained in areas with thicker LTV.

A current mirror CM2 is provided, which is driven by the current 6° flowing through the transistor Q. A resistor Rb is connected to the output side of the current mirror CM2, and the voltage appearing across this resistor R+ is defined as a voltage X. voltage x
is given by X ”” I 62 RL, so this voltage
＞ as shown by the solid line. The slope of the part where the voltage X changes linearly is given by -R(,/R. Therefore, this slope can be changed by changing the value of resistor R22.

In FIG. 24, another differential circuit 61 also has the same configuration as the differential circuit 62. The currents flowing through the transistor Q to which the input voltage ■ is applied and the transistor Q52 to which the label voltage vLA is applied are I and I, respectively.
Then, these currents change as shown in FIG. 26(C) with respect to the input side I52 pressure V.

The current mirror CPvl is driven by the current I5□ flowing through the transistor Q51. Since the current I51 flows through the resistor Rt connected to the output side of the current mirror CM1, the voltage x1 dropped by this resistor R is xl = l5
It becomes 1RL. A graph showing changes in voltage x1 with respect to input voltage V is a solid line in FIG. 26(D). The slope of the portion where the voltage X1 increases linearly is given by R/R. The resistor R21 is a resistor connected between the emitters of the two transistors Q51 and Q52 of the differential circuit 61L 21 , and by changing the value of this resistor R21, the above slope is changed.

The membership function circuit 31a includes a 2-input 111N circuit. For easier understanding, the components of this old N circuit are given the same reference numerals as the corresponding components Q1□, Q1° in the old N circuit of FIG. As the current source C81, a current source 64 of the old N circuit 24a, which will be described later, is used. No compensator is provided. As mentioned above, the compensator of the old N circuit subtracts the emitter/base voltage VEI3 of the transistor, and the compensator of the MAX circuit adds the emitter/base voltage ■IEB of the transistor. Therefore, when the old N circuit and the 1^X circuit are connected in cascade, the compensators of these circuits can be omitted. Since no compensator is provided in the MAX circuit including the transistors Q, Q, and the wired OR described above, the transistor Q
The compensator of the old N circuit including 11"1□ can be omitted.

The voltages x and x2 mentioned above are applied to the base of the transistor Q11''12 constituting the old N circuit.

The output voltage VA1 (aAl) appearing at the emitters of these transistors Q11'12 is the MI of voltages X1 and xl.
This is the result of N calculation, and its graph is shown as a solid line in FIG. 26(E). The output voltage VA1 changes triangularly with respect to the input voltage V, and the triangular membership function M
F represents. The input side corresponding to the peak value is the label voltage VLA.

Also, by resistor R or R22, for example,
), the slope is changed as shown by SL and SL2.

Although it is not particularly relevant in Fig. 24, just to be sure, if the input side V is the above-mentioned sweep signal, the output voltage ``At'' changes in a triangular waveform on the time axis.The input voltage V and label voltage VLA can be positive and negative.

Similarly, from the other membership function circuit 31b,
Under the set label voltage VLP, an output voltage Vn□ representing a membership function m (a o t ) corresponding to the input voltage ■ is obtained.

The old N circuit 24a includes a wired 0R63 and a current source 64. Then, the membership function circuit 31a described above
, 31b (7) Output voltage vA1. Given to vB1 Kawiert 0R63. The output of the wired 0R83 becomes a voltage VM1 representing the old N calculation result corresponding to a and l.

More specifically, the membership function circuit 31a
transistor Q11"12 of the membership function circuit 31b, and the wired transistor Q11"12 of the membership function circuit 31b.
A 4-input 1N circuit is formed by R63 and the current source 64.
It can be said that M has been completed.

As can be seen from the graph in FIG. 26(E), the peak value of the membership function in the membership function circuits 31a and 31b is determined by IR. If the resistance R0 is constant, the peak value changes by changing the current I.

The grade control circuit 51 is a circuit for changing the current I in accordance with the applied control voltage. The grade control circuit 51 includes a current mirror CM that functions as a current source, and this current mirror CM4 and the membership function circuit 3
The transistor Q53''54 as a current source of La and the transistor Q53Q54 as a current source of the membership function circuit 31b constitute a multi-current mirror. Therefore, the current equal to the current ■ flowing through the mirror CM4 is ?1! It will flow through these transistors Q53''54. Current mirror CM4 includes capacitor C1. This capacitor C1 is a phase compensation capacitor. As shown in FIG. 23, the output of the voltage adjustment circuit 48 is connected to the input V of the grade control circuit 5I. This capacitor C1 can prevent oscillation when feeding back to the circuit.

This current mirror CM4 drives another current mirror CM5. A resistor R is connected to the collector of one transistor of this current mirror CM5. When current I flows through this resistor R, a voltage of VR-IRo appears.

The grade control circuit 51 is provided with a differential circuit 65 and a current source C8 for driving the differential circuit 65. The differential path 65 includes two transistors Q71"72 whose emitters are connected by two resistors R23"24 of equal value, the junction of these two resistors being connected to the output of the current source C8. . A control voltage vc is applied to the base of one transistor Q71, and the above voltage VR is applied to the base of the other transistor Q7□. These voltages Vc and VI? When they are equal, the current mirror CM3 causes equal currents to flow through both transistors Q71 and Q72.

If the voltages V and VR are not equal, there will be a difference between the currents (1) and (2) flowing through both transistors. Current mirror CM3 includes both transistors Q71 and Q7
Since it works to flow a current equal to □, the current ■ and 1
A current with a difference of 2 flows into the base of a transistor Q73 connected to the collector side of the transistor Q72, and a current with a current amplification factor β times the difference flows into the emitter of the transistor Q73. The emitter of transistor Q73 is a Zener
Since it is connected to the current mirror CM4 via the diode ZD, the current flowing through the current mirror CM4 changes.

This current change appears as a change in the current I flowing through the resistor R, and the voltage VR is the control voltage V. It acts so that it is equal to . The Zener φ diode ZD is for applying an appropriate potential to the emitter of the transistor Q73, and may be replaced by providing a plurality of transistors.

The difference between the voltage V and V is Δ” R23-R24-
When R r , the current I and the lightning voltage R are given by the following equations.

1-(1/r) ・β・ΔV V -RI-(1/r)・β-R8Ro
e ΔV −(1/r)−β−R(V −VR)e
OC Therefore.

VR-[(1/ r,) ・β・Ro/(1+(1/
r) ・β・R11・v′.

e O Here, if (1/r)　・β・R〉〉1.

e 0 vR-v.

becomes. Therefore, the current I flowing through the resistor R is 1-V
/R CO .

As described above, the current (2) is controlled by the control pressure (V), and the membership function circuit 31a.

The peak voltage of 31b is determined by the simple addition circuit 4 shown in FIG.
6 output voltage V. 2 is the reference voltage V. (Fuzzy logic 1
(equivalent to).

Control voltage V. is given to all rule boards 50, so the above control is performed in all rule boards 50.

The combination of the membership function circuit 31a or 31b and the grade control circuit 51 is called a grade controllable membership function circuit (GC-NFC).

Although not particularly related to this embodiment, when controlling the peak value of the grade controllable membership function circuit for each rule board, the simple addition circuit 46
The output voltage V. 2 (Vo) should not be fed back to each rule board. and the output voltage ■ of the 1-weighted addition circuit 42; 1 as the output voltage V of the simple addition circuit 46 according to equation (4). Divide by 2 to get the final non-fuzzy output.

FIG. 44 shows another embodiment. As described above, the label (weight) of the singleton in the consequent part is realized by the resistance J (s -1 to r) of the weighted addition circuit 42 and the resistance Rr. In FIG. 23, these resistors R and Rr are both provided on the defassifier board. In the circuit of FIG. 44, the input resistance R of the 1-weighted addition circuit 42
1 and an input resistor R of the simple adder circuit 46 are provided on each rule board 50. Moreover, the resistor R0 is made a variable resistor so that the weight can be changed. switch S
Generally, either p or SN is turned on. If the rule board is not used, both switches S,
S is also turned off, or N resistor R1 is set to infinity.

In FIG. 44, the output voltage a of each rule board 50
H1 is connected to the resistor R via the buffer circuit 50a.

given to R. The resistor R0 is connected to the output terminal Tp of each rule board 50 via the switches lsP and pN, respectively.
, connected to T. Switch Sp is turned on when there is a positive singleton, and switch SN is turned on when there is a negative singleton.

Through these switches S and SN, the output terminal T p ,
The voltage appearing at T is V and ■N, respectively.
Pi
Let it be Ni. On the other hand, the resistor R is connected to the output terminal T of the rule board. The voltage appearing at this terminal is V
. Let it be i.

The output terminals Tp of all the rule boards 50 are connected to the input side children Tp of the defassifier board, the output terminals TN are connected to the input side children TN of the defassifier board, and the output terminals T of all the rule boards 50 are connected to the defassifier board. input side child T
are connected to each.

In the defassifier board, the 1-weighted addition circuit 42 includes operational amplifier circuits 41A and 41B connected to the input side terminals T and T, respectively, and these Lf
It is composed of an operational amplification circuit 41C that subtracts the output of the jL arithmetic amplification circuits 41A and 41B. Operational amplifier circuit 41A
Since the addition of Σ (R'/Ri)VPi is performed in the operational amplifier circuit 41B, and the addition of Σ (Rr/R,)VNI is performed in the operational amplifier circuit 41B, the operational amplifier circuit 41C outputs Σ (R/R,)V, - Σ (Rr/R1)+
A non-fuzzy output given by rI + VNl is obtained.

Needless to say, a signal representing Σ voi is obtained from the simple addition circuit 46.

In the embodiment shown in FIG. 44, no MAX circuit is provided. That is, this embodiment uses addition and subtraction rules rather than MIN/MAX calculation rules.

(3) Sweep type based on algebraic product rules, which is one of the application examples of fuzzy controllers based on algebraic product rules. We will explain the fuzzy controller of

As the simplest example, consider a case where one implication (control law) exists and the antecedent of that implication includes one fuzzy proposition. In the sweep type controller shown in Fig. 15, the old N operation is used as the fuzzy inference synthesis operation (
MIN circuit 38). The fuzzy controller described here uses algebraic product (so-called multiplication) as a fuzzy inference synthesis operation.

Referring to Figure 27(^), two GC-MFC31G
C:.

33 GCs are provided. This GC-NPC is the 24th
Membership function circuit (MFC1a) 31a shown in the figure
and a grade control circuit 51. A fixed value input V is given to one GC-MFC 31GC. Also, a label voltage vLA is set. This circuit 31
The grade control voltage of 0C (corresponding to V in Figure 24) is a constant voltage V. is given. Of course, this control voltage vc may be changed as necessary (for example, for weighting as described later).

When the control voltage V is constant, GC-MPC31G
Instead of C, a membership function circuit (in FIG. 24, a constant current source flows through the transistors Q 1 and Q 2 of the circuit 31a) may be used.

The other GC-MFC 33GC receives a sweep signal SW from the timing circuit 60 as its input (corresponding to ◯ in FIG. 24). In addition, as the grade control voltage (corresponding to vo), the output voltage V of the previous stage GC-MFC31GC
A (corresponding to output voltage VA1 in FIG. 24) is given. A unique label voltage VLll is also set for this circuit 330C.

As described above, the grade control voltage sets the grade (peak value) in GC-NFC.

GC- as grade control voltage of GC-MFC33GC
Since the output voltage VA of MPC31GC is given,
From the GC-liver C33GC, an output VB representing a membership function distributed on the 1-time axis multiplied by a value corresponding to the output voltage VA is obtained. That is, a one-algebraic product fuzzy inference operation is performed.

The output voltage VB of the GC-MI'C 33GC is then applied to the center of gravity determination circuit 36SW, and a voltage V representing the center of gravity is generated and becomes the definitive output of this fuzzy controller.

If there are multiple implications, the 15th
Similar to the fuzzy controller shown in the figure, prepare a number of circuits consisting of two GC-MFC81GC and 33GC, perform 1^X operation on their outputs, and use the MAX operation result as the defassifier ( It can be defuzzified using a centroid determination circuit).

If there are 291 fuzzy propositions in the antecedent part of one implication, the old N or M shown in Figure 16
The output of the AX circuit 24a may be given as a grade system [i pressure] of the GC-MPC 33GC, and this GC-MFC 33GC may be used as the membership function circuit of the consequent part of the implication. The same applies when there are three or more fuzzy propositions. If there are multiple implications with two or more fuzzy propositions in their antecedents, each GC-MF
Needless to say, the output of C33GC) may be applied to the MAX circuit 37 (FIG. 15).

FIG. 27 (13) shows an example of a parallel type fuzzy controller based on algebraic product rules. To explain in comparison with Fig. 27 (A), GC-MFC3
In place of 3GC, a grade controllable membership function generation circuit G C-M rG1, which will be described in detail later, is used.
3Gc is used, and the output of the QC-Ml C31GC in the previous stage is the grade control voltage V of this GC-MFG 13Gc.
As! I can get it. The output of the GC-MFG 13GG is given to the defassifier 15, making a truncation circuit unnecessary. This controller can also be expanded by using the MAX circuit 16 when there are multiple implications, and the output of the MIN or MAX circuit 24a shown in FIG.
1FG130C, it can be expanded to be applicable even when two or more fuzzy propositions exist in the antecedent part of the implication.

An example of the center of gravity determination circuit 383W in FIG. 27(^) will be briefly described with reference to FIGS. 28 and 29. FIG. 28 is a configuration example of the center of gravity determining circuit 368W, and FIG. 29 is a waveform diagram showing the operation of the fuzzy controller shown in FIG. 27 including this center of gravity determining circuit. In a sweep type fuzzy controller, a voltage signal representing an inference result is expressed on the time axis. The fuzzy inference is performed every cycle τ of the sweep signal SW, and one centroid determination operation is performed every two cycles 2τ. therefore.

The input voltage V is held constant during two periods 2τ. Let the time axis of the sweep signal SW be T, and let t be the local time variable of the voltage V13(t) representing the inference result. time t
The origin is, for example, the point where the sweep signal SW crosses zero.

As explained with reference to FIG. 9, the position of the center of gravity of the inference result B' is the point at which the area of the function B'-μ(1) is divided into left and right (front and back) halves on the time axis. The area So of the inference result B' output in the first period is determined. Then in the second cycle.

An integral operation is performed on the time axis to obtain the area of the inference result B', and this integral value is exactly S. The time point t when the value becomes /2 represents the center of gravity position. In other words, the center of gravity of the second inference result B' is expressed by the time above the time axis when the above integral value becomes So/2, the time on the time axis T at that time, or the order III of the sweep signal SW at that time. be done. This position 1 of the sweep signal SW is further expressed as the voltage VW of the sweep signal SW corresponding thereto. Therefore, this m-pressure VW is output from the center of gravity determining circuit 363W as a definitive output of the inference result B'.

Referring to FIGS. 28 and 29, the integral operation for determining the area described above can be realized by charging a capacitor, and the charging voltage represents the integral value. A capacitor C11 with a capacitance of 2co (co is a certain value).

A co capacitor C1□ whose capacitance is 1/2 of that is provided. A voltage signal VB representing the inference result is converted into a current IB corresponding to the voltage by a voltage/current conversion circuit 63 and applied to a changeover switch 64. The changeover switch 64 is used to switch whether marB flows into the capacitor C or into the capacitor C12, and is controlled by a switching control signal SC. The switching control signal SC is provided by the timing circuit 6.
It is output from 0, becomes H level in the first period, becomes L level in the second period, and repeats this in two periods 2τ.

In the first period, input current IB is applied to capacitor C, and capacitor C11 is charged.

Voltage V of capacitor C1□ when the first period ends
" represents the area So of the two feet, which is the comparator 65
is given to the negative input side child of . In the second period, current IB flows into capacitor C via changeover switch 64. Since the capacitance [2] of capacitor C12 is half the capacitance of capacitor C11, half of the charge of capacitor Ctt is transferred to capacitor C1.
When charged to □ (this means that the integrated area is So/
2), the voltage v2 of the capacitor C12 becomes equal to the voltage Vt of the capacitor C1l. The voltage of capacitor C12 is applied to the positive input side of comparator B5. Therefore, the output Vo of the comparator 65
The time when t rises is the time t representing the center of gravity. When the second period ends, the charges in the capacitors C and c are discharged by the switches 61 and 62 turned on by the reset signal PR generated from the timing circuit 60.

The output voltage (2) of the comparator 65 then detects the rise of this signal Vo, and at the time of this rise 1. is sent to a circuit that converts the voltage V into the voltage V of the corresponding sweep signal SW. Signal V. The rising edge of is detected by the differentiating circuit 66, and this rising edge detection pulse is further converted into a single pulse signal SD of a constant width by a monostable multi-by-break or the like and output. The pulse width of this pulse signal SD may be sufficient as long as it is enough time to charge a capacitor C, which will be described later.

It is preferable that it be as short as possible. Pulse signal SD is used to control analog switch 67, and this switch 67 is turned on for a period of time equal to the pulse width of pulse signal SD. Then, the sweep signal SW input to this switch 67 charges the capacitor C until it becomes equal to the voltage of this signal at that time. The voltage on capacitor C is held until the next pulse signal SD is generated. When the switch 67 is turned on by the next pulse signal SD, if the voltage of the sweep signal SW is higher than the voltage of the capacitor C, the capacitor C is charged until it becomes equal to the voltage of the sweep signal SW.

If the voltage is low, the capacitor C is discharged until the voltage becomes equal to the voltage of the sweep signal SW. In this way.

The voltage on capacitor C always represents the determined center of gravity position. This voltage is outputted as a center-of-gravity position voltage (2) via an FET input operational amplifier 68, for example.

The principle of determining the center of gravity using the circuit shown in FIG. 28 is that in the first cycle, a first capacitor with a certain capacity ff12c is charged by the input terminal, and then in the second cycle that follows,
A second capacitor with a capacity C that is half the capacity of the first capacitor is charged with the same input current, and the point t when the voltage of the second capacitor becomes equal to the voltage of the first capacitor is the center of gravity. It stands out as the time it represents. Instead of using two capacitors with capacitances of 2co and C6, two capacitors with equal capacitance can also be used. In this case, in the second integration operation of the Jl theory result, twice the current of the input side element is used. In other words, in this method, a first capacitor of a certain capacity is charged by an input terminal, and then a second capacitor of the same capacity as the first capacitor is charged by an input terminal of twice this capacity. The point 1V when the voltage of the second capacitor becomes equal to the voltage of the first capacitor may be set as the time representing the center of gravity. The voltage may be doubled instead of the 71i flow.

(4) Fuzzy controller that can be weighted for each rule As mentioned above, FIG. A type of fuzzy controller is shown. Fuzzy inference regarding one implication rule (control law) is executed by one fuzzy inference synthesis circuit 14a which receives the outputs of two membership function circuits 31a and 31b and one membership function generation circuit 13. Ru. The collection of circuits 31a, 31b, 13 and 14a will be referred to as a rule board.

In the fuzzy inference mentioned above in which there are multiple implication rules (control rules), not all implication rules always have the same importance. There may also be some very important implications.

There may also be things that are not very important. Therefore, we decided to weight the implication rules (control rules) according to their importance. This weighting is done for each rule board. Weighting is performed by simultaneously controlling the grades (peak values) of the membership functions of both the antecedent part and the consequent part, and those with high importance are set to high grades. Membership function circuits and membership function generation circuits belonging to one rule board are given the same weight. In other words, the peak membership of the antecedent part and the consequent part is set to the same value.

To weight the membership function of the membership function circuit, the grade controllable
A membership function circuit (cc-NFC) is used. In order to weight the membership functions generated from the membership function generation circuit, the grade controllable membership function generation circuit (
GC-λIFG) is used. Such GC-MF
A circuit in which one rule board R of the fuzzy controller of FIG. 14 is rewritten using C and c c -M p c is shown in FIG. In FIG. 30, the membership function circuits 31a, 31b of FIG. 14,
Membership function generation circuit 13 is GC-MFC31G
Ca, 31GCb, GC-MPG One rule shown in Figure 14 except that it is replaced with 13GC.
Board and all (same. QC-MFC31GCa,
The maximum grade (peak value of membership function) of 31GCb and GC-MI'G 13Gc is one grade control voltage V.

are controlled to be exactly the same. Even if this control voltage V is manually set externally,
Adjustments may be made using a digital computer or the like in accordance with the learning results of the controlled object using the fuzzy controller.

In the GC-NPC, the control voltage V 1 is given instead of the control voltage V 2 in the GC-NFC (configured by a combination of the grade control circuit 51 and the membership function circuit 31a or 31b) shown in FIG. G
The C-MFG will be described below.

In FIG. 31, the GC-MFG 73 includes a voltage distribution generation circuit 741 that generates a predetermined voltage distribution on a plurality of signal lines, a switch array 75 for sending the generated voltage distribution onto a predetermined output signal line, and a switch array 75 for sending the generated voltage distribution onto a predetermined output signal line. The switch array 75 decodes the code representing the label
It is composed of a decoder 76 that controls the switches of. Although the shape of the voltage distribution generated by the voltage distribution generating circuit 74 is predetermined, the position of this voltage ni on the output signal line is changed by the switch array 75 controlled by the output of the decoder 76. Therefore, a voltage distribution representing the membership function corresponding to the selected label appears on the output line. The grade (voltage value) of the voltage distribution generated by the voltage distribution generating circuit 74 is adjusted by the grade control signal (2).

Below are some G C-M I! A specific example of G will be explained, in which seven types of membership functions are generated. The labels of these membership functions are described above in 1. NL, NM, NS, ZR, PS, PM and PL
shall be. Further, it is assumed that the number of points (corresponding to the number of elements of the fuzzy set) in the domain of variables of the membership function is limited to 25.

Therefore, the membership function generation circuit has 25 output terminals.

FIGS. 32 and 33 show an example of a GC-MFG using a switch matrix as a switch array. In Fig. 32, O~24 of GC-MFG
Seven types of membership functions output from these output terminals are illustrated below the output terminals numbered up to .

The output fuzzy membership function values are quantized into four levels for simplicity.

These four levels are "Vcl"'c2"'c3""
c', and the maximum one cycle of the control sum voltage ■ is, for example, 5V.
There is. These four levels of voltage are generated in voltage distribution generating circuit 74A. This circuit 74A includes three resistors 7I connected in series, and a control 1u voltage V is applied to this resistor circuit, so that the voltage at the connection point of the resistor 71 is
,■ becomes. Therefore” cl-cl
c2 v /3. It becomes vo2-2Vo/3. This voltage characteristic 4
Five voltage lines VL drawn diagonally in FIG.
However, there is a voltage V on the lines on both sides. 2, but the two outermost lines have a voltage of V. ■ are given respectively.

Decoder 76A is a 1-of-8 decoder. This decoder 78A has 3 bits (CI, C2,
C3) binary signal is input. Decoder 76
A outputs an H level signal to one of the eight output terminals depending on the code represented by this input signal. The eight output terminals correspond to no designation and the seven types of labels described above. For example, when the 9 input code signal is ooo, an H level signal is output to the unspecified output terminal, and when it is 001, an H level signal is output to the NL output terminal. A signal line SL shown by a horizontal line in FIG. 32 extends from all of these output terminals, except for unspecified output terminals.

In the switch matrix 75A, an output line OL extends from a predetermined intersection between the Tri voltage VL and the signal line SL to the output terminal 25. A symbol 75a indicated by a small square at the intersection of these lines is provided between the voltage line VL and the output line OL, and is controlled on and off by the voltage of the signal line SL, as shown in FIG. The switch is composed of, for example, a MOS FET. Of course, two or more switches 75a may be provided on one output line OL. Each output line OL is grounded via a resistor 75b on its output terminal side.

In the M configuration described above, when a label of a certain membership function is given to the decoder 76A, an H (enable) level signal appears on one of the signal lines SL corresponding to that label, and the signal line corresponding to the label appears on the signal line SL. The switch 75a is turned on.

As a result, each voltage of the voltage component IYi generating circuit 74A appears at the corresponding output terminal via the output line OL through the turned-on switch 75a, so that a voltage distribution representing the above-mentioned membership function is output. The grade of the membership function that is output is the control voltage V. can be changed by

34 and 35 show a GC-MFG using a bus transistor array 75B as a switch array.
It shows.

The voltage distribution generation circuit 74B generates a membership function l[
In order to quantize to the level of , a voltage dividing circuit consisting of ten series resistors 71 is provided, and a control voltage V 1 is applied to this voltage dividing circuit. The fuzzy truth voltage 0゜V -V /lo, V, -2V is applied to the ground terminal and the connection point of the resistor.
o/10. -, Vc9-cl e 9V /10. V −v appear and these are Ccl[c fuzzy truth value 0. 1/In,..., 9/10
and 1, respectively. These voltages V. 1~V
clO is also a control voltage V. It is variable depending on Moreover, this generation circuit 74B is a PI? in which the value of the membership function of label -ZR is programmed. Equipped with OM.

This PRON includes a power line VL connected to the voltage source and ground, and a bus transistor array 7.
An output line OL is provided which is connected to the output terminal via 5B. The P ROM consists of two A3 layers (upper and lower layers), and the output line OL is on the first layer.

Power supply lines VL are respectively formed in the second layer. These two upper and lower layers are insulated by an insulating layer such as photosensitive polyimide. The shape of the membership function is programmed by forming through holes at the intersections of these layers. Is the through hole mask 1? Since it can be formed using OM technology, any form of membership function can be programmed. Line VL and Line O
A black circle indicating a node with L indicates a through hole.

Line VL and line OL are connected at the point where the through hole is formed, and the fuzzy truth voltage is transferred to the bus or transistor array 75B. The junction of the two lines VL and OL may be shorted using the Field 1170M technique, ie by applying a high voltage and breaking down the desired intersection.

The bus transistor array 75B connects the output line OL extending from the voltage distribution generating circuit 74B, the signal line SL connected to the seven output terminals of the decoder 76B, and the 71 voltage at the intersection of these lines by 4 digits or 4 digits to the left or right. Diagonal line BL for shifting by 8 digits, signal line SL and output line OL
and a switching element PMO3FIET 75c, which is provided at each intersection with the diagonal line BL and controlled by the voltage of the signal line SL. The state of connection of this switching element 75c is shown in the 35th
As shown in the figure. The seven signal lines SL connected to the decoder 76B or the rows of switching elements controlled by these lines are respectively switch rows S,
S2. =-s7. S x -3-t let sometimes refers to the signals on these lines SL.

Switch column S1 shifts the membership function programmed in voltage distribution generating circuit 74B four digits to the left, switch columns S, S4 and s6 shift the membership function programmed in voltage distribution generating circuit 74B four digits to the right.
Shift 8 digits to the left and 8 digits to the right. Switch columns S2 and S5 do not shift the programmed membership function to the right or left, but send it directly to the output terminal. The switch row S7 is a grounded switch array, and when this switch S7 is on and the other switches sl to S6 are off, all output terminals are dropped to the ground level.

The relationship between the label of the membership function and the binary level of the signals S and -S7 is shown in FIG. The decoder 78B inputs one 3-bit binary high signal cl.
23, c (OV or +5V) into 7-bit binary signals S1 to S7 (-5V rL level or +5VrH level) according to the table shown in FIG.
Specifically, as shown in FIG.
7 and an inverter 78 (14).

For example, if the input label is PL.

Switch rows S and S6 are turned on. The membership function programmed into the voltage distribution optical main circuit 74B is shifted four digits to the right through switch row S3 and further shifted eight digits to the right through switch row S8. Therefore, the programmed membership function will be shifted to the right by 12 digits and the membership function appearing at the output terminal will be PL (large positive value).

, in FIG. 34, the line VL connected to the ground level of the voltage distribution generation circuit 74B has 25 output lines OL in the center, as well as 12 output lines OL on each side parallel to it. In and diagonal line BL
are connected to each other, and switch arrays S1゜sss, s6 are provided at the intersections of these lines and the signal line SL. This 2° 3° 4 is to ensure that a ground level signal is output to the output terminal no matter how the programmed membership function is shifted.

Bus transistor φ array 75B must pass the fuzzy truth voltage (0-5V) to the output terminal without attenuation. In a normal I) MO8 circuit, if the fuzzy truth voltage is lower than the threshold voltage of PMO8FCT, the PMO3FET will have a gate voltage of V
. If (decoder output) is Ov, it will not be in a complete on state. In order to completely turn on PMO3PIET, it is necessary to set VG to about -5V. For this.

As mentioned above, the decoder 78B is -5V (L).

It is configured to generate an output that takes +5V (H). The 37th generator generates such output signals 81 to S7.
An example of the NAND gate 77 constituting the decoder shown in the figure is shown in FIG.

In the above description, the fuzzy membership functions are shown as chevron-shaped or triangular-shaped. However, various types of membership functions can be considered, and it is preferable to be able to select different types of membership functions as necessary.

FIG. 39 shows a GC-Mr' of the type shown in FIG. 32.
This is a voltage distribution generating circuit that is mainly applicable to G, and is a circuit that allows selection of fuzzy membership function forms. The divided voltage V controlled by the control voltage ■. The output line OL1 is connected to the voltage line VL connected to the node where c4 appears, and the output line OL1 is connected to output a voltage distribution representing a chevron-shaped or triangular fuzzy membership function form. An output line OL2 is provided, which is connected to output a voltage distribution representing the voltage distribution. Each of these lines OLI and OL2 has a switching element, NHO2FIET70A.
.

70B are connected, and on the output side of these switching elements the lines OL1. OL2 is connected to an output line OL that is connected to an output terminal. switching element 7
0B is controlled directly by selection signal C, and element 70A is controlled via inverter 79.

When the selection signal C is at L level, the switching element 70
A is turned on, and a voltage representing a chevron-shaped or triangular membership function shape is output to the output line OL. Conversely, when signal C is at H level, element 70B is turned on, so that a voltage representing a trapezoidal functional form is output. In this way.

It becomes possible to select a fuzzy membership function form.

In the circuit of FIG. 39, FIET 70A, 70
Set the threshold voltage of B to VTll (usually about IV)
If so, the binary φ level of the selection signal Cs that controls these FETs may be such that the L level is equal to or less than vTl+, and the H level is equal to or greater than VT, +5V. Here, 5V is
This is the maximum voltage of the control voltage V.

The distribution form of the generated voltage in the voltage distribution generation circuit.

That is, the fuzzy membership function form is not limited to the above two forms, but it is also possible to create three or more forms in advance so that one of these forms can be selected. It goes without saying that the selection of the function form is also applicable to the GC-MFG shown in FIG.

The voltage distribution generating circuit generates voltage signals distributed on a plurality of lines. Therefore, it is possible to apply the output voltage of one voltage distribution generating circuit to a plurality of switch arrays 75. FIG. 40 shows one voltage distribution generating circuit 74 and a plurality of switch arrays 7 to which this output voltage is applied.
GC-M Ii G including 5 is shown. Each switch array 75 is driven by a respective decoder 76. Each decoder 76 is provided with a code signal of the same or different label. Therefore, this GC-M
Voltage distributions representing a plurality of same or different membership functions can be obtained from l'G. Moreover, the grade of these multiple membership functions is controlled by the voltage V
can be controlled equally and simultaneously by

The cc-upc shown in Fig. 40 is particularly
It is suitably used in the parallel type fuzzy computer shown in the figure. In this case as well, it goes without saying that the grade should be controlled for each implication.

GC-NFC is also applicable to the sweep type fuzzy computer shown in FIG. In this case as well, it is preferable to be able to adjust the grade for each implication.

[Brief explanation of drawings]

Figure 1 is a graph showing the membership function. The same figure (A) shows the -Funetsuri shape, the same figure ([3) shows the triangular and trapezoidal functions, and the same figure (C) shows the Z function and the S function, respectively. FIG. 2 shows membership functions represented by voltages distributed on a plurality of signal lines. FIG. 3 is a waveform diagram showing waveforms of the sawtooth sweep signal and the mempage and tube function signals. FIG. 4 is a block diagram showing the concept of a basic parallel type fuzzy computer, and FIG. 5 is a block diagram showing the concept of the same type of fuzzy computer when a plurality of implications exist. FIG. 6 is a block diagram showing the configuration of a basic parallel type fuzzy inference engine. Figure 7 is a block diagram showing the concept of a basic sweep type fuzzy computer, and Figure 8 is a block diagram showing the concept of a sweep type fuzzy computer applied to fuzzy inference with multiple implications. It is. FIG. 9 is an explanatory diagram showing the process of fuzzy inference in a membrane style. FIG. 1O shows the H concept of a parallel type extended fuzzy inference engine, and FIG. 11 is a block diagram showing its configuration. FIGS. 12 and 13 are explanatory diagrams of the inference process in the fuzzy controller. FIG. 14 is a block diagram showing the configuration of a parallel φ type fuzzy controller. FIG. 15 is a block diagram showing the configuration of a sweep type fuzzy controller, and FIG. 16 is a block diagram showing another example of the same controller. FIG. 17 is an explanatory diagram of the inference process when the consequent part of an implication is expressed as an Nangleton. FIG. 18 is a circuit diagram of a weighted addition circuit, and FIG. 19 is a circuit diagram of a simple addition circuit. FIG. 20 is a graph showing membership functions, their labels, and their singleton forms. FIG. 21 is a circuit diagram of the old N circuit, and FIG. 22 is a circuit diagram of the MAX circuit. FIG. 23 is a circuit diagram showing the configuration of a fuzzy processor,
FIG. 24 is a circuit diagram showing the configuration of the rule board of the fuzzy processor. Fig. 25 is a circuit diagram showing a part of the membership function circuit extracted to explain the circuit, and Fig. 26 (^)~(
H) is a graph showing signals of the same circuit. FIGS. 27(A) and 27(B) are block diagrams each showing a configuration example of a fuzzy controller that performs inference by algebraic product operations. FIG. 28 is a circuit diagram showing the configuration of the center of gravity determining circuit. FIG. 29 is a waveform diagram showing the operation of the circuit shown in FIGS. 27 and 28. FIG. 30 is a block diagram showing a rule board in a parallel type fuzzy controller that performs weighting for each rule board. FIG. 31 is a block diagram showing the basic configuration of the grade controllable membership function circuit. FIG. 32 is a circuit diagram showing a grade controller pull φ membership function generation circuit realized using a switch matrix, and FIG. 33 shows a specific configuration of symbols in FIG. 32. Fig. 34 is a circuit diagram showing a grade controllable membership function generation circuit realized using a pass transistor array, Fig. 35 shows a specific configuration of symbols in Fig. 34, and Fig. 36 34 is a table showing the operation of the decoder in FIG. 34, FIG. 37 is a circuit diagram showing a specific structure of the decoder, and FIG. 38 is a circuit diagram showing a NAND gate used in the circuit of FIG. 37. FIG. 39 is a circuit diagram showing a voltage distribution generation circuit that can select the membership function form. FIG. 40 is a block diagram showing a developed form of the grade φ controller pull membership function generating circuit. FIGS. 41 to 44 are circuit diagrams showing modified examples of the fuzzy processor. 11, 12.13...Membership function generation circuit. 130C...Grade controllable membership function generation circuit. 14...Fuzzy inference engine. 14a, 34...Fuzzy inference synthesis circuit. 31, 32.33...Membership function circuit. 31GG, 33GC, 31GCa, 3H1; Cb
...Grade controllable membership function circuit. 50... Rule 0 board t 51... Grade control circuit. 52...Switch array. 53... Connector. Below

Claims (6)

[Claims] (1) At least one membership function circuit that outputs a signal representing a membership function according to an input signal, and a plurality of switches connected in parallel to each other on the output side, each of which is provided for each control law. a plurality of control law circuits, and a weighting circuit that gives a weight to each switch in the control law circuit. A fuzzy processor with (2) The weighting circuit is constituted by a weighting addition circuit having the same number of inputs as the number of switches, and mutually corresponding switch outputs of the plurality of control law circuits are connected to corresponding inputs of the weighting addition circuit through a MAX circuit. A fuzzy processor as claimed in claim (1). (3) The above MAX circuit is provided in each control law circuit, and weights the transistor whose base is connected to the switch output and whose emitter is the output terminal of the control law circuit, and the emitters of mutually corresponding transistors in the control law circuit. The fuzzy processor according to claim 2, comprising a wired OR connected to a corresponding input of the adder circuit and a current source connected to the input side of the weighted adder circuit. (4) The membership function circuit of the control law circuit is a grade controllable membership function circuit in which the level of the output signal is controlled by the applied grade control signal, and the weighting circuit is equal to the number of the switches. a simple addition circuit configured by a weighted addition circuit having an input, in which mutually corresponding switch outputs of the plurality of control law circuits are connected to corresponding inputs of the weighted addition circuit through a MAX circuit, and adds the outputs of the MAX circuits; It further comprises: a grade level adjustment circuit that applies the same grade control signal to the grade controllable membership function circuits of all control law circuits so that the output of the simple addition circuit represents a fuzzy logic value of 1; A fuzzy processor according to claim (1). (5) At least one membership function circuit that outputs a signal representing a membership function according to an input signal, and a variable resistance circuit connected to the output side for giving a weight, and provided for each control law. A fuzzy processor is equipped with a plurality of control law circuits, and an adder circuit that adds the output signals of the control law circuits. (6) Multiple fuzzy inference circuits that perform predetermined fuzzy inference for each implication or control law, and a MA that performs MAX calculation of the output signals of the multiple fuzzy inference circuits.
It is composed of an transistors each provided on the first substrate, the output of the fuzzy inference circuit being given to the base and the emitter serving as the output terminal of the first substrate; and a current source provided on the second substrate and connected to the input terminal thereof. and a wired OR configured by connecting the output terminals of the first board to the input terminals of the second board through connectors, respectively.