JPH03123070A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device used in an optical receiving circuit section in an optical data link, an optical CATV system, etc., and particularly relates to reducing stray capacitance.

[Conventional technology]

A conventional optical receiving circuit of this type is shown in FIG. The optical signal is received by the light receiving element 1 and converted into a voltage signal by the resistor RL. The DC component of the received signal converted into a voltage signal is removed by a capacitor C6, and the amplifier 2 amplifies and demodulates the received signal. These resistances R
, capacitor C6 and amplifier 2 are integrated into one integrated circuit (I
C) Built into the chip 3. -For boat fishing,
The resistance Rt is approximately several hundred Ω to IOKΩ, and the DC blocking capacitor Cc is several pF to several hundred pF. In addition, the light receiving element 1
A junction capacitance C of approximately 0.5 pF is generated at the PN junction of the capacitor Cc, and a stray capacitance D with respect to the ground is generated in the capacitor Cc.An input capacitance G CIN is generated at the input portion of the amplifier 2. Here, the high cutoff frequency F of the received signal
And the low cutoff frequency FL is expressed by the following equation, where RI N h is the input resistance of the amplifier 2.

F -1/[2π(R//R,N) HL (CPD+CIN0ccG)] ... (1) F -1/[2π(Rb//RI N)" CC
]L ... (2) [Problem to be solved by the invention] However, in the above conventional device configuration, the equation (1
), if the value of resistor R1 is increased to increase the receiving sensitivity of the circuit, the signal-to-noise ratio (S/N ratio) improves and the receiving sensitivity improves, but the high cutoff frequency There was a problem that FH decreased. When the value of this resistance Rt is constant, (CPD + CI N
The smaller the value of +CCG>, the higher the cutoff frequency FH.
becomes higher.

Also, as understood from equation (2), in order to lower the low cutoff frequency F, if the value of the resistor Rt is constant, it is necessary to increase the value of the DC cutoff capacitor Cc. be. Therefore, in the chip pattern inside the IC chip 3 shown in FIG. 4, the chip pattern 4 of the capacitor Cc occupies a large proportion of the total pattern area. Therefore, the value of the stray capacitance C66 generated between the chip pattern 4 and the ground pattern (not shown) formed on the entire back surface of the IC chip 3 becomes large.
There was a problem that the high cutoff frequency FH was lowered. Furthermore, if the value of the capacitor C6 is reduced in order to reduce the stray capacitance C60, the low cutoff frequency Ft will become higher, resulting in an increase in jitter.

The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device with high reception sensitivity and a wide reception band.

[Means to solve the problem]

The present invention provides a semiconductor substrate in which the crystal structure of a predetermined region is destroyed, a circuit element monolithically formed on the front surface of the semiconductor substrate located above the predetermined region, and a circuit element formed monolithically on the back surface of the semiconductor substrate located below the predetermined region. The wiring pattern is set to the reference potential of the electric circuit.

[Effect]

Almost no charge change occurs in circuit elements and wiring patterns formed between predetermined regions where the crystal structure is destroyed.

〔Example〕

FIG. 2 is a circuit diagram showing an optical receiving circuit according to an embodiment of the present invention, which is monolithically formed on a semiconductor substrate to be described later.

A resistor Rt is connected in series to the photodiode 11. One end of a capacitor Cc is connected to the connection point between the photodiode 11 and the resistor RL, and the other end is connected to the input of a buffer amplifier 12, which is a non-rotating amplifier with an amplification factor of 1. This buffer amplifier 12 is composed of a source follower circuit, etc., and its output is given to an amplifier 13. The output of the amplifier 13 is connected to an external terminal 14, and this external terminal 14 is connected to a receiving device (not shown). Further, the output of the buffer amplifier 12 is connected to an isolated pattern 27, which will be described later.

1 shows a part of the semiconductor substrate on which the optical receiver circuit shown in FIG. 2 is formed, FIG. 1(a) is a plan view, and FIG. 1(b)
is a cross-sectional view, and (c) is a back view.

The above-mentioned optical receiving circuit is formed on the semiconductor substrate 21, and a capacitor C which is a part of the circuit is shown in FIG. One end of the capacitor Cc is connected to a resistor RL (not shown) through a wiring pattern 22, and the other end is connected to an input of a buffer amplifier 12 (not shown) through a wiring pattern 23. Also,
One end of the wiring pattern 24 is connected to the output of the buffer amplifier 12.

The capacitor C6 is composed of a first wiring layer 22g and a second wiring layer 23a with an insulating film 25 interposed therebetween, as shown in FIG. 2(b). Also, capacitor C6
Protons (H ions) accelerated by a high electric field are implanted into a predetermined region 29 of the semiconductor substrate 21 located under the semiconductor substrate 21, and its crystal structure is destroyed.

On the back surface of the semiconductor substrate 21, as shown in FIG. 2(c), a ground pattern 26 with a wide area is formed by metallizing gold palladium, silver palladium, or the like. This ground pattern 26 is connected to the semiconductor substrate 21.
This is set as the reference potential of the optical receiving circuit formed in the. Further, by patterning the metallized metal using an etching technique, an island-shaped isolated pattern 27 is formed electrically separated from the ground pattern 26. This isolated pattern 27 is connected to the wiring pattern 24 via a VIA hole 28, and is set to the same potential as the output voltage of the buffer amplifier 12.

In such a configuration, when an optical signal is received by the photodiode 11, the optical signal is converted into an optical output current. This optical output current is converted into a voltage signal by resistor RL, and further, the DC component of this voltage signal is removed by capacitor C6. The received signal from which the DC component has been removed passes through a buffer amplifier 12, is amplified and demodulated by an amplifier 13, and is provided to a receiving device via an external terminal 14. Further, the received signal output from the buffer amplifier 12 is given to the isolated pattern 27.

Therefore, the alternating current voltage change of the second wiring layer 23a constituting one electrode of the capacitor C6 is approximately equal to the alternating current voltage change of the isolated pattern 27. In other words, the second wiring layer 23a
The amplitudes of the voltages at each part of the isolated pattern 27 located on the back surface thereof are approximately equal, and the phases thereof are also equal. Furthermore, almost no change in charge occurs in the second wiring layer 23a and the isolated pattern 27, which are formed sandwiching the region 29 in which the crystal structure is destroyed. This is because almost no charge is generated in the region 29 due to the destruction of the crystal structure. Here, the stray capacitance C60 of the capacitor Cc with respect to the ground (isolated pattern 27) is
and the isolated pattern 27, and is the ratio of the change in charge ΔQ accumulated between the two electrodes to the voltage change ΔV between the two electrodes. Therefore, wiring layer 2
3a and the isolated pattern 27, the voltage change ΔV and charge change ΔQ are almost non-existent as described above, so the stray capacitance C
6G will hardly be generated.

Therefore, the high cutoff frequency Fn of the received signal shown in equation (1) can be made high because the stray capacitance C60 can be ignored. Furthermore, it becomes possible to increase the capacitance value of the DC cutoff capacitor co without considering the stray capacitance C60, and the low cutoff frequency FL shown in equation (2) can be lowered. Therefore, the reception band of the circuit is widened. Furthermore, since the capacitance i c cc decreases in equation (1) and the capacitance Cc increases in equation (2), it becomes possible to increase the value of the resistor RL, and the receiving sensitivity of the circuit increases.

By the way, the low cutoff frequency FL in this type of optical receiving circuit is usually 1/1.00 of the high cutoff frequency FH.
~l/1000 or less. Therefore, for example, when trying to create an optical receiver circuit with a bandwidth of 500 MHz, the low cutoff frequency FL must be 5 MHz or less. Furthermore, if the minimum receiving sensitivity of the circuit is set to -30 dBm, the value of the resistor R1 connected in series with the photodiode 11 must be at least IKΩ. in this case,
The capacitance value of the DC cutoff capacitor C6 is determined as follows by substituting each constant value into the equation (2) indicating the low cutoff frequency Ft. Here, the value of resistor RL is amplifier 1
Since it is sufficiently large compared to the input resistance RIN of No. 3, the resistance R
The value of the parallel combined resistance RL/1RIN of and resistance RIN is approximately equal to the value of resistance Rt.

3 5X10 -1/(2π・1×10・Cc),',
Cc -31, 8p F Capacitor that can be fabricated monolithically on IC is 0.0
It is about 5 to 0.1 f F/μm2, where 0.1
Even if a capacitor of fF/μm2 can be manufactured, the area of the capacitor C6 will be 318.000 μm2.

When a capacitor C6 having this area is realized using the conventional device configuration shown in FIG. 3, its stray capacitance C66 with respect to the ground becomes as follows, assuming that the IC is formed from gallium arsenide (G a As ). . Here, GaA
The thickness of the s-substrate is generally 400 μm, and its dielectric constant ε is 13.

CcG-C0ε・318000/40092fF Generally, the value of the sum (C2D+CIN) of the junction capacitance CPD of the light receiving element 1 and the input capacitance C of the amplifier 2 is N 0.4 to 0.69F, so the conventional device configuration The proportion of stray capacitance CcG in this sum is approximately 20%.
It becomes something that cannot be ignored. Therefore, the denominator of equation (1) becomes large, and the high cutoff frequency F becomes the stray capacitance C6
It decreases due to the influence of 0.

As a result, the bandwidth of the signal received by the circuit becomes narrow.

However, according to the above embodiment, as described above, the voltage changes of each electrode constituting the stray capacitance C66 are approximately equal, and furthermore, there is almost no change in the charge accumulated in each electrode. Therefore, the area of capacitor C is 318,000μ
Even if it becomes large as m2, stray capacitance C66 with respect to the isolated pattern 27 hardly occurs. Therefore, the bandwidth of the signal received by the circuit becomes wider, and the reception sensitivity of the circuit becomes higher.

In addition, in the description of the above embodiment, the isolated pattern 27
Although the output voltage of the buffer amplifier 12 is applied to the second wiring layer 23a and the isolated pattern 27 are formed so that the voltage changes are approximately equal to each other, this structure is not necessarily required. In other words, only by destroying the crystal structure of the region 29, the ratio of the charge change ΔQ to the voltage change ΔV becomes almost zero, making it possible to sufficiently reduce the stray capacitance i c cc.

〔Effect of the invention〕

As described above, according to the present invention, almost no charge change occurs in the circuit elements and wiring patterns formed between the predetermined regions in which the crystal structure has been destroyed. Therefore, almost no stray capacitance is generated in the capacitor that removes the DC component of the received signal, and a semiconductor device with high reception sensitivity and a wide reception band can be provided.

Therefore, the present invention is particularly effective when applied to high-speed, broadband communication systems.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a part of a semiconductor device showing an embodiment of the present invention, FIG. 1(b) is a cross-sectional view of this semiconductor device, and FIG. 1(c) is a cross-sectional view of this semiconductor device. 2 is a diagram of the optical receiving circuit formed in the semiconductor device shown in FIG. 1, FIG. 3 is a diagram of the optical receiving circuit formed in the conventional semiconductor device, and FIG. 4 is a diagram of the optical receiving circuit formed in the conventional semiconductor device. FIG. 3 is a chip pattern diagram of the conventional IC chip shown in the figure. 21... Semiconductor substrate, 22, 23. 24... Wiring pattern, 22a... First wiring layer, 23a... Second
wiring layer, 25... insulating film, 26... ground pattern, 27... isolated pattern, 28... VIA hole, 29... region where crystal structure is destroyed, co...
DC blocking capacitor.

Claims (1)

[Claims] A semiconductor substrate in which the crystal structure in a predetermined region is destroyed, a circuit element monolithically formed on the front surface of the semiconductor substrate located on the predetermined region, and a circuit element formed on the back surface of the semiconductor substrate located under the predetermined region. and a wiring pattern set to a reference potential of an electric circuit configured using the circuit element.