JPH03121547A - Cache memory control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a cache memory system.

[Conventional technology]

Traditional cache memory systems, e.g.

An example thereof is disclosed in Japanese Unexamined Patent Publication No. 61-59554.

A control method of a conventional cache memory system will be explained with reference to FIG. In Fig. 3, 1 is the central processing unit (C
PU), 2 is a memory management unit (MMU), and 3 is a memory control unit (MMU) that controls main memory access.
CU), 4 is logical address tag and valid bit (V)
The address array (AA) 5 has a cache memory (buffer storage) that temporarily stores the contents of the main memory in order to reduce the access time of the main memory
BS), 6 is a main memory (MM), 7 is a physical address generation unit including an address translation buffer (TLB), 8 is an internal stage control unit, 9 is a main memory control unit, 10 is an address array control unit, 11 is a Address array (cache memory) hit determination unit, 14 is a logical address bus, 15 is a data bus, 16 is a physical address bus, 17 is an address array data bus, 18 is an address array write enable signal (AAWE-N), 19 is Cache memory write enable (BSWE-N).

20 is a cache hit signal (which goes to 'L' level when the address array (cache memory) is hit);
BSHiT-N), 22 is a memory access stage T
4. 23 is a write control signal (WRiTE-N) for MCU3 when writing data to MM6; 26 and 27 are three-state bus drivers. Generally, the CPUI is MM
When attempting to read the contents of 6, the physical address generation unit 7 that receives the logical address bus 14 outputs the physical address to the bus 16. At this time, the address array hit determination unit 11 determines the physical address and the address array data bus 1.
By comparing the address tag part that comes out via step 7 and referring to the valid bit (V), it is possible to determine whether the address array is hit, that is, whether the contents of the corresponding physical address are temporarily stored in the cache memory. judge. If the hit occurs, the hit signal (BS
HiT-N) 20 to l L 1 level. In the case of a cache hit, the contents of the cache memory (O8) 5 are taken into the CPUI via the data bus 15, and if there is a miss, that is, the cache memory (BS) 5
If the content of the corresponding physical address is not stored in the memory control unit 9, the main memory control unit 9
3 is activated to access the main storage device 6.

On the other hand, if there is a miss during write access, the write control signal 23 output from the main memory control unit 9 causes the MM6
You only need to write to .

If it is a hit, data must be written to the cache memory 5 at the same time as MM6. Therefore, after the cache hit signal 20 is determined, if it is a hit, the cache memory write enable signal (BSWE-N) 19 is written.
Cache memory (BS) with j L l level
5 is generally written.

An example of a timing chart of this write operation is shown in FIG. Here, CLK is a basic clock, and ALE-N is an address latch enable signal indicating that a valid physical address is being output. In this conventional example, write access is performed in 6 clocks of To-T5, and FIG. 11A shows the timing when a cache memory hit occurs, and FIG. 11B shows the timing when a cache memory miss occurs. Also t
represents the time from the start of memory access until the cache hit signal 20 is determined.

In this conventional example, the write signal 23 is asserted at the rising edge of the basic clock T2 to start writing to the main memory device 6. However, at that point, the cache memory (BS
) 5 human judgment is not completed. Since the cache memory hit determination is confirmed in the middle of T3, assuming that the write enable of the address array requires two clocks,
In the case of humans, as in (,), T4. AAWE- at T5
Assert N, if mishint AAWE-N is l
The control is fixed at HT.

In addition, as a prior art related to this matter, there is also the Japanese Unexamined Patent Application Publication No. 63
-300339 and Japanese Patent Application Laid-Open No. 64-26253.

[Problem to be solved by the invention]

The above-mentioned conventional technology has the disadvantage that if the hit determination of the cache memory is slow, all write cycles are extended because it is not determined whether it is acceptable to write to the cache memory until the hit determination is completed. Memory cycles are an important issue because even one clock affects the performance of the entire system.

The purpose of the present invention is to
Reduce memory write cycle time.

The purpose is to invalidate the performance of the entire cache memory system.

[Means to solve the problem]

In order to achieve the above object, in the present invention, all the
- At the time of access, before the cache memory hit determination is completed, data is also written to the cache memory at the same time as the write to the main memory is started, and it is later determined that there is a miss.

The configuration is such that the valid bit in the address array is set to 0' to invalidate the entry (block cancel). Furthermore, a decode signal of a bit in a control register, a logical address, or a physical address is used as a setting condition for a mode for writing to the cache memory before a hit determination.

[Effect]

Since data is written to the cache memory without waiting for cache hit determination, the length of one write cycle can be shortened. In addition, when a miss occurs, the valid bit is set to 0' to invalidate the entry, but in the case of a program that has an extremely high cache memory hit limit (hit rate), the hit rate decreases due to cache memory invalidation. Since the effect of shortening one write cycle is more effective on the overall information processing time, the performance of the entire system can be improved.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In addition to the conventional system configuration diagram in Figure 3, 1 in Figure 1
2 is a control register that can be rewritten from the central processing unit (Cr'U) 1, and 21 is a memory access stage T3.
．． Stage signal at I Hl level during T4, 2
4 is a stage signal that is at LHj level during the period of memory access stage T4, and 28 is a control register 1.
This is the write cycle mode switching bit (M) in 2. In this embodiment, when the CPUI attempts to write data, if the mode switching bit 28 in the control register 12 is set to 1', the stage signal 21
By character, Tayu memory hit.

Data is written to the cache memory every time regardless of a miss. In addition, when there is a mishit, that is, when the cash hit signal 20 is 1)■', the address array control controls to set the valid bit of the corresponding entry in the address array to 10' at the timing of T4 using the stage signal 24. Department 10 will conduct this.

A timing chart at this time is shown in FIG.

Here, write access is performed in five clocks from TO to T4, and by writing to the cache memory before determining a hit, the memory cycle can be shortened by one clock. Also.

If the mode switching bit 28 of the control register 12 is set to 0', write access control similar to the conventional example is performed. As a result, when the hit rate of the cache memory is high, the write access cycle is shortened by one clock, and the information processing performance of the entire system is improved.

Furthermore, by rewriting the mode switching bit 28 according to the level of the hit rate of the program, it is possible to use the two modes described above and to set the cache memory control optimal for the system.

Further, an embodiment using a different mode switching method will be described with reference to FIGS. 2 and 6. Reference numeral 13 in FIG. 2 is an address decoder, which is provided as an alternative to the control register 12 of the previous embodiment.

FIG. 6 is a physical address space map of the processing device of this embodiment, including area A and territory area. The address decoder 13 in FIG. 2 is set to output '1' to the signal line 25 only when the address of area A, area on the address map is specified. Here, if a program with a high cash hit rate is placed in area A or area B in the address space, the information processing performance of the entire system will be improved, as in the previous embodiment. Furthermore, by using the address decode signal as a condition for mode switching, it is possible to save the effort of rewriting the control register in the previous embodiment. Here, areas A and B may be placed anywhere on the address map, and it does not matter how many areas the area is divided into.

Although the above two embodiments have been described, these are just one embodiment, and the gist of the present invention is to provide a means for writing to the cache memory before determining the hit of the cache memory,
The purpose of this embodiment is to shorten the first access cycle of the cache memory system, and the timing does not necessarily have to be the same as that of this embodiment. Furthermore, the address to be decoded in the second embodiment may be a logical address.

In addition, in the above embodiment, the central processing unit (CPU)
Although the description has been made regarding the cache memory of No. 1, it goes without saying that the present invention can also be applied to other cache memory systems such as a disk cache.

〔Effect of the invention〕

According to the present invention, since the write access cycle of the cache memory system can be shortened, the information processing efficiency of the system can be improved.

This effect is particularly significant when the cache hit rate is high.

Furthermore, in programs where the hit rate is not very high, since the program provides means for use in combination with the conventional cache access method, it is possible to prevent the hit rate from decreasing due to invalidation of the cache memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a memory write cycle of the present invention. FIG. 5 is a timing diagram of a write cycle in the conventional example, and FIG. 6 is a diagram showing a physical address space map in the second embodiment. 1... Central processing unit, 2... Memory management unit,
3...Memory control unit, 4...Address array, 5...Cache memory, 11...Address array (cache memory) hit determination section, 12...Control register, 13...Address decoder. Figure 4 Atsushi Figure 5

Claims (1)

[Scope of Claims] 1. In an information processing device having a cache memory that stores a part of data in a storage device, during a data write operation, the cache memory and the storage device are 1. A cache memory control method, comprising: performing a writing operation to both of the cache memory, and setting a mode in which, after a hit determination, an entry is invalidated only when a mis-hit occurs in the cache memory. 2. The cache memory control method according to claim 1, wherein the mode setting is controlled by a decode signal of an address to be accessed. 3. A cache memory control method, characterized in that the mode setting is performed by control register means that is rewritable from a central processing unit. 4. In a data processing device having a storage device and a cache memory that stores a part of the contents of the storage device, whether or not an access to the storage device is to an area stored in the cache memory during a data write operation. means for writing data into the cache memory and the storage device before a hit determination is completed, and means for invalidating the data write entry in the case of a miss after the hit determination. A cache memory control device characterized by: 5. The data processing device according to claim 4 has a mode setting means that can be rewritten by a central processing unit, and the data writing means and the invalidation means are controlled by the mode setting means. Characteristic cache memory control device. 6. The data processing device according to claim 4 has means for decoding an address from the central processing unit, and the data writing means and the invalidating means are controlled by the output of the decoding means. A cache memory control device characterized by: