JPH03121503A - Operation display panel with sequence control function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a programmable operation panel for mechanical equipment, etc., and more specifically, a first processor that controls the mechanical equipment and has a sequence function, and a switch item. This is a small and easy-to-operate operation display with a sequence control function, consisting of a display panel that displays on the screen, switches corresponding to the switch items on the panel display screen, and a second processor that controls the display panel and the switches. Regarding the panel.

[Conventional technology]

A conventional programmable operation panel has a control section that controls mechanical equipment and has a sequence function, a display panel that displays switch items on a screen, and an operation section that operates and controls switches corresponding to the switch items on the panel display screen. Provided in separate locations, between them R3-232C, R
Serial interface such as 3-422 or DI/D
They are connected to each other by an o-coupled parallel interface and function as an operation panel.

In addition, as an integrated control unit and operation unit, 1
In some cases, the control section and operation section are controlled by two processors to realize the operation panel.
ual port memory).

Furthermore, devices having a separate processor for memory control are also known.

[Problem to be solved by the invention]

Conventional devices have the following problems.

i) In a device in which a control section and an operation section are connected through an interface, there is a problem that there is a large time delay because manipulated information or control information is transmitted through the interface. Attempts to speed up the interface in order to minimize time delays are expensive and complicate control. In addition, since transmission is used, the amount of data that can be transmitted at one time is limited, and as a result, the transmitted data is used redundantly between the screens displayed on the display panel, and the control side has to send/receive it. A program is required to distribute and collect data to the areas used on each screen, which complicates control. In addition, a means for confirming whether the transmitted data has been correctly transmitted to the other party is required, and the control program becomes complicated.

ii) If the control unit and the operation unit are integrated using individual (two) processors, when operation information is generated on the operation unit side, it is set in memory regardless of the control unit side.
One switch during one scan of control on the control unit side
There is a high possibility that the N case and the OFF case will be mixed.
It may become impossible to maintain the correct state of data, leading to incorrect control. Dual-port memory and processors are also more expensive than regular memory.

1ii) If one processor is used, the one processor must have both control and operation functions, which may lead to a decrease in control performance. If a high-performance processor is used without deterioration, it will be more expensive than one with two processors.

Therefore, an object of the present invention is to provide an operation display panel that is low in cost, has good operability, and is user-friendly (high degree of freedom) for the user.

[Means to solve the problem]

a first processor that performs sequence control operations based on the operating status of an external device and a built-in program;
A first storage means for storing input/output data for the processor, a second storage means for storing switch item screen data, and a display panel for displaying the switch items on the screen according to the screen data read from the second storage means. a switch means for generating and outputting information of the item each time the switch item is operated corresponding to the switch item on the panel display screen; a second processor for controlling the display panel and the switch means; third storage means for storing input/output data for the second processor;
Transfer means is provided for setting output information to be outputted from the processor to the first processor in the third storage means, and copying and transferring this together with the transferred data to the first storage means.

[Effect]

By organically coupling the first processor and the second processor to each other via their respective storage means, operability and performance are improved.

〔Example〕

FIG. 1 is a system configuration diagram showing an embodiment of the present invention, and shows an example of a programmable operation display panel of an assembly processing machine.

An assembly processing machine consists of a transport mechanism for the workpiece, various processing mechanisms that perform processing on the workpiece, etc.The workpiece is detected by a sensor, transported by the transport mechanism, and processed by the processing mechanism. In addition to being configured so that the product can be finished using the machine, it is also equipped with a control device that displays the status of each sensor and controls the conveyance in order to cancel operation and adjust machine operation in the event of an abnormal condition. Step operations using the drive mechanism can be performed from the operation panel. For these functions, please use a commercially available programmable controller (sequencer).
Since this is a function that boat fishing has, a detailed explanation of how to implement it will be omitted.

Although not shown, the sequencer is naturally equipped with reading means for reading outputs from various sensors, and output means for outputting signals to control the transport mechanism and the processing N structure. It is assumed that

In Fig. 1, 1 is a microcomputer system as an operation display CPU (central processing unit), 2 is a character generator (CG) that generates display characters, and 3 is a screen memory (EEFRO) for storing graphic data that makes up the screen.
M) (Instead of using the above CG2, use this screen memory 3
), 4.
is a data memory (RAM) for holding quantitative data displayed on the screen (by storing the operating status for each screen in this memory 4, it is easy to restart after the power is turned off. (Also, this memory 4 is preferably bank-amplified with a battery so that it becomes a non-volatile memory), 5 is an internal bus, and 6 is a transparent touch key that integrates a display panel and a transparent switch. One of these days,
In particular, the reference numeral 6a is used to refer to a transparent switch, and the reference numeral 6b is used to refer to a display panel (although neither 6a nor 3b are directly shown in FIG. 1).

Note that the transparent switch 6a is located on the display screen of the display panel 6b, and by touching the switch item displayed on the screen through the transparent body that constitutes the transparent switch 6a, the corresponding operation can be performed from the transparent switch 6a. The transparent touch key 6 is designed to generate a switch output to
This has been well known for a long time.

7 is a key encoder (which receives the operation output of the transparent switch 6a, encodes it and transmits it to the microcomputer system 1), 8 is an operation switch, and 9 is a microcomputer system (CPU) that functions as a sequencer. A machine (not shown), in this case an assembly processing machine, is connected to the end of this sequencer, and the procedure (program) of the assembly processing machine is controlled by this sequencer. 10 is a zero memory for storing information to be output to the sequencer CPU 9 of the operation switch, and 11 is a memory for storing information to be output to the sequencer CPU 9 of the operation switch.
DMA (Direct Me
It is a controller. 12 is I10 memory on the operation display CPUI side,
13 is an I10 memory of nine example sequencer CPUs. 1
4 is an indicator lamp, 15 is an alarm relay, and 16 is a buzzer.

In such a system configuration, the sequencer GPU 9
The processing is as shown in Figure 2. That is, there is a process S1 that controls the sequence of the assembly processing machine and a data transfer process S2 to the I10 memory 13. After executing the sequence process (1 scan), the data of the scan result is transferred to the I10 memory 13. Repeat the process alternately.

All memory transfers between the I10 memory 13 and the I10 memory 12 are carried out by the operation display CPU 9 while stopping the operation of the sequencer CPU 9 in accordance with the flowchart of FIG. The operation display CPUI executes the flowchart of FIG. 3 by interrupt.

That is, the operation display CPUI learns from the interrupt that one scan of sequence processing by the sequencer CPU 9 has been completed, and executes step S3.

In step S3, the DMA controller 11 is used to transfer all the contents of the I10 memory 13 of the sequencer CPU 9 to its own I10 memory 12.

At this time, not all of the data from the I10 memory 13 may be transferred, but only the data necessary for the operation display CPUI may be transferred. In step S4, I
The information stored in the memory 10 that is to be output to the sequencer CPU 9 is transferred to the memory (110
memory 12). In step S5, the memory contents set in step S4 are copied to the I10 memory 13 of the sequencer CPU 9 using the DMA controller 11, together with the previously transferred data.

This makes the state of the I10 memory 13 of the sequencer CPU 9 equal to the state of the I10 memory 12 of the operation display CPUI, and data can be synchronized. Further, by executing the flowchart processing shown in FIG. 3, it is possible to set the data even if the output addresses of each CPU are adjacent to each other and mixed in a random manner.

Next, processing other than when interrupting by the operation display CPUI will be explained with reference to FIG.

First, in step S6, data is read from the I10 memory 12, and in step S7, it is checked whether or not the data is failure data. If it is failure data, a failure inspection display is performed on the display panel 6b (see 59). If not, it is checked in step S8 whether it is a menu request for screen switching, and if it is a menu request, a screen menu is displayed on the display panel 6b in step SIO. In step Sll, the inputs of the transparent switch 6a and the operation switch 8 are checked, and if there is an input, it is determined in step 312 whether or not the screen is to be switched, and if it is screen control, step S
At step 13, screen switching and screen display output are performed. Step S
At step 14, it is checked whether the operation content should be output to the sequencer CPU 9, and if it is, it is set in the 0 memory 10. This O memory 10. The contents of will be used during the memory transfer shown in FIG.

Through the above-described procedure, it is possible to realize an operation display panel with a sequence control function that has a control function, is small in size, and has excellent operability.

〔Effect of the invention〕

According to the present invention, since control can be performed without using communication and while synchronizing data between external control and operation display control, it is possible to realize a small and high-performance operation display panel. In addition, it is inexpensive because it does not require the use of expensive components such as dual port memory. Furthermore, since the operation contents on the operation display panel are directly transmitted to the target mechanical device through the sequencer, the basic function as an operation display panel for controlling mechanical devices etc. is not lacking.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram showing an embodiment of this invention;
The figure is an explanatory diagram to explain the functions of the sequencer CPU, Figure 3 is a flowchart to explain the memory transfer operation by the operation display CPU, and Figure 4 is the operation display CPU.
3 is a flowchart for explaining processing operations other than when interrupted by I; Code explanation 1... Operation display CPUI (microcomputer system),
2... Character generator (CG), 3...
Screen memory (EEFROM), 4...Data memory (RAM), 5...Internal bus, 6...Transparent touch key, 6a...Transparent switch, 6b...Display panel, 7...Key Encoder, 8...operation switch, 9...sequencer CPU (microcomputer system),
10...0 memory, 11...DMA controller,
12.13...I10 memory, 14...display lamp, 15...alarm relay 16...buzzer

Claims (1)

[Claims] 1) a first processor that performs sequence control operations based on the operating status of an external device and a built-in program; a first storage means that stores input/output data for the first processor; a second storage means for storing switch item screen data; a display panel for displaying switch items on the screen according to the screen data read from the second storage means; a switch means for generating and outputting information on the item each time; a second processor for controlling the display panel and the switch means; and a third storage means for storing input/output data for the second processor. and while transferring data from the first storage means to the third storage means, setting output information to be output from the second processor to the first processor in the third storage means, and storing this together with the transferred data. 1. An operation display panel with a sequence control function, comprising: a transfer means for copying and transferring data to a storage means; 2) The operation display panel with a sequence control function according to claim 1, wherein the data to be transferred from the first storage means to the third storage means is limited to only what is necessary for the second processor.