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JPH03120791A - Via formation method on aluminum nitride substrate - Google Patents

Via formation method on aluminum nitride substrate

Info

Publication number
JPH03120791A
JPH03120791A JP25806589A JP25806589A JPH03120791A JP H03120791 A JPH03120791 A JP H03120791A JP 25806589 A JP25806589 A JP 25806589A JP 25806589 A JP25806589 A JP 25806589A JP H03120791 A JPH03120791 A JP H03120791A
Authority
JP
Japan
Prior art keywords
paste
via holes
aln
green sheet
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25806589A
Other languages
Japanese (ja)
Other versions
JP2699581B2 (en
Inventor
Koji Omote
孝司 表
Hirozo Yokoyama
横山 博三
Mineharu Tsukada
峰春 塚田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25806589A priority Critical patent/JP2699581B2/en
Publication of JPH03120791A publication Critical patent/JPH03120791A/en
Application granted granted Critical
Publication of JP2699581B2 publication Critical patent/JP2699581B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To prevent the occurrence of cracks in via boles which result in inferior continuity by filling the via holes provided in an AlN green sheet with W paste after applying W paste to which AlN is added to the inner surface of the via holes and calcining the green sheet in a non-oxidative atmosphere. CONSTITUTION:After W paste 3 mixed with AlN is thinly applied to the inner surface of via holes 2 provided in an AlN green sheet 1, the via holes 2 are filled up with W paste and the green sheet 1 is burned. When such process is used, effects of the burning shrinkage of the AlN and W can be relieved and low-resistance via holes can be formed. In addition, after a piece of porous water absorbing paper 7 is placed on a pressure reducing container 6 with numerous holes 5, the green sheet 1 and a mask 6 which is accurately positioned to the via holes 2 are successively put on the paper 7 and low-viscosity W paste mixed with AlN is fed onto the mask. When the pressure is reduced through the paper 7 by operating an exhaust system, the W paste mixed with AlN gets into the via holes 2 and adheres to the inner surface of the holes. Therefore, via holes which are free from cracks can be obtained.

Description

【発明の詳細な説明】 〔概要] 窒化アルミニウム基板のビア形成方法に関し、低抵抗の
ビアを形成することを目的とし、窒化アルミニウムグリ
ンシートに設けたビアホールの内壁に窒化アルミニウム
を添加したタングステンペーストを塗布して乾燥した後
、該ビアホールにタングステンペース1−を充填し、非
酸化性雰囲気中で焼成することを特徴として窒化アルミ
ニウム基板のビア形成方法を構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for forming a via in an aluminum nitride substrate, for the purpose of forming a via with low resistance, a tungsten paste added with aluminum nitride is applied to the inner wall of a via hole provided in an aluminum nitride green sheet. After coating and drying, the via hole is filled with tungsten paste 1- and fired in a non-oxidizing atmosphere.

〔産業上の利用分野〕[Industrial application field]

本発明は窒化アルミニウム(以下略してAρN)基板に
ついて低抵抗のビア形成方法に関する。
The present invention relates to a method for forming a low resistance via on an aluminum nitride (AρN) substrate.

大量の情報を高速に処理する必要から情報処理装置は小
形大容量化が行われており、この装置の主体を占める半
導体集積回路は集積度が向上してLSIやVLSIが実
用化されている。
Due to the need to process a large amount of information at high speed, information processing devices are becoming smaller and larger in capacity, and the degree of integration of semiconductor integrated circuits that form the main body of these devices has improved, and LSI and VLSI have been put into practical use.

一方、これらの集積回路はチップのま\で複数個をセラ
ミックスからなるチップ搭載用基板(インターポーザ)
に搭載してLSI モジュールを作り、これを取替え単
位として印刷配線基板などに装着する実装形体がとられ
つ\ある。
On the other hand, these integrated circuits are still chips and are mounted on a chip mounting substrate (interposer) made of ceramics.
A mounting system is being adopted in which an LSI module is created by mounting it on a printed wiring board or the like as a replacement unit.

このように半導体集積回路の集積度が増し、また高密度
実装が行われるに従って装置の発熱量も加速度的に増加
している。
As described above, as the degree of integration of semiconductor integrated circuits increases and high-density packaging is performed, the amount of heat generated by devices is also increasing at an accelerating pace.

すなわち、当初はIC−個当たりの発熱量は約35W程
度と少なかったが、現在LSI−個当たりの発熱量は約
10Wに増加しており、これがマトリックス状に多数個
装着されている場合は発熱量は膨大であり、更に増加す
る傾向にある。
In other words, in the beginning, the amount of heat generated per IC was as low as about 35W, but now the amount of heat generated per LSI has increased to about 10W, and when many of these are installed in a matrix, the amount of heat generated increases. The amount is enormous and is likely to increase further.

従来、LSIチップなどを搭載する基板は熱伝導度が高
く、耐熱性が優れたアルミナ([203)が使用されて
きた。
Conventionally, alumina ([203)], which has high thermal conductivity and excellent heat resistance, has been used for substrates on which LSI chips and the like are mounted.

然し、アルミナの熱伝導度は優れているもの\20W/
mK程度であり、上記のチップ搭載用基板用材料として
は不充分である。
However, alumina has excellent thermal conductivity\20W/
mK, which is insufficient as a material for the above-mentioned chip mounting substrate.

第1表 そこで、熱伝導度が320 W/liK (理論値)と
大きなAI!、Nが着目され、この基板の実用化が進め
られている。
Table 1 So, AI has a large thermal conductivity of 320 W/liK (theoretical value)! , N has attracted attention, and the practical use of this substrate is progressing.

第1表は両者の特性を比較したものである。Table 1 compares the characteristics of both.

すなわち、AINは熱伝導度が優れている以外に熱膨張
係数が小さく、LSIを構成するSiの熱膨張係数(3
,6XIO−6/ ’C)に近(、また誘電率が小さい
ことは多層基板を形成する場合に漏話(Crossta
lk)を少なくできる点からも有利である。
In other words, in addition to its excellent thermal conductivity, AIN has a small coefficient of thermal expansion, and has a coefficient of thermal expansion (3
, 6XIO-6/'C) (and the small dielectric constant causes crosstalk when forming a multilayer substrate.
It is also advantageous in that it is possible to reduce lk).

〔従来の技術〕[Conventional technology]

1/2N基板は半導体集積回路搭載用基板として着目さ
れているが、iNは融点が高く、基板の焼成は1800
’Cを越す高温で行われることから、導体線路の構成金
属としては高融点のタングステン(W)を用い、導体線
路の形成はWペーストをグリンシート上にスクリーン印
刷し、これを積層して一体化した後に焼成することによ
って行われている。
1/2N substrates are attracting attention as substrates for mounting semiconductor integrated circuits, but iN has a high melting point and the baking time of the substrate is 1800℃.
Since the process is carried out at a high temperature exceeding 100% Celsius, tungsten (W), which has a high melting point, is used as the constituent metal of the conductor line, and the conductor line is formed by screen printing W paste on a green sheet and laminating it to form an integral piece. This is done by baking after converting into

こ\で、多層基板の各層を構成する導体線路の電気的接
続は各層に設けたビア(Via)により行われている。
Here, the electrical connection of the conductor lines constituting each layer of the multilayer board is performed by vias provided in each layer.

すなわち、グリンシートの段階でプレスにより接続位置
を穴開けしてビアホール(ν1ahole)を作り、こ
れに導体線路の形成に使用したWペーストを充填して穴
埋めし、スクリーン印刷法により導体線路をパターン形
成した後、このグリンシートを積層して一体化し、この
状態で1800°Cにまで加熱することによって多層回
路基板が形成されている。
That is, at the green sheet stage, a via hole (ν1ahole) is created by punching a hole at the connection position using a press, and the hole is filled with the W paste used to form the conductor line, and the conductor line is patterned using a screen printing method. Thereafter, the green sheets are laminated and integrated, and heated to 1800°C in this state to form a multilayer circuit board.

然し、加熱に当たってWペーストを構成するW粉末は約
1000“Cから焼成収縮が始まるのに対してグリンシ
ートを構成するIN粉末は1600°Cまで全く収縮が
生ぜず、これ以上の温度で焼結助剤との反応が生じて液
相ができ焼成収縮が生ずるという違いがある。
However, when heated, the W powder that makes up the W paste begins to shrink at about 1000°C, whereas the IN powder that makes up the green sheet does not shrink at all until 1600°C, and cannot be sintered at temperatures higher than this. The difference is that a reaction with the auxiliary agent occurs, forming a liquid phase and causing shrinkage during firing.

そのために、焼成の過程でクラックを生じ、基板とビア
との密着力が低下して導通不良の原因となっている。
As a result, cracks occur during the firing process, which reduces the adhesion between the substrate and the via, causing poor conductivity.

この対策として、Wペーストの中に5%以上のAj2N
粉末を加えることにより、焼成過程での収縮率の差を緩
和し、密着力を向上する方法がある。
As a countermeasure for this, 5% or more of Aj2N is added to the W paste.
There is a method of adding powder to alleviate the difference in shrinkage rate during the firing process and improve adhesion.

然し、この方法ではビアの抵抗値が上昇してしまい、特
性の良い多層回路基板が形成できないと云う問題がある
However, this method has the problem that the resistance value of the via increases, making it impossible to form a multilayer circuit board with good characteristics.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上記したように11多層回路基板の導体線路の構成材
料としてWが使われているが、Anの焼成収縮開始温度
とWの焼成収縮開始温度とが約400℃異なるためにビ
アにクラックを生じ、導通不良の原因となっていること
が問題で、この解決が課題である。
As mentioned above, W is used as a constituent material for the conductor lines of the 11 multilayer circuit board, but cracks occur in vias because the firing shrinkage start temperature of An and the firing shrinkage start temperature of W differ by about 400°C. The problem is that it causes poor conduction, and the challenge is to solve this problem.

〔課題を解決するだめの手段] 上記の課題はAJ2Nグリンシートに設けたビアホール
の内壁にAINを添加したWペーストを塗布して乾燥し
た後、このビアホールにWペーストを充填し、非酸化性
雰囲気中で焼成することを特徴としてAIN基板のビア
形成方法を構成することにより解決することができる。
[Means to Solve the Problem] The above problem is solved by applying W paste containing AIN to the inner wall of the via hole provided in the AJ2N green sheet, drying it, filling the via hole with W paste, and placing it in a non-oxidizing atmosphere. This problem can be solved by configuring the via formation method for the AIN substrate so that the via formation method is characterized by firing inside the AIN substrate.

〔作用〕[Effect]

本発明はビアホールにAl2N混入wベーストヲそのま
\充填するのではなく、第1図に示すように、Aj2N
グリンシート1のビアホール2の内面にI<  An混
入Wペースト3を被覆して後、この中にWペースト4を
充填し、焼成することによって問題を解決するものであ
る。
In the present invention, instead of directly filling the via hole with Al2N mixed base, as shown in FIG.
The problem is solved by coating the inner surface of the via hole 2 of the green sheet 1 with the W paste 3 containing I<An, and then filling the W paste 4 therein and firing it.

このようにするとiNとWとの焼成収縮の影響が緩和さ
れ、また低抵抗のビアの形成が可能になる。
In this way, the influence of firing shrinkage of iN and W is alleviated, and it becomes possible to form a via with low resistance.

こ\で、問題は穴径が200μm程度と小さいビアホー
ルの内面に如何にして薄< An混入Wペーストを被覆
できるかであるが、これは低粘度に粘度調節したIN混
入Wペーストを真空吸引することにより塗布することが
できる。
The problem here is how to coat the inner surface of a via hole with a small diameter of about 200 μm with a thin layer of W paste mixed with An, but this is done by vacuum suctioning the W paste mixed with IN whose viscosity has been adjusted to a low viscosity. It can be applied by

第2図は真空吸引法を説明する断面図であって、表面に
多数の穴5の開いた減圧容器6の上に多孔質の吸水紙7
を置き、この上にAnグリンシート1と、このビアホー
ル2に正確に位置合わせしたマスク8を置き、このマス
クの上に低粘度のA1N混入Wペーストを供給する。
FIG. 2 is a sectional view illustrating the vacuum suction method, in which a porous water-absorbing paper 7 is placed on a vacuum container 6 with many holes 5 on its surface.
The An green sheet 1 and the mask 8 accurately aligned with the via hole 2 are placed thereon, and a low viscosity AlN-containing W paste is supplied onto this mask.

そしてスキージにより塗布した後、排気系を動作させる
と、吸水紙7を通して減圧が行われる結果、Al2N混
入Wペーストはビアホール2に吸引されて内壁に付着す
る。
After application with a squeegee, when the exhaust system is operated, the pressure is reduced through the water-absorbing paper 7, and as a result, the Al2N-mixed W paste is sucked into the via hole 2 and adheres to the inner wall.

本発明はこのようにしてビアホール2の内面にiN混入
Wペーストの塗布を行い、乾燥した後、従来のようにW
ペーストを充填することによりビアを形成するものであ
る。
In the present invention, the iN-containing W paste is applied to the inner surface of the via hole 2 in this manner, and after drying, the W paste is applied as in the conventional method.
Vias are formed by filling them with paste.

〔実施例〕〔Example〕

実施例:    第2表 第2表に示す組成のグリンシート(密度1.70g/c
m3+厚さ250 μm)をドクタブレード法で形成し
、このグリンシートを90mm角に打ち抜き、パンチで
直径が200μmのビアホールを362個形成した。
Example: Green sheet with the composition shown in Table 2 (density 1.70 g/c
m3+thickness 250 μm) was formed using a doctor blade method, this green sheet was punched into a 90 mm square, and 362 via holes each having a diameter of 200 μm were formed using a punch.

次に、第3表に示す組成のAβNβN添加−ペースト度
3000ボイズ)にテレピネオールを添加し、粘度を5
00ボイズにしてビアホールの内面にペーストの塗布を
行い、70°Cで15分に亙って乾燥した。
Next, terpineol was added to the composition shown in Table 3 (AβNβN addition-paste degree 3000 voids), and the viscosity was reduced to 5.
The paste was applied to the inner surface of the via hole at a void of 0.00, and dried at 70°C for 15 minutes.

第3表 次に、第4表に示す組成のWペースト(粘度3000ボ
イズ)を従来のように印刷してビアホールの充填と導体
線路の印刷を行い、70°Cで15分に亙って乾燥した
Table 3 Next, W paste (viscosity 3000 voids) having the composition shown in Table 4 was printed in the conventional manner to fill via holes and print conductor lines, and then dried at 70°C for 15 minutes. did.

第4表 このグリンシート6枚を一組として積層し、50MPa
の圧力で加圧して一体化した後、N2気流中で1000
“Cにまで50°C/時の昇温速度で加熱して脱脂を行
い、その後、1800°C930時間の焼成を行って多
層基板を形成した。
Table 4 Six of these green sheets are laminated as a set, and the pressure is 50MPa.
After pressurizing and integrating at a pressure of 1,000 yen in a N2 stream,
Degreasing was performed by heating to 50° C. at a heating rate of 50° C./hour, and then baking was performed at 1800° C. for 930 hours to form a multilayer substrate.

そして、測定の結果、ビアの体積抵抗率は35μΩcm
であり、従来のWペースト使用の場合(約30μΩcm
)にくらべると多少高いが基板−ビア間にはクラックは
存在しなかった。
As a result of measurement, the volume resistivity of the via was 35 μΩcm.
When using conventional W paste (approximately 30μΩcm
), but there were no cracks between the substrate and the via.

比較例1: 実施例1と同様にしてグリンシートを作り、362個の
ビアホールを打ち抜いた。
Comparative Example 1: A green sheet was made in the same manner as in Example 1, and 362 via holes were punched out.

このグリンシートのビアホールに第4表に示すWペース
ト(粘度3000ボイズ)の充填を行い、70°Cで1
5分乾燥した。
The via holes of this green sheet were filled with W paste (viscosity 3000 voids) shown in Table 4, and heated at 70°C for 1 hour.
Dry for 5 minutes.

このグリンシート6枚を一組として積層し、50MPa
の圧力で加圧して一体化した後、N2気流中で1000
℃にまで50°C/時の昇温速度で加熱して脱脂した後
、1800″C930時間の焼成を行って多層基板を形
成した。
Six of these green sheets were laminated as a set, and the pressure was 50MPa.
After pressurizing and integrating at a pressure of 1,000 yen in a N2 stream,
After degreasing by heating at a temperature increase rate of 50° C./hour to 1,800° C., a multilayer substrate was formed by firing at 1800° C. for 930 hours.

そして、測定の結果、ビアの体積抵抗率は30μΩcm
と低いが、基板−ビア間にはクラックが生じていた。
As a result of measurement, the volume resistivity of the via was 30 μΩcm.
However, cracks were observed between the substrate and the via.

実施例2; 実施例1と同様にしてグリンシートを作り、362個の
ビアホールを打ち抜いた。
Example 2: A green sheet was made in the same manner as in Example 1, and 362 via holes were punched out.

このグリンシートのビアホールに第3表に示すiN添加
Wペースト(粘度2500ポイズ)の充填を行い、70
°Cで15分乾燥した。
The via holes of this green sheet were filled with iN-added W paste (viscosity 2500 poise) shown in Table 3, and
Dry at °C for 15 minutes.

その後、実施例と同様に6枚を一組として積層脱脂、焼
成を行い多層基板を形成した。
Thereafter, in the same manner as in the example, a set of six sheets was laminated, degreased, and fired to form a multilayer board.

そして、測定の結果、ビアの体積抵抗率は80μΩcm
と高かったが、基板−ビア間にはクランクは生じていな
かった。
As a result of measurement, the volume resistivity of the via was 80 μΩcm.
However, no crank occurred between the board and the via.

〔発明の効果〕〔Effect of the invention〕

本発明の実施によりビアの体積抵抗率が低く、また基板
−ビア間にクランク発生のないAIN多層回路基板を製
造することができる。
By carrying out the present invention, it is possible to manufacture an AIN multilayer circuit board in which the volume resistivity of the vias is low and there is no cranking between the substrate and the vias.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理を示す断面図、 第2図は真空吸引法を説明する断面図、である。 図において、 lはAnグリンシート、 2はビアホール、 3はAI!、N混合Wペースト、 4はWペースト、    5は穴、 6は減圧容器、 1 2 である。 ) 3 FIG. 1 is a sectional view showing the principle of the present invention, FIG. 2 is a sectional view illustrating the vacuum suction method. In the figure, l is An green sheet, 2 is a beer hall, 3 is AI! , N mixed W paste, 4 is W paste, 5 is hole, 6 is a vacuum container; 1 2 It is. ) 3

Claims (1)

【特許請求の範囲】[Claims]  窒化アルミニウムグリンシートに設けたビアホールの
内壁に窒化アルミニウムを添加したタングステンペース
トを塗布して乾燥した後、該ビアホールにタングステン
ペーストを充填し、非酸化性雰囲気中で焼成することを
特徴とする窒化アルミニウム基板のビア形成方法。
Aluminum nitride characterized by applying tungsten paste added with aluminum nitride to the inner wall of a via hole provided in an aluminum nitride green sheet, drying it, filling the via hole with tungsten paste, and firing in a non-oxidizing atmosphere. How to form vias on a board.
JP25806589A 1989-10-03 1989-10-03 Via forming method for aluminum nitride substrate Expired - Fee Related JP2699581B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25806589A JP2699581B2 (en) 1989-10-03 1989-10-03 Via forming method for aluminum nitride substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25806589A JP2699581B2 (en) 1989-10-03 1989-10-03 Via forming method for aluminum nitride substrate

Publications (2)

Publication Number Publication Date
JPH03120791A true JPH03120791A (en) 1991-05-22
JP2699581B2 JP2699581B2 (en) 1998-01-19

Family

ID=17315042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25806589A Expired - Fee Related JP2699581B2 (en) 1989-10-03 1989-10-03 Via forming method for aluminum nitride substrate

Country Status (1)

Country Link
JP (1) JP2699581B2 (en)

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WO2005106973A1 (en) * 2004-04-27 2005-11-10 Kyocera Corporation Wiring board for light emitting element
JP2006041230A (en) * 2004-07-28 2006-02-09 Kyocera Corp WIRING BOARD FOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE
JP2006066409A (en) * 2004-07-28 2006-03-09 Kyocera Corp LIGHT EMITTING DEVICE WIRING BOARD, LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE WIRING BOARD MANUFACTURING METHOD
JP2006156447A (en) * 2004-11-25 2006-06-15 Kyocera Corp WIRING BOARD FOR LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND ITS MANUFACTURING METHOD
JP2007220764A (en) * 2006-02-15 2007-08-30 Murata Mfg Co Ltd Laminated ceramic electronic component and its manufacturing method
JP2008010605A (en) * 2006-06-29 2008-01-17 Murata Mfg Co Ltd Stacked ceramic electronic component and its manufacturing method
US7514791B2 (en) 2002-09-27 2009-04-07 Medtronic Minimed, Inc. High reliability multilayer circuit substrates
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US7514791B2 (en) 2002-09-27 2009-04-07 Medtronic Minimed, Inc. High reliability multilayer circuit substrates
US8003513B2 (en) 2002-09-27 2011-08-23 Medtronic Minimed, Inc. Multilayer circuit devices and manufacturing methods using electroplated sacrificial structures
US7781328B2 (en) 2002-09-27 2010-08-24 Medtronic Minimed, Inc. Multilayer substrate
US7659194B2 (en) 2002-09-27 2010-02-09 Medtronic Minimed, Inc. High reliability multilayer circuit substrates and methods for their formation
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