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JPH03120749A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPH03120749A
JPH03120749A JP1259202A JP25920289A JPH03120749A JP H03120749 A JPH03120749 A JP H03120749A JP 1259202 A JP1259202 A JP 1259202A JP 25920289 A JP25920289 A JP 25920289A JP H03120749 A JPH03120749 A JP H03120749A
Authority
JP
Japan
Prior art keywords
film substrate
semiconductor element
semiconductor
board
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1259202A
Other languages
Japanese (ja)
Other versions
JP2734684B2 (en
Inventor
Yutaka Makino
豊 牧野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1259202A priority Critical patent/JP2734684B2/en
Priority to KR1019900015305A priority patent/KR940003374B1/en
Publication of JPH03120749A publication Critical patent/JPH03120749A/en
Application granted granted Critical
Publication of JP2734684B2 publication Critical patent/JP2734684B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enhance density and to reduce in size a wiring circuit board, etc,. by mounting semiconductor devices on both side surfaces of a film board, connecting electrodes to lead patterns formed on both side surfaces of the board, and connecting them via through holes. CONSTITUTION:A semiconductor device package P is formed with lead patterns 20, 23 on both side surfaces of a film board 10, and semiconductor devices 30 are placed and connected at the centers of the patterns 20, 23 through bumps 70. The pattern 20 of the upper surface side is connected partly to a land 22 formed at the opposite side surface via a through hole 21 bored through the board 10 near the outer peripheral end. The remaining pattern 20 is connected to the pattern 23 of the opposite side surface via a similar through hole 21. The devices 30, 30 of both side surfaces of the board 10 and the central parts of the patterns 20, 23 are integrally sealed with sealing resin 50, and the hole 21 is also covered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体素子パッケージに関し、詳しくは、
IC,LSI等の半導体素子を配線回路基板等に実装す
る際に、配線接続や取り扱いを容易にしたり、半導体素
子を外部環境から保護したりすることを目的として、基
板に搭載した半導体素子を樹脂で封入しておく半導体素
子パッケージに関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor element package, and in detail,
When mounting semiconductor elements such as ICs and LSIs on printed circuit boards, etc., the semiconductor elements mounted on the board are coated with resin to facilitate wiring connections and handling, and to protect the semiconductor elements from the external environment. This relates to a semiconductor device package that is sealed in a semiconductor device package.

〔従来の技術〕[Conventional technology]

半導体素子パッケージは、極めて微小な半導体素子を、
配線回路等の外部回路上に実装するために用いるもので
ある。−船釣な半導体パッケージの構造としては、DI
P構造やフランドパツク構造あるいはチップキャリア構
造等、様々な構造のものが製造されている。
Semiconductor element packages carry extremely small semiconductor elements.
It is used for mounting on external circuits such as wiring circuits. -The structure of a semiconductor package that can be used on a boat is DI.
Various structures are manufactured, such as a P structure, a French pack structure, and a chip carrier structure.

第5図は、従来の半導体素子パンケージのうち、フィル
ムフラットバンク式と呼ばれるパッケージの構造を示し
ている。この半導体素子パッケージPにおいては、ポリ
イミド樹脂等からなるフィルム基板1の表面にCu等の
導体金属薄層からなるリードパターン2が形成され、リ
ードパターン2で囲まれたフィルム基板1中央部にハン
ダ等の手段で半導体素子3が搭載固定されている。半導
体素子3の各電極とリードパターン2はポンディングワ
イヤ4等で電気的に接続されている。フィルム基板1の
半導体素子3搭載部分はエポキシ樹脂等の封止樹脂5で
覆われている。フィルム基板1の外周ば封止樹脂5の外
に延長されており、各リードパターン2の外周端が、配
線回路基板8の配線回路8aにハンダ等の手段で接続さ
れることにより、電気的な接続がなされるとともに、機
械的にも半導体素子パッケージPの配線回路基板8への
搭載固定がなされている。
FIG. 5 shows the structure of a package called a film flat bank type among conventional semiconductor element package packages. In this semiconductor element package P, a lead pattern 2 made of a thin layer of conductive metal such as Cu is formed on the surface of a film substrate 1 made of polyimide resin, etc., and a solder etc. The semiconductor element 3 is mounted and fixed by the following means. Each electrode of the semiconductor element 3 and the lead pattern 2 are electrically connected by a bonding wire 4 or the like. The portion of the film substrate 1 on which the semiconductor element 3 is mounted is covered with a sealing resin 5 such as epoxy resin. The outer periphery of the film substrate 1 is extended outside the sealing resin 5, and the outer periphery end of each lead pattern 2 is connected to the wiring circuit 8a of the printed circuit board 8 by means such as soldering, thereby providing an electrical connection. At the same time as the connection is made, the semiconductor element package P is also mechanically mounted and fixed on the printed circuit board 8.

配線回路基板8に複数の半導体素子3を実装するには、
それぞれの半導体素子3を収容した半導体素子パッケー
ジPを平面的に一定の間隔をあけて並べた状態で、配線
回路基板8の配線回路8a上に接続搭載していた。この
ように、従来の半導体素子パッケージは、半導体素子を
フィルム基板の一面に搭載するのみであった。
In order to mount a plurality of semiconductor elements 3 on the printed circuit board 8,
Semiconductor element packages P containing respective semiconductor elements 3 were connected and mounted on the wiring circuit 8a of the wiring circuit board 8 in a state where they were lined up at regular intervals in a plane. In this manner, the conventional semiconductor device package only mounts the semiconductor device on one surface of a film substrate.

〔発明が解決しようとする課題] ところが、配線回路基板8の高密度化や小型化が進むに
つれ、配線回路基板8上に実装する半導体素子パッケー
ジPの小型化が要望されているが、従来の半導体素子パ
ッケージPは、以下の理由でその小型化が困難なため、
実装面に占める面積が比較的広く、この広い占有面積の
ために、配線回路基板8全体の小型化を阻害していると
いう問題があった。
[Problems to be Solved by the Invention] However, as the printed circuit board 8 becomes more dense and smaller, there is a demand for a smaller semiconductor element package P to be mounted on the printed circuit board 8. It is difficult to miniaturize the semiconductor element package P for the following reasons.
There is a problem in that the area occupied on the mounting surface is relatively large, and this large occupied area hinders miniaturization of the printed circuit board 8 as a whole.

すなわち、半導体素子パッケージPに搭載する半導体素
子3自体は、高集積化あるいは小型化が図られているの
に対し、半導体素子パッケージPは、半導体素子3とリ
ードパターン2の接続およびリードパターン2と配線回
路8aの接続を可能にするために、一定以上の大きさが
どうしても必要であり、半導体素子パッケージPの平面
的な寸法を小さくすることには限界があったのである。
In other words, while the semiconductor element 3 itself mounted on the semiconductor element package P is designed to be highly integrated or miniaturized, the semiconductor element package P is designed to provide connections between the semiconductor element 3 and the lead pattern 2, and the connection between the semiconductor element 3 and the lead pattern 2. In order to enable connection of the wiring circuit 8a, a certain size or more is absolutely necessary, and there is a limit to reducing the planar dimensions of the semiconductor element package P.

配線回路基板8に複数の半導体素子パッケージPを実装
する場合には、さらに、それぞれの半導体素子パッケー
ジP毎に充分な間隔をあけて配線回路8a上に配置しな
いと、リードパターン2と配線回路8aとの接続作業が
できないために、余計に大きなスペースが必要になり、
配線回路基板8全体の小型化を大きく阻害していた。
When mounting a plurality of semiconductor element packages P on the printed circuit board 8, the lead pattern 2 and the printed circuit 8a must be placed on the printed circuit 8a with sufficient spacing between each semiconductor chip package P. Since it is not possible to connect with
This greatly hinders miniaturization of the printed circuit board 8 as a whole.

そこで、この発明は、配線回路基板等に複数の半導体素
子パッケージを実装する際の実装効率を高めて、配線回
路基板等の高密度化および小型化を図ることのできる半
導体素子パッケージを提供することにある。
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor element package that can increase the mounting efficiency when mounting a plurality of semiconductor element packages on a wired circuit board, etc., and achieve higher density and smaller size of the wired circuit board, etc. It is in.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決する、この発明の半導体素子パッケージ
は、フィルム基板の両面にそれぞれ半導体素子が搭載さ
れて、これら半導体素子の各電極が、フィルム基板の両
面にそれぞれ形成されたリードパターンに接続され、少
なくとも一部のり−ドバクーンが、フィルム基板を貫通
ずるスルーホールで、フィルム基板の一方の面から他方
の面へと接続されているとともに、フィルム基板両面の
各半導体素子が封止樹脂で一体的に封入されている。
A semiconductor element package of the present invention that solves the above problems includes semiconductor elements mounted on both sides of a film substrate, and electrodes of these semiconductor elements connected to lead patterns formed on both sides of the film substrate, respectively. At least a portion of the adhesive tape is connected from one side of the film substrate to the other through a through hole passing through the film substrate, and each semiconductor element on both sides of the film substrate is integrally sealed with a sealing resin. It is enclosed.

フィルム基板は、ポリイミド樹脂等の合成樹脂フィルム
材Mからなり、通常のフィルムフランI□バック式パッ
ケージ等で用いられているのものと同様のものである。
The film substrate is made of a synthetic resin film material M such as polyimide resin, and is similar to that used in ordinary film flan I□ back type packages.

半導体素子としては、通常のIC1L S Iあるいは
その他の電子素子が自由に使用できる。フィルム基板の
両面に搭載される半導体素子の組み合わせ方も任意であ
るが、例えば、マイコンチップとメモリをフィルム基板
の両面に搭載すること等である。フィルム基板の両面に
半導体素子を搭載する手段は、通常のパッケージ構造と
同様に、ハンダハンプや接着等の手段が採用できる。
As the semiconductor element, an ordinary IC1LSI or other electronic element can be freely used. Although the combination of semiconductor elements mounted on both sides of the film substrate is arbitrary, for example, a microcomputer chip and a memory may be mounted on both sides of the film substrate. As for the means for mounting semiconductor elements on both sides of the film substrate, means such as solder humping or adhesion can be employed as in the case of a normal package structure.

リードパターンは、Cu等の通常の導体金属層からなり
、エツチング等の通常の回路形成手段でパターン形成さ
れている。なお、従来の半導体素子パッケージでは、フ
ィルム基板の片面のみに半導体素子が搭載されているの
で、リードパターンも、半導体素子が搭載された面のみ
に形成しておけばよいが、この発明では、フィルム基板
の両面に半導体素子を搭載しているので、リードパター
ンもフィルム基板の両面に形成される。
The lead pattern is made of an ordinary conductive metal layer such as Cu, and is patterned by ordinary circuit forming means such as etching. Note that in conventional semiconductor element packages, the semiconductor element is mounted on only one side of the film substrate, so the lead pattern only needs to be formed on the side on which the semiconductor element is mounted. Since semiconductor elements are mounted on both sides of the substrate, lead patterns are also formed on both sides of the film substrate.

リードパターンと半導体素子を電気的に接続する手段は
、ワイヤボンディング接続やバンブ接続等の通常の接続
手段が採用できる。
As a means for electrically connecting the lead pattern and the semiconductor element, ordinary connection means such as wire bonding connection and bump connection can be used.

リードパターンは、中央側で半導体素子の電極と接続さ
れるとともに、外周側では、配線回路基板の配線回路等
の外部回路に接続できるようになっている。リードパタ
ーンのうち、外部回路に接触する側の面では、従来の半
導体素子パッケージと同様のパターン構造で形成してお
けばよいが、外部回路に接触しない反対側の面に形成さ
れたリードパターンは、フィルム基板を貫通するスルー
ホールを経て、外部回路との接触面に形成されたランド
部へと接続しておき、このランド部を外部回路に対面さ
せて接続するようにしている。この、スルーホールやラ
ンド部の具体的な構造や形成手段は、通常の回路形成と
同様の構造および手段が適用される。
The lead pattern is connected to the electrode of the semiconductor element on the center side, and can be connected to an external circuit such as a wiring circuit of a printed circuit board on the outer peripheral side. The side of the lead pattern that comes into contact with the external circuit can be formed with the same pattern structure as that of conventional semiconductor device packages, but the lead pattern formed on the opposite side that does not come into contact with the external circuit is It is connected to a land portion formed on a contact surface with an external circuit through a through hole penetrating the film substrate, and this land portion is connected to face the external circuit. As for the specific structure and formation means of the through-holes and land portions, the same structure and means as for ordinary circuit formation are applied.

フィルム基板の両面に搭載された半導体素子の電極同士
を配線接続する場合、それぞれのリードパターンを経て
外部回路に一旦接続した後、外部回路上で互いに接続す
るようにしてもよいが、フィルム基板上で、フィルム基
板を貫通するスルーホールを介して表裏のリードパター
ンを接続するようにすることもできる。
When wiring the electrodes of semiconductor elements mounted on both sides of a film substrate, it is possible to connect them to an external circuit through each lead pattern and then connect them to each other on the external circuit. It is also possible to connect the lead patterns on the front and back sides via a through hole penetrating the film substrate.

フィルム基板の両面に搭載された半導体素子およびリー
ドパターンの大部分は、封止樹脂によって一体的に封入
されている。封止樹脂としては、エポキシ樹脂等、通常
の半導体素子パッケージと同様の樹脂材料が用いられ、
具体的な封止構造や封止手段も、通常のパッケージ技術
が適用できる〔作  用〕 1枚のフィルム基板の両面にそれぞれ半導体素子を搭載
するようにしておけば、従来と同じ平面寸法の半導体素
子パンケージに、2倍個数の半導体素子を搭載すること
ができ、半導体素子の搭載密度を2倍にすることができ
る。
Most of the semiconductor elements and lead patterns mounted on both sides of the film substrate are integrally encapsulated with a sealing resin. As the sealing resin, the same resin materials as those used in ordinary semiconductor element packages, such as epoxy resin, are used.
Ordinary packaging technology can be applied to the specific sealing structure and sealing means [Function] If semiconductor elements are mounted on both sides of a single film substrate, semiconductors with the same planar dimensions as conventional ones can be used. Double the number of semiconductor devices can be mounted on the device pancage, and the mounting density of semiconductor devices can be doubled.

フィルム基板の両面に半導体素子を搭載すると、それぞ
れの面に形成されたリードパターンを、配線回路基板等
の外部回路に接続しなければならないが、この発明では
、リードパターンが、フィルム基板ヲ貫通するスルーホ
ールで、フィルム基板の一方の面から他方の面へと接続
されているので、両面のリードパターンを、何れも、同
じ外部回路面に接続することが可能である。また、フィ
ルム基板の両面に搭載された半導体素子の電極同士を接
続する場合にも、フィルム基板゛を貫通して形成された
スルーホールで両面のリードパターン同士を接続すれば
よい。
When semiconductor elements are mounted on both sides of a film substrate, lead patterns formed on each side must be connected to an external circuit such as a printed circuit board, but in this invention, the lead patterns penetrate through the film substrate. Since one side of the film substrate is connected to the other side with a through hole, it is possible to connect the lead patterns on both sides to the same external circuit side. Furthermore, when connecting electrodes of semiconductor elements mounted on both sides of a film substrate, the lead patterns on both sides may be connected to each other through through holes formed through the film substrate.

2個の半導体素子に対して、同じフィルム基板および封
止樹脂が用いられるので、別々の半導体素子パッケージ
を用いるのに比べて、材料コストおよび製造コストが半
減され、製造時間も短くて済む。
Since the same film substrate and sealing resin are used for the two semiconductor devices, the material cost and manufacturing cost are halved and the manufacturing time can be shortened, compared to using separate semiconductor device packages.

〔実 施 例〕〔Example〕

ついで、この発明を、実施例を示す図面を参照しながら
、以下に詳しく説明する。
Next, the present invention will be explained in detail below with reference to the drawings showing examples.

第1図は、半導体素子パッケージを配線回路基板に搭載
した状態を示している。半導体素子パッケージPは、フ
ィルム基板10の両面にリードパターン20.23が形
成され、各リードパターン20.23の中央部分には、
それぞれバンブ70を介して半導体素子30が搭載接続
されている。
FIG. 1 shows a semiconductor element package mounted on a printed circuit board. In the semiconductor element package P, lead patterns 20.23 are formed on both sides of the film substrate 10, and in the center of each lead pattern 20.23,
Semiconductor elements 30 are mounted and connected via bumps 70, respectively.

上面側のリードパターン20は、一部のリードパターン
20が、外周端近くで、フィルム基板10を貫通するス
ルーホール21を経て、反対面側に形成されたランド部
22に接続されている。また、残りのリードパターン2
0は、前記同様のスルーホール21を介して、反対面側
のリードパターン23に接続されている。フィルム基板
10両面の半導体素子30.30およびリードパターン
20.23の中央部分は封止樹脂50で一体的に封入さ
れている。封止樹脂50は、前記した上下のリードパタ
ーン20.23をつなぐスルーホール21も覆っている
。封止樹脂50の外方に延びたフィルム基板10および
リードパターン20.23は、図中下方側に折曲された
後、再び水平方向に折曲されており、このフィルム基板
lOの外周の足状部11を、配線回路基板80に搭載接
続するようになっている。
A portion of the lead pattern 20 on the upper surface side is connected to a land portion 22 formed on the opposite surface side through a through hole 21 penetrating the film substrate 10 near the outer peripheral edge. Also, the remaining lead pattern 2
0 is connected to a lead pattern 23 on the opposite side through a through hole 21 similar to the above. The central portions of the semiconductor elements 30.30 and lead patterns 20.23 on both sides of the film substrate 10 are integrally sealed with a sealing resin 50. The sealing resin 50 also covers the through hole 21 that connects the upper and lower lead patterns 20 and 23 described above. The film substrate 10 and the lead patterns 20.23 extending outward from the sealing resin 50 are bent downward in the figure and then horizontally again, and the legs on the outer periphery of the film substrate 10 The shaped portion 11 is mounted and connected to a printed circuit board 80.

配線回路基板80は、ガラスエポキシ樹脂等からなる絶
縁層810表面に、Cu等の導体金属層からなる配線回
路82がパターン形成されている。この配線回路82の
上に半導体素子パンケージPのフィルム基板10の足状
部11を載せて、足0 状部11裏面のリードパターン23もしくはランド部2
2を、ハンダ接続等の手段で配線回路82に接続する。
In the printed circuit board 80, a printed circuit 82 made of a conductive metal layer such as Cu is patterned on the surface of an insulating layer 810 made of glass epoxy resin or the like. The foot portion 11 of the film substrate 10 of the semiconductor element pancage P is placed on this wiring circuit 82, and the lead pattern 23 or the land portion 2 on the back side of the foot portion 11 is placed on top of the wiring circuit 82.
2 is connected to the wiring circuit 82 by means such as soldering.

第2図は、半導体素子パッケージPの下面側のリードパ
ターン23の形状の一例を示しており、各リードパター
ン23は、半導体素子30の外縁のそれぞれの電極形成
位置から、フィルム基板10の四方に突出形成された足
状部11の外周端まで形成されている。足状部11の外
周端には、リードパターン23の間に、反対面側のリー
ドパターン20にスルーホール21で接続されているラ
ンド部22が形成されている。リードパターン23の途
中には、反対面側のリードパターン20との接続用スル
ーホール21が設けられている。
FIG. 2 shows an example of the shape of the lead patterns 23 on the lower surface side of the semiconductor element package P, and each lead pattern 23 extends from each electrode formation position on the outer edge of the semiconductor element 30 to the four sides of the film substrate 10. It is formed up to the outer peripheral end of the protruding foot-shaped portion 11. A land portion 22 is formed between the lead patterns 23 at the outer peripheral end of the leg portion 11 and is connected to the lead pattern 20 on the opposite side through a through hole 21 . A through hole 21 for connection with the lead pattern 20 on the opposite side is provided in the middle of the lead pattern 23.

第3図は、上記のようなリードパターン構造を、フィル
ム基板10の上面側から見た状態を示している。上面側
のリードパターン20ば、一部のリードパターン20に
ついては、半導体素子30の外縁のそれぞれの電極形成
位置から足状部11の外周近くまで形成され、ここでス
ルーホール21を経て反対面側のランド部22へとつな
がっている。残りのリードパターン20については、半
導体素子30の電極形成位置からすこし離れた位置でス
ルーホール21を経て反対面側のリードパターン23に
つながっている。
FIG. 3 shows the lead pattern structure as described above, viewed from the top side of the film substrate 10. Some of the lead patterns 20 on the upper surface side are formed from the respective electrode formation positions on the outer edge of the semiconductor element 30 to near the outer periphery of the foot-shaped portion 11, and then pass through the through holes 21 to the opposite surface. It is connected to the land portion 22 of. The remaining lead patterns 20 are connected to the lead patterns 23 on the opposite side through through holes 21 at positions slightly away from the electrode formation positions of the semiconductor element 30.

以上に説明したように、この発明にかかる半導体素子パ
ッケージPは、基本的には通常の半導体素子パッケージ
製造技術をそのまま利用して製造することができる。
As explained above, the semiconductor element package P according to the present invention can basically be manufactured using ordinary semiconductor element package manufacturing techniques as they are.

第4図は、フィルム基板10に半導体素子30を搭載固
定するのに好ましい方法を示している。
FIG. 4 shows a preferred method for mounting and fixing the semiconductor element 30 on the film substrate 10.

半導体素子30をフィルム基板10のリードパターン2
0.’23にバンプ接続する場合、半導体素子30の電
極とリードパターン20.23をバンプ70を介して加
圧および加熱しなりればならない。そこで、フィルム基
板10の両面に搭載する半導体素子30の寸法に大小を
つけておき、まず、小さいほうの半導体素子30を、通
常の方法で、ハンプ70を間に挟んでフィルム基板10
のリードパターン23に加圧および加熱して接続面1 2 定する。つぎに、大きいほうの半導体素子30を搭載接
続する際には、第4図に示すように、小さいほうの半導
体素子30が丁度入る大きさの凹所91が形成された受
台90を用い、小さいほうの半導体素子30よりも外周
部分のフィルム基板10に受台90の上面が当接するよ
うな状態で、フィルム基板10の上面側のリードパター
ン20にバンブ70を介して大きいほうの半導体素子3
0を載せ、受台90との間で加圧しながら加熱して接続
固定する。こうずれば、先に搭載接続した半導体素子3
0が邪魔にならずに、両面の半導体素子30を何れも確
実に搭載接続することができる〔発明の効果〕 以上に述べた、この発明の半導体素子パッケージは、1
枚のフィルム基板の両面に半導体素子が搭載され、1個
の半導体素子パッケージに少なくとも2個の半導体素子
が封入されていることになるので、従来の半導体素子パ
ッケージに比べて、同じの面積の外部回路上に、2倍個
数以上の半導体素子を実装することが可能になり、実装
密度の大幅な向上が実現できる。特に、個々の半導体素
子パッケージ毎に外部回路を配線形成したり、半導体素
子パッケージの搭載接続作業を行う必要がないので、配
線回路基板等の配線回路形成が簡単になり、半導体素子
パッケージの搭載接続作業の手間も半減する。
The semiconductor element 30 is connected to the lead pattern 2 of the film substrate 10.
0. 23, the electrodes of the semiconductor element 30 and the lead patterns 20.23 must be pressed and heated via the bumps 70. Therefore, the sizes of the semiconductor elements 30 to be mounted on both sides of the film substrate 10 are determined, and first, the smaller semiconductor element 30 is placed on the film substrate 10 with the hump 70 in between in the usual manner.
The connection surface 1 2 is fixed by applying pressure and heating to the lead pattern 23 . Next, when mounting and connecting the larger semiconductor element 30, as shown in FIG. The larger semiconductor element 3 is attached to the lead pattern 20 on the upper surface side of the film substrate 10 via the bump 70 in such a state that the upper surface of the pedestal 90 is in contact with the outer peripheral portion of the film substrate 10 than the smaller semiconductor element 30.
0 is placed and heated while applying pressure between it and the pedestal 90 to connect and fix it. If this happens, the semiconductor element 3 that was mounted and connected first
[Effects of the Invention] The semiconductor element package of the present invention described above has the following features: 1.
Semiconductor elements are mounted on both sides of a single film substrate, and at least two semiconductor elements are encapsulated in one semiconductor element package. It becomes possible to mount twice or more the number of semiconductor elements on a circuit, and a significant improvement in packaging density can be achieved. In particular, since there is no need to form wiring for external circuits for each individual semiconductor element package or to perform mounting and connection work for semiconductor element packages, it is easier to form wiring circuits such as wired circuit boards, and to connect mounting and connecting semiconductor element packages. The work effort is also halved.

半導体素子パッケージ内でフィルム基板両面のリードパ
ターンをスルーボール接続することによって、半導体素
子同士の配線接続が行えるので、いちいち外部回路上で
半導体素子同士を配線接続するのに比べ、配線距離が格
段に短くなり、接続も確実に行われるので、信号伝達の
信頼性や安定性等の配線接続性能が大幅に向上する。
Wiring connections between semiconductor devices can be made by through-ball connecting the lead patterns on both sides of the film substrate within the semiconductor device package, so the wiring distance can be significantly reduced compared to connecting semiconductor devices one by one on an external circuit. Since the wires are shorter and connections are made more reliably, wiring connection performance such as reliability and stability of signal transmission is greatly improved.

複数個の半導体素子で、フィルム基板や封止樹脂等が共
用されることになるので、材料コスI・が半減するとと
もに、製造時間も短くなり、全体の製造コストを大きく
削減できる。
Since the film substrate, sealing resin, etc. are shared by a plurality of semiconductor elements, the material cost I. is halved, the manufacturing time is shortened, and the overall manufacturing cost can be greatly reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の実施例を示す実装状態の断3 4 面図、第2図は底面側のリードパターンを示す平面図、
第3図は上面側のリードパターンを示す平面図、第4図
は製造方法の一例を示す概略断面図、第5図は従来例の
実装状態を示す断面図である10・・・フィルム基板 
20・・・リードパターン21・・・スルーホール 2
2・・・ランド部 30・・・半導体素子 50・・・
封止樹脂 70・・・バンプ 80・・・配線回路基板
 82・・・配線回路 P・・・半導体素子パッケージ
FIG. 1 is a cross-sectional view of a mounted state showing an embodiment of the present invention, and FIG. 2 is a plan view showing a lead pattern on the bottom side.
3 is a plan view showing the lead pattern on the upper surface side, FIG. 4 is a schematic sectional view showing an example of the manufacturing method, and FIG. 5 is a sectional view showing the mounting state of a conventional example.
20...Lead pattern 21...Through hole 2
2... Land portion 30... Semiconductor element 50...
Sealing resin 70...Bump 80...Wiring circuit board 82...Wiring circuit P...Semiconductor element package.

Claims (1)

【特許請求の範囲】[Claims] 1、フィルム基板の両面にそれぞれ半導体素子が搭載さ
れて、これら半導体素子の各電極が、フィルム基板の両
面にそれぞれ形成されたリードパターンに接続され、少
なくとも一部のリードパターンが、フィルム基板を貫通
するスルーホールで、フィルム基板の一方の面から他方
の面へと接続されているとともに、フィルム基板両面の
各半導体素子が封止樹脂で一体的に封入されている半導
体素子パッケージ。
1. Semiconductor elements are mounted on both sides of the film substrate, each electrode of these semiconductor elements is connected to a lead pattern formed on both sides of the film substrate, and at least some of the lead patterns penetrate through the film substrate. A semiconductor device package in which one side of a film substrate is connected to the other through a through hole, and each semiconductor device on both sides of the film substrate is integrally encapsulated with sealing resin.
JP1259202A 1989-10-03 1989-10-03 Semiconductor device package Expired - Fee Related JP2734684B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1259202A JP2734684B2 (en) 1989-10-03 1989-10-03 Semiconductor device package
KR1019900015305A KR940003374B1 (en) 1989-10-03 1990-09-26 Package of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1259202A JP2734684B2 (en) 1989-10-03 1989-10-03 Semiconductor device package

Publications (2)

Publication Number Publication Date
JPH03120749A true JPH03120749A (en) 1991-05-22
JP2734684B2 JP2734684B2 (en) 1998-04-02

Family

ID=17330806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1259202A Expired - Fee Related JP2734684B2 (en) 1989-10-03 1989-10-03 Semiconductor device package

Country Status (2)

Country Link
JP (1) JP2734684B2 (en)
KR (1) KR940003374B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019433A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor device and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019433A (en) * 2004-06-30 2006-01-19 Nec Electronics Corp Semiconductor device and manufacturing method thereof
US7795721B2 (en) 2004-06-30 2010-09-14 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
US8193033B2 (en) 2004-06-30 2012-06-05 Renesas Electronics Corporation Semiconductor device having a sealing resin and method of manufacturing the same
US8207605B2 (en) 2004-06-30 2012-06-26 Renesas Electronics Corporation Semiconductor device having a sealing resin and method of manufacturing the same
US8541874B2 (en) 2004-06-30 2013-09-24 Renesas Electronics Corporation Semiconductor device
US8890305B2 (en) 2004-06-30 2014-11-18 Renesas Electronics Corporation Semiconductor device
US9324699B2 (en) 2004-06-30 2016-04-26 Renesas Electonics Corporation Semiconductor device
US10672750B2 (en) 2004-06-30 2020-06-02 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date
KR940003374B1 (en) 1994-04-21
KR910008828A (en) 1991-05-31
JP2734684B2 (en) 1998-04-02

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