JPH0311797A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0311797A JPH0311797A JP1146210A JP14621089A JPH0311797A JP H0311797 A JPH0311797 A JP H0311797A JP 1146210 A JP1146210 A JP 1146210A JP 14621089 A JP14621089 A JP 14621089A JP H0311797 A JPH0311797 A JP H0311797A
- Authority
- JP
- Japan
- Prior art keywords
- case
- holes
- heat dissipation
- dissipation plate
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 238000003780 insertion Methods 0.000 abstract description 7
- 230000037431 insertion Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 230000002146 bilateral effect Effects 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 240000008168 Ficus benjamina Species 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の放熱板上にケースを取付ける
位置合せ機構の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in an alignment mechanism for attaching a case onto a heat sink of a semiconductor device.
第２図ａは従来のこの種の半導体装置を示す斜視図、第
２図すは第２図ａの半導体装置に接着するケースを示す
斜視図、第２図Ｃは第２図ａの上面図である。第２図に
おいて、１は放熱板、２はこの放熱板１に取付けられた
絶縁基板、３ａ、 ３ｂ、 ３ｃはこの絶縁基板２上に
形成された金属パターン。FIG. 2a is a perspective view showing a conventional semiconductor device of this type, FIG. 2 is a perspective view showing a case bonded to the semiconductor device of FIG. 2a, and FIG. 2C is a top view of FIG. 2a. It is. In FIG. 2, 1 is a heat sink, 2 is an insulating substrate attached to the heat sink 1, and 3a, 3b, and 3c are metal patterns formed on the insulating substrate 2.
４は金属パターン３ｂ上に取付けられた半導体素子、５
は半導体素子４と金属パターン３ａ、３ｃを接続する金
属細線、６はケース、７はこのケースと一体化された電
極、８ａ、 ８ｂは半導体装置を放熱フィン（図示省略
）に取付けるための穴、９ａ〜９ｄはケース６の下面に
設けられた突起、ｌ０ａ−１０ｄは上記放熱板１に設け
られ上記ケース６の突起９ａ〜９ｄと合致してこれを通
すための穴である。4 is a semiconductor element mounted on the metal pattern 3b, 5
6 is a case, 7 is an electrode integrated with the case, 8a and 8b are holes for attaching the semiconductor device to a heat dissipation fin (not shown), 9a to 9d are protrusions provided on the lower surface of the case 6, and l0a to 10d are holes provided in the heat sink 1 to match the protrusions 9a to 9d of the case 6 and allow them to pass therethrough.
この半導体装置の放熱板１とケース６の接着工程は以下
のようなものである。放熱板１上に、絶縁基板２、金属
パターン３ａ〜３Ｃ及び半導体素子４を接着し、半導体
素子４と金属パターン３ａ、３ｃを金属細線５で接続し
た後、ケース６の放熱板１と接着する面に接着剤を塗布
し、また電極７の金属パターン５と接する面には半田な
どのろう材を塗布する６次に、ケース６と放熱板１を接
着し、放熱板１の裏側から、放熱板の穴１０ａ〜ＩＯｄ
を通して出てきたケース６の突起９ａ〜９ｄをつぶす、
その後、熱板などの上で接着剤を硬化させる。The process of bonding the heat sink 1 and the case 6 of this semiconductor device is as follows. The insulating substrate 2, metal patterns 3a to 3C, and semiconductor element 4 are bonded onto the heat sink 1, and the semiconductor element 4 and the metal patterns 3a, 3c are connected with thin metal wires 5, and then bonded to the heat sink 1 of the case 6. Apply adhesive to the surface, and apply a brazing material such as solder to the surface of the electrode 7 in contact with the metal pattern 5. 6. Next, glue the case 6 and the heat sink 1, and heat the heat sink from the back side of the heat sink 1. Holes 10a to IOd in the board
Crush the protrusions 9a to 9d of the case 6 that come out through the
The adhesive is then cured on a hot plate or the like.
従来の半導体装置は、放、熱板１に設けられた穴１０ａ
〜ｌＯｄが放熱板１の中心線に対して対称に配置されて
おり、ケース６に設けられた突起９ａ〜９ｄもこれに対
応して対称となっている。このため、ケース６と放熱板
１を接着するとき、１８０°反対に接着することもでき
、誤挿入による不良を発生するなどの問題点があった。A conventional semiconductor device has a hole 10a provided in a heat radiation plate 1.
~lOd are arranged symmetrically with respect to the center line of the heat sink 1, and the protrusions 9a to 9d provided on the case 6 are also symmetrical accordingly. Therefore, when bonding the case 6 and the heat dissipating plate 1, the bonding can be done in the opposite direction by 180 degrees, which causes problems such as defects due to incorrect insertion.
この発明は上記のような問題点を解消するためになされ
たもので、放熱板へのケース誤挿入を防ぐことを目的と
する。This invention was made to solve the above-mentioned problems, and its purpose is to prevent incorrect insertion of the case into the heat sink.
この発明に係る半導体装置は、ケースとの密着性を増す
ために放熱板に設けた穴とそれに対応する位置にケース
側に設けた突起を、非対称に配置したものである。In the semiconductor device according to the present invention, in order to increase the adhesion with the case, holes provided in the heat sink and protrusions provided on the case side at corresponding positions are arranged asymmetrically.
この発明における半導体装置は、放熱板に設けた穴と、
この穴に対応した位置にケースに設けた突起を非対称に
したことにより、一定方向しが接着できなくなり、誤挿
入を防ぐことができる。The semiconductor device according to the present invention includes a hole provided in a heat sink,
By making the protrusions provided on the case asymmetrical at positions corresponding to these holes, it is impossible to adhere in a fixed direction, which prevents incorrect insertion.
第１図はこの発明の一実施例による半導体装置を示すも
ので、第２図Ｃに対応する図である。第１図において、
ｌＯａ、 ｌＯｂ、 ｌＯｃ、 １０ｄは放熱板１の左
右に２個ずつ設けられた穴で、これらの穴１０ａ〜１０
ｄのうち、穴１０ｄだけを穴８ｂ側にずらすことにより
、放熱板１の中心線に対して左右が非対称となるよう配
置されている。なお図示しないが、この放熱板１に接着
されるケース６についても、このケース６に設けられる
突起９ａ〜９ｄのうち、穴９ｄの位置を放熱板１の穴１
０ｄと嵌め合うような位置に設ける。このようにした放
熱板１とケース６においては、放熱板の穴１０ａ〜ｌＯ
ｄにケースの突起９ａ〜９ｄを通して接着する方法は一
通りに限られることになり、誤挿入のおそれはない。FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and is a diagram corresponding to FIG. 2C. In Figure 1,
lOa, lOb, lOc, 10d are two holes provided on the left and right sides of the heat sink 1, and these holes 10a to 10
By shifting only the hole 10d toward the hole 8b, the heat dissipating plate 1 is arranged asymmetrically with respect to the center line of the heat sink 1. Although not shown, the hole 9d of the protrusions 9a to 9d provided on the case 6 is also aligned with the hole 1 of the heat sink 1 in the case 6 to be adhered to the heat sink 1.
Provided at a position that fits with 0d. In the heat sink 1 and case 6 thus constructed, the holes 10a to 10 of the heat sink are
The method of adhering the case through the protrusions 9a to 9d is limited to one method, and there is no risk of incorrect insertion.
以上のようにこの発明によれば、ケースと密着性を増す
ために使用する放熱板の穴を非対称に設け、その穴に挿
入すべきケースに設けた突起も放熱板の穴にあわせて非
対称に配置したので、誤挿入のおそれはなく、不良を発
生しない効果がある６As described above, according to the present invention, the holes in the heat sink used to increase adhesion to the case are provided asymmetrically, and the protrusions provided on the case that are to be inserted into the holes are also asymmetrically aligned with the holes in the heat sink. Because of this arrangement, there is no risk of incorrect insertion and there is no risk of defects6.
第１図は、この発明の一実施例による半導体装置の上面
図、第２図ａは従来の半導体装置を示す斜視図、第２図
すは半導体装置のケースを示す斜視図、第２図ｃ Ｊ、
を従来の半導体装置を示す上面図である。
図中、ｌは放熱板、２は絶縁基板、３ａ、 ３ｂ、 ３
ｃは金属パターン、４は半導体素子、５は金属細線、６
はケース、７はｔｉ、８ａ、８ｂは取付用穴、９ａ〜９
ｄは突起、ｌＯａ〜、ＩＯｄは穴である。
なお１図中同一符号は同−又は相当部分を示す。1 is a top view of a semiconductor device according to an embodiment of the present invention, FIG. 2a is a perspective view of a conventional semiconductor device, FIG. 2 is a perspective view of a case of the semiconductor device, and FIG. 2c is a perspective view of a conventional semiconductor device. J.
FIG. 2 is a top view showing a conventional semiconductor device. In the figure, l is a heat sink, 2 is an insulating substrate, 3a, 3b, 3
c is a metal pattern, 4 is a semiconductor element, 5 is a thin metal wire, 6
is the case, 7 is ti, 8a, 8b are mounting holes, 9a to 9
d is a protrusion, lOa~, IOd are holes. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
されるケース側に設けられた複数の対応する突起を通し
て取付けるようにしたものにおいて、上記放熱板の穴を
左右非対称になるように配置し、これに対応して上記ケ
ースの突起も放熱板の穴にあわせて非対称に配置したこ
とを特徴とする半導体装置。In the case where the heat sink is installed through a plurality of holes provided in the heat sink through a plurality of corresponding protrusions provided on the side of the case that is bonded onto the heat sink, the holes in the heat sink are arranged so that the holes are asymmetrical. A semiconductor device characterized in that the projections of the case are also arranged asymmetrically in accordance with the holes of the heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146210A JPH0311797A (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1146210A JPH0311797A (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0311797A true JPH0311797A (en) | 1991-01-21 |
Family
ID=15402609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1146210A Pending JPH0311797A (en) | 1989-06-08 | 1989-06-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311797A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008251687A (en) * | 2007-03-29 | 2008-10-16 | Toshiba Corp | Printed circuit board, and electronic equipment equipped with this |
-
1989
- 1989-06-08 JP JP1146210A patent/JPH0311797A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008251687A (en) * | 2007-03-29 | 2008-10-16 | Toshiba Corp | Printed circuit board, and electronic equipment equipped with this |
| US8125783B2 (en) | 2007-03-29 | 2012-02-28 | Kabushiki Kaisha Toshiba | Printed circuit board and electronic apparatus |
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