JPH0311767A - Velocity modulation type field-effect transistor - Google Patents

Abstract

PURPOSE:To enable a field effect transistor of this design to execute a velocity modulation well by a method wherein a pair of quantum well layers, which are formed of different materials and arranged adjacent to each other through the intermediary of a tunnel barrier, and provided as channels. CONSTITUTION:A buffer layer 2 of i-AlGaAs and an undoped first quantum channel layer 3 are formed on an S, I, GaAs substrate 1 through a molecular beam epitaxial growth method. Furthermore, a potential barrier layer 4, a second channel layer 5, and a gate insulating layer 6 are successively laminated thereon. Then, a gate electrode 8 is built on the insulating layer 6, as IS and an ID are formed through ion implantation, and a source electrode 9S and a drain electrodes 9D are formed through evaporation. When the channel layers 3 and 5 are brought into ohmic contact and the thicknesses of the channel layers 3 and 5 different from each other in lattice constant are reduced to a critical thickness or below where a misfit transition occurs, an excellent interface can be obtained. By this setup, an excellent velocity modulation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor (F) using a heterojunction.
Field-Effect Transistor (hereinafter abbreviated as FET), particularly related to an element called a speed modulation type FET, and an FE for improving its speed control characteristics.
Regarding TfN construction.

(Prior art) Figure 8 shows Vinter and Tadela.
Applied Physics Letters (Appl, Phys, Lett,) Volume 50, 7
Speed modulation type F reported in No. 410 (1987)
A cross-sectional view of an ET element is shown. In the figure, 1 is semi-insulating (S
, 1. ) GaAs substrate, 83 is a first channel layer made of non-doped GaAs, 84 is non-doped A1o, 3G
ao, potential barrier layer consisting of 7As, 85 is n
a second channel layer (quantum well layer) made of type GaAs;
86 is a gate insulating layer, which is non-doped A1o, 3Gao.
, 7A3. A gate electrode 8 is formed on the surface of the gate insulating layer 86. After forming the n-wall regions Is and ID by ion implantation, a source electrode 98.degree. and a drain electrode 9D are formed by vapor deposition to make ohmic contact with the channel layer 83,85.

FIG. 9 is a band diagram under the gate of this device at thermal equilibrium. Such a speed modulation type FET functions as follows. In a state where the carrier concentration (ns) is low, as shown in FIG.
3 is thicker than the second channel layer 85, the ground level E1 of electrons in the first channel is lower in energy than the ground level E1 of electrons in the second channel. However, when a forward voltage is applied to the gate and ns becomes high, the conduction band of the second channel layer decreases.
E12 has lower energy than Ell. At lower gate voltages than the gate voltage vc (transition voltage) where subbands E11 and E12 intersect, many electrons travel through non-doped GaAs (first channel layer) with high electron mobility; Conversely, a high gate voltage travels through n-type GaAs (second channel layer) with low electron mobility, resulting in negative transfer conductance.

(Problems to be Solved by the Invention) The characteristic of the velocity modulation type FET taken as an example here is that velocity modulation is performed by utilizing the difference in electron mobility between non-doped GaAs and n-type GaAs. It is.

Here, since a high electric field is applied to the channel of a microgauge (0.25 μm or less) FET, the transfer conductance of such a device is considered to be determined by the saturation speed rather than the low electric field mobility. Tomizawa
awa) et al.
Device Letters (IEEE ElectronDe
vice Lett, ), EDL Volume-5, No. 11, 4
As reported on page 64 (1984), since the electron saturation speeds of non-doped GaAs and n-type GaAs are almost the same, the effectiveness of conventional velocity modulation type FETs in fine gates is doubtful.

In addition, in conventional velocity modulation type FETs, the energy band shape in the first channel changes significantly with ns, so the ground level shifts depending on the gate voltage, and the problem is that the control method of Vc is poor and device design is difficult. was there.

The present invention provides an FET in which good velocity modulation can be performed even in an ultra-fine gate whose carrier transport characteristics are dominated by the saturation velocity, and in which the element design is flexible.

(Means for Solving the Problem) According to the present invention, a pair of quantum well layers formed through a potential barrier layer having a thickness that allows carriers to pass through by tunneling effect is provided as a channel layer, and the channel layer A field effect transistor that performs charge control by applying a voltage to a gate electrode provided through a gate insulating layer, the pair of quantum well layers having a charge control function of a pair of carriers formed in each quantum well layer. The quantum well layer is formed so that the energy magnitude relationship of the ground level is switched depending on the level of the gate voltage, and the pair of quantum well layers are made of materials having different effective masses of carriers. A modulated field effect transistor is obtained.

Furthermore, if a charge supply layer doped with impurities is provided separately from the channel layer in order to supply charges, the current driving ability can be improved. Furthermore, as another means of improving the current drive ability, the channel layer may be doped with impurities.

(Function) In all of the velocity modulation type FETs according to the prior art, a pair of channel layers in which real-space transition of carriers occurs are made of the same material, and depending on the presence or absence of impurity doping (or the presence or absence of a spacer layer that spatially separates the carrier supply layer) ) that created a difference in electron mobility. In order to perform velocity modulation well even in a fine channel, it is sufficient to make the pair of channels different in not only the low electric field mobility but also the saturation velocity of carriers. That is, different materials may be employed for each channel.

In addition, by employing a pair of quantum well layers coupled through a tunnel barrier layer as the first and second channels, the ground level can be controlled by the effective electron mass and the well width. It also becomes easier.

(Example) FIG. 1 shows a cross-sectional view of a velocity modulation type FET according to a first example of the present invention. Such an element is manufactured as follows. S, 1. Non-doped Alo, 2Ga□ is deposited on the GaAs substrate 1 by, for example, molecular beam epitaxial growth.
, BAs buffer layer 2 of 111 m, non-doped In
The first quantum well channel layer made of □, 2Gao, and BSa is 10OA; the potential barrier layer 4 is made of non-doped AIo, 2Gao, and BAs is made of 50A1; the second quantum well channel layer 5 is made of non-doped GaAs is made of 10O
A gate insulating layer 6 made of non-doped A, 4Ga□, and 6As is sequentially grown to a thickness of 500A. Next, a gate electrode 8 is formed on the gate insulating layer 6. After forming n-type head regions Is and ID by ion implantation, ohmic contact with the channel layers 3 and 5 is established by forming a source electrode 9S and a drain electrode 9D by vapor deposition. Here InGa
Although As and AlGaAs have different lattice constants, In□,2
It is known that by making the Gao or BAs layer less than the critical thickness (approximately 150A) at which misfit dislocations occur, elastic strain becomes a positive lattice layer that alleviates lattice misalignment, forming a good interface. .

FIG. 2 is a band diagram of the first embodiment of the present invention shown in FIG. 1 in a thermal equilibrium state. here,
The numbers 2 to 8 correspond to those in FIG. El
l and El2 are the ground levels of electrons in the first channel 3 and the second channel 5, respectively.

There is about 290 between Ino, 2Ga□, 8As and QaAs.
Since there is a meV band gap difference, 60% of that
becomes a conduction band offset, the first quantum well layer 3
The bottom of the conduction band is about 170 degrees lower than that of the second quantum well layer 5.
It is deeper by meV. In this embodiment, since the first and second channel layers have the same film thickness, the heights of the ground levels El1 and El2 from the bottom of the conduction band are approximately the same.

The gate voltage at which subbands E11 and El2 intersect is Vc.
shall be. Figure 3(a) when the gate voltage is below Vc.
Since the bandgap of InGaAs channel 3 is smaller than that of GaAs channel 5, El is
Lower energy, almost all electrons are InGaA
Runs in the s layer. However, when the gate voltage exceeds Vc, the conduction band of the second channel layer decreases, and as shown in FIG. 3(b), El has lower energy than El1, and the probability of occupation of the GaAs channel 5 In
It comes to exceed GaAs channel 3. When the gate voltage is lower than Vc, a large number of electrons travel through non-doped InGaAs, but when the gate voltage is high, on the contrary, many electrons travel through non-doped GaAs. Henderson et al.
Letters (IEEE Electron Device
Lett, ), EDL-7, p. 288 (1986), the electron saturation velocity in Ino, 2Gao, and BAs strained layers is about 1.5 times higher than that of GaAs, so the device Good velocity modulation can be achieved even in ultrafine gates whose carrier transport characteristics are dominated by the saturation velocity.

Here, let us briefly estimate the voltage Vc. El and E1
Assuming that the heights measured from the bottom of the two conduction bands are almost the same, the second
The channel layer (position 200A from the buffer l-channel interface) has a conduction band discontinuity (approximately 170m
The condition where Ell and El2 intersect is a state in which the energy becomes lower by eV). VC=VOFF+ΔV
If c (VOFF: threshold voltage of EFT) is set, the vacuum potential at the gate interface (at a position 75 OA from the buffer channel interface) when the gate voltage is Vc has lower energy than the buffer channel interface by ΔVc. Assuming that the electric field is uniform, ΔVc can be obtained by solving the following equation.

ΔVc ΔV1 + 170meV Δ
v1750A 200A
50A, it can be seen that ΔVc~850meV. In this way, in the present invention, the ground level is uniquely determined by the thickness of the quantum well layer and has no bias dependence, so that the transition voltage Vc can be easily controlled and the designability of the element can be improved.

FIG. 4 shows a cross-sectional view of a velocity modulation type FET according to a second embodiment of the present invention. In the figure, I is S, 1. GaAs substrate, 42 a buffer layer made of non-doped GaAs, 43
44 is a first quantum well channel layer made of non-doped Ino, 2Ga□, and BAs, and 44 is a non-doped AI0.2Ga layer.
g, a potential barrier layer made of BA3; 45, a second quantum well channel layer made of non-doped GaAs; 4;
6 is a gate insulating layer (electron supply layer) made of n-type A1o, 2GaO08A8 with an impurity concentration of 18 3 2×10 7 cm, and 47 is a cap layer made of n-type GaAs with an impurity concentration of 5×10 181 cm 3 .

A gate electrode 8 is formed in the recessed portion G÷ formed beyond the cap layer 47. In addition, channel layers 43 and 4
5, a two-dimensional electron gas is generated.

A source electrode 9S and a drain electrode 9 are provided on the surface of the cap layer 47.
After forming D by vapor deposition, alloy regions As, AD are formed to make ohmic contact with the channel layer 43, 45.

FIG. 5 is a band diagram under the gate of this device at thermal equilibrium. Here, the numbers 8.42 to 46 correspond to those in FIG.

Ell and E12 are the ground levels of electrons in the first channel 43 and the second channel 45, respectively. Even in such an element, good velocity modulation can be achieved using the same mechanism as in the first embodiment. In the first embodiment, since there was no charge supply layer, sufficient current driving ability could not be obtained, but by adopting such a structure, it is also possible to improve the current driving ability.

FIG. 6 shows a cross-sectional view of a velocity modulation type FET according to a third embodiment of the present invention. In the figure, I is S, 1. GaAs substrate, 62 is a buffer layer made of non-doped GaAs, 63
64 is a first quantum well channel layer made of non-doped Ino, 2Gao, BAs, and 64 is non-doped AIo, 2Ga.
o, a potential barrier layer made of BAs; 65, a second quantum well channel layer made of n-type GaAs with an impurity concentration of 6×1010171 C; and 66, a gate insulating layer made of non-doped Alo, 4Gao, and 6As. A gate electrode 8 is formed on the surface of the gate insulating layer 66. After forming n-wall regions Is and ID by ion implantation,
Source electrode 9S, drain electrode 98. Drain electrode 9D
are formed by vapor deposition and are in ohmic contact with the channel layer 63,65.

FIG. 7 is a band diagram under the gate of this device at thermal equilibrium. Here, the numbers 8.62 to 66 correspond to those in FIG.

Ell and E12 are the ground levels of electrons in the first channel 63 and the second channel 65, respectively. In such devices, there is a speed modulation effect based on the difference in electron saturation speed between InGaAs and GaAs, and a conventional speed modulation FET.
Combined with the electron mobility modulation effect based on the same principle (that is, the difference in mobility depending on the presence or absence of doping in the channel), extremely good current modulation can be achieved. Further, in this embodiment, since the channel is made of an n-type semiconductor, a high current driving capability can be obtained as in the second embodiment. As a variation of this third embodiment, the first quantum well channel layer is doped with n-type impurities at 10181 cm3. The effects of the invention can also be obtained when the second quantum well channel layer is doped with an n-type impurity of 5×10 /am.

In the above embodiments, AlGaAs/InGaAs/GaA
Although the present invention has been explained using an s strain system, the present invention also applies to AlO,
48Ino, 52AS/Gao4□-xIno, 53+
It is also possible to realize other material systems such as xAS/Gao 4□Ino and 53AS strained systems.

(Effects of the Invention) As is clear from the above detailed description of the invention, according to the present invention, a pair of quantum well layers made of different materials and disposed adjacent to each other with a tunnel barrier interposed therebetween are used as channels. , the current modulation characteristics of the velocity modulation FET can be greatly improved, and the carrier ground level can be controlled by the effective mass and well width, making device design easier.

Sufficient current driving capability can be obtained by providing a semiconductor layer doped with impurities as a charge supply layer for the channel layer. Further, by doping the channel layer with impurities, the velocity modulation effect can be amplified and the current driving ability can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the element structure of the first embodiment according to the present invention;
Fig. 2 is a potential band diagram in thermal equilibrium of the first embodiment, Fig. 3 is a potential band diagram showing the velocity modulation operation of the present invention, and Fig. 4 is a cross section of the element structure of the second embodiment according to the present invention. 5 is a potential band diagram in thermal equilibrium of the second embodiment, FIG. 6 is a cross-sectional view of the element structure of the third embodiment according to the present invention, and FIG. 7 is a potential band diagram in thermal equilibrium of the third embodiment. FIG. 8 is a sectional view of an element structure of an example of a velocity modulation type FET according to the prior art, and FIG. 9 is a potential band diagram of a conventional velocity modulation type FET in thermal equilibrium. In the figure, 1.8.1. GaAs substrate, 2, 4, 6, 44, 64,
66.84.86...Non-doped AlGaAs layer, 3
,43.63...--Non-doped InGaAs strained layer, 5.42,45,62.83...Non-doped GaA
s layer, 8... Schottky gate electrode, 9S, 9D-
0, ohmic electrode, 46-n-type AlGaAs layer, 47,
65.85・n-type GaAs layer, AS, AD...alloy region, IS, ID...n-type implantation region, El, El・
...It is the electronic ground level.

Claims (3)

[Claims] (1) A pair of quantum well layers are formed as a channel layer through a potential barrier layer having a thickness that allows carriers to pass through by tunneling effect, and a gate electrode is provided through the channel layer and a gate insulating layer. A field effect transistor that performs charge control by applying a voltage, and the pair of quantum well layers has a relationship in energy level between the ground levels of a pair of carriers formed in each quantum well layer depending on the level of the gate voltage. 1. A velocity modulation field effect transistor, wherein the pair of quantum well layers are formed so as to be exchanged according to each other, and the pair of quantum well layers are made of materials having different effective masses of carriers. (2) In the velocity modulation field effect transistor according to claim 1, at least one layer other than the pair of quantum well layers is to generate a two-dimensional carrier gas in at least one of the pair of quantum well layers. A speed modulation field effect transistor comprising a semiconductor layer doped with a charge supply layer. (3) The speed modulation type field effect transistor according to claim 1, wherein at least one of the pair of quantum well layers is doped with an impurity.