JPH03117219A - Variable length coding transmission system and transmitter and receiver for variable length coding transmission - Google Patents

Abstract

PURPOSE:To take complementary matching of a memory occupancy quantity of both transmission reception buffer memories by providing a unique word generating circuit or the like to a transmitter and providing a unique word detection circuit or the like to a receiver. CONSTITUTION:A UW(unique word) generating circuit 100, a 1st multiplex circuit 101, a BMO(buffer memory occupied quantity) register circuit 102 and a 2nd multiplex circuit 103 are provided to a transmitter in addition. Then a memory occupancy quantity information of a transmission buffer memory 5 is multiplexed onto a coded signal and the result is transmitted. Moreover, a UW detection circuit 18, a reception BMO difference detection circuit 19 and an LPF 20 are provided to a receiver in addition, and a difference between the specified memory occupancy quantity of the reception buffer memory 11 obtained from the sent memory occupancy quantity information of the memory 5 and the actual memory occupancy quantity of the memory 11 is detected and the result controls a decoded operating clock frequency as a control signal. Thus, the complementary matching state of the memory occupancy quantity of the memories 5, 11 is always obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention relates to variable length coding transmission in which information signals such as television signals and audio signals are compressed and transmitted by variable length coding. and the transmitting and receiving devices used to implement the method.

(Prior art) If television signals and audio signals are simply PCM encoded, they are fixed-length encoded information, but high-efficiency encoding that removes the inherent redundancy and audiovisual redundancy of the signal is required. When this is done, the information generally becomes a variable length code. When such variable-length encoded signals are transmitted over a fixed rate transmission line, a buffer memory (referred to as a transmission buffer memory) is used on the transmitting side to control and smooth the amount of encoded information. Further, on the receiving side, a buffer memory (referred to as receiving buffer 7 memory) is used at the input end in order to secure a fixed number of television or audio signal samples per unit time.

On the other hand, in recent years, systems for packet transmission of television signals and audio signals have become integrated 5e (ISDN) systems.
rv1ces digital network) A
It has been proposed as TM (asynchronous transfer mode). Even in such a variable rate transmission line, the maximum rate that can be transmitted is actually limited, and there is packet delay fluctuation that varies depending on the packet arrival time depending on the state of the packet transmission network, so it is difficult to use a fixed rate transmission line. As with the case, buffer memory is required for both sending and receiving.

In addition to its original function of buffering (smoothing) variable-length encoded signals, this buffer memory is also used to synchronize the operating clock frequencies of the transmitter (encoder) and receiver (decoder). can do. This conventional example will be explained below.

The transmitting device and the receiving device are connected via a transmission path, but since the transmission path is not necessarily dedicated to each individual encoding/transmission system, the encoding/receiving device and the transmission path are in an asynchronous state. Often connected. That is, since the operating clock frequencies of the encoding/decoding system and the transmission system do not have a simple integer ratio, it is often difficult to achieve phase synchronization of the operating clocks using a PLL or the like. Therefore, by operating the input and output of the buffer memory asynchronously, it is possible to connect the two. As a result, an asynchronous system exists between the transmitting device and the receiving device, and the synchronization between the transmitting device and the receiving device is inevitably not maintained. If the transmitting device and the receiving device are operated asynchronously, the difference in operating clock frequencies between them will cause underflow and overflow of input data in the receiving device, so normal decoding operation cannot be expected.

Therefore, conventionally, the memory occupancy of the transmission buffer memory ff
Negative feedback control of the encoding characteristics is performed so that the long-term average value of i (T-BMO) becomes a constant value, and the long-term average value of the memory occupancy of the reception buffer memory (R-BMO) is monitored. A method is adopted in which the operating clock of the receiving device is controlled so that the R-BMO becomes a predetermined value. That is, if the operating clock of the receiving device has a frequency deviation with respect to the operating clock of the transmitting device, the memory occupancy Ji of the receiving buffer memory is reduced according to the frequency deviation.
Since the long-term average value of lR-BMO increases or decreases, this is detected and the decoding operation clock is controlled.

FIG. 10 is a block diagram of a video transmission system for explaining a conventional video variable length encoding method, and assumes that the transmitting device, transmission path, and receiving device do not have a common clock as described above. . Further, the transmission line 9 is a fixed rate transmission line. The video input signal is DPCM (differential PCM
) After being converted into a prediction error signal by the encoding circuit 3, it is converted into a variable length code word by the variable length encoding circuit (VWL CENC) 4, and statistical redundancy is removed.

The output of the variable length encoding circuit 4 is written into the transmission buffer memory (T-BUF) 5 using a clock (variable length encoding clock) corresponding to the variable length code word. Reading from the transmission buffer memory 5 is performed using a transmission lock supplied from the transmission line 9. In the example shown in FIG. 10, an error correction encoding circuit (FEC) 6 for correcting transmission errors is connected to the output side of the transmission buffer 7 and memory 5.

From the transmission buffer memory 5, the memory occupancy (T-BM
Information O) is detected and provided to the encoding control circuit 7. The encoding/control circuit 7 outputs an encoding control signal according to T-BMO.

This encoding control signal is fed back to the DPCM encoding circuit 3, for example, and the amount of information generated in the encoded signal is controlled by a method such as changing the quantization characteristic. With this negative feedback control, the memory occupancy iT-BMO of the transmission buffer memory 5 becomes a prescribed fixed value on a long-term average. Note that the output rate of the transmission buffer memory 5 is fixed to a constant value determined by the transmission rate.

Further, the operating clock of the transmitting device is, for example, a clock synchronized with a video synchronization signal supplied from the outside, and is given to each circuit of the transmitting device, but as described above, it is not in a synchronous relationship with the transmission lock.

Although a block diagram using DPCM encoding is shown here, the same applies to other encoding methods.

Next, the receiving device will be explained. In the receiving device, the video data input via the transmission line 9 and the transmission lock synchronized therewith are input, and after passing through an error correction decoding circuit (FEC) 10, the data is sent to a reception buffer memory (R-B).
UF) Write to 11. Reading of this reception buffer memory 11 is performed by the variable length decoding circuit (VWLCDEC) in the subsequent stage.
) 12.

That is, a variable length code is output using the variable length decoding clock output from the variable length decoding circuit 12 so that a constant video signal (pixel sample) can be decoded per unit time. Therefore, the output of the variable length decoding circuit 12 is a prediction error signal having a fixed number of samples per unit time, which is decoded by the DPCM decoding circuit 13 into the original video signal.

Memory occupancy detected from the reception buffer memory 11 (
R-BMO) information is sent to the decoding operation clock control circuit 14.
The difference between the long-term average value of this memory occupancy R-BMO and a prescribed fixed value corresponding to the long-term average memory occupancy of the transmission buffer memory is detected and fed back to the decoding operation clock generation circuit 15. and controls the frequency of the decoding operation clock.

Note that the video synchronization signal multiplexed in advance into the transmission signal is detected by the variable length decoding circuit 12 and output to the terminal 17.

The conventional technology described above has the following problems.

1) If the long-term average value of the occupancy T-BMO of the transmission buffer memory 5 is not defined in advance, the reception buffer memory 11 cannot operate in a state consistent with the transmission buffer memory 5. That is, the memory occupancy ffl of the transmitting buffer memory 5 and the receiving buffer memory 11 is originally complementary to T-BMO and R-BMO. For example, when T-BMO is almost at the maximum, R-BMO is at the minimum. Perform complementary operations to achieve this. At this time, the maximum values of T-BMO and R-BMO may be the same. However, if the long-term average value of the T-BMO of the transmitting buffer memory 5 is not specified, a deviation will occur in this complementary operation, so the receiving buffer memory 11 will need an extra large capacity as a margin for the deviation. shall be. The same applies if the initialization of the reception buffer memory 11 is incorrect. In such a case, R
- Since the BMO does not accurately indicate the deviation between the decoding operating clock and the encoding operating clock, it is impossible to accurately control the decoding operating clock using this.

2) Even when a long-term average value of the memory occupancy T-BMO of the transmission buffer memory 5 is defined, T-BMO fluctuates in a short time depending on the nature of the video input signal. Therefore, the memory occupancy fiR-B of the reception buffer memory 11
MO will also fluctuate in a short period of time accordingly.
Low frequency phase jitter remains in the decoding operation clock.

3) Variable rate transmission line (ISDN packet transmission: A
TM, etc.), the advantage of constant quality transmission is that the amount of encoded information is essentially not controlled, so it is possible to control the memory occupancy T-BMO of the transmission buffer memory 5 to a specified value. Can not. Therefore, according to the above-mentioned prior art, not only is it impossible to control the receiving clock frequency in variable rate transmission, but also the sending/receiving buffer memory 5.
11 matching operation is also not guaranteed.

(Problems to be Solved by the Invention) As described above, when a video signal is variable-length encoded and transmitted, an asynchronous transmission path is interposed between the transmitter and the receiver, so the transmitter The operating clock of the receiver becomes out of synchronization with the operating clock of the receiving device, and if this is left unattended, data underflow or overflow occurs in the receiving device, making it impossible to perform correct decoding operations. Therefore, conventionally, negative feedback control of the encoding characteristics is performed so that the long-term average value of the memory occupancy of the transmitting buffer memory becomes a constant value, and the long-term average value of the memory occupancy of the receiving buffer memory is monitored. By controlling the operating clock of the receiving device so that this becomes a specified value, a method is used to achieve complementary matching regarding the memory occupancy of the transmitting/receiving buffer memory.

However, this conventional technology has limitations such as 1) the long-term average value of the memory occupancy of the transmission buffer memory must be a fixed specified value, and 2) the long-term average value of the memory occupancy of the transmission buffer memory is not specified. 3) Even when the memory capacity is short-term, the influence of short-term fluctuations in memory occupancy remains as low-frequency jitter in the decoding operation clock, and 3) it cannot be applied to variable rate transmission lines such as ISDN ATMs. was there.

The present invention provides a variable-length coding transmission method that can complementarily match the memory occupancy of both transmitting and receiving buffer memories in variable-length coding transmission of video signals, etc., without the above-mentioned problems; It is an object of the present invention to provide a transmitting device and a receiving device for variable length coding transmission to which this method is applied.

C Configuration of the Invention] (Means for Solving the Problems) In order to solve the above problems, in the present invention, the memory occupancy information of the transmission buffer memory is multiplexed into an encoded signal and transmitted from the transmitting side, and the receiving side In this step, the initial occupied capacity of the receiving buffer memory is set using the transmitted memory occupancy information of the transmitting buffer memory, and the memory occupied capacity of the receiving buffer memory determined from the memory occupied capacity information of the transmitting buffer memory that is subsequently transmitted. The present invention is characterized in that the difference between the specified value and the actual memory occupancy of the reception buffer memory is detected, and the decoding operation clock frequency is controlled using the difference signal as a control signal.

(Function) In the present invention, the specified memory occupancy of the reception buffer memory is determined on the reception side based on the memory occupancy information of the transmission buffer memory transmitted from the transmission side, and this is used as the initial memory occupancy of the reception buffer memory. value. As a result, an accurate complementary matching state of the memory occupancies of the transmit buffer memory and the receiving buffer memory is achieved, and this matching state is maintained even after initialization unless there is an abnormality such as line disconnection. As a result, the capacity margin of the receive buffer memory, which was conventionally required due to incomplete initialization, is no longer necessary, and the capacity of the receive buffer memory can basically be the same as the capacity of the transmit buffer memory.

In addition, since information on the memory occupancy of the transmission buffer memory necessary for initializing the reception buffer memory is transmitted periodically, it is possible to set the long-term average value of the memory occupancy of the transmission buffer memory to a fixed value in advance, as in the conventional example. It is not necessary to specify this value, and it is acceptable for this long-term average value to fluctuate. Therefore, the degree of freedom in encoding control in fixed rate transmission increases, and higher quality encoding becomes possible. At the same time, unlike variable rate transmission, the long-term average value of the memory occupancy of the transmission buffer memory is not originally defined (in variable rate transmission, the transmission rate is arbitrary within a certain range,
In this case, the receiving buffer memory can be initialized in exactly the same way.

Regarding the control of the decoding operation clock frequency, as in the case of initializing the reception buffer memory described above, there is no need to impose any restrictions on the long-term average value of the memory occupancy of the transmission buffer memory.

In addition, low frequency jitter of the decoding operation clock does not occur due to short-term fluctuations in the memory occupancy of the transmission buffer memory, making stable frequency control possible. Furthermore, even in variable rate transmission, stable frequency control of the decoding operation clock is possible in exactly the same way.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a transmitter (encoder) for variable length coded transmission in the variable length coded transmission system of the present invention.

In the transmitting device shown in FIG. 1, a UW (unique word) generation circuit 1 is added to the conventional transmitting device shown in FIG.
00, a first multiplexing circuit (MUX) 101, a BMO (buffer memory occupied ff1) register circuit 102, and a second multiplexing circuit 103 are added. The UW generation circuit 100 generates a unique word (hereinafter referred to as UW) for distinguishing horizontal or vertical synchronization of video, which becomes a variable interval due to variable length encoding, and generates a unique word (hereinafter referred to as UW), The U for synchronization is added to the variable length encoded signal in advance.
This is for inserting the W, and although it is not shown in FIG. 10, it is basically necessary even in the conventional case.

Therefore, the transmitting device shown in FIG. 1 is essentially different from the conventional device shown in FIG. - Generate BMO information, multiplex it into a variable length coded signal output from the transmission buffer memory (T-BUF) 5 by the multiplexing circuit 103, and then send it to the transmission line via the error correction coding circuit 6. 9.

FIG. 2 is a block diagram showing an embodiment of a receiving device (decoding section) for variable length coding transmission in the variable length coding system of the present invention.

Regarding the second cause, the conventional receiving device shown in FIG.
Difference detection circuit 19 and LPF (low pass filter) 2
0 is added. The UW detection circuit 18 detects the UW from the output of the reception buffer memory 11 and determines the synchronization timing (
SYNC) and memory occupancy i of transmit buffer memory 5
Detects the T-BMO information and stores it in the receiving side buffer memory 1.
Information on the specified value R-BMO' of the memory occupation amount R-BMO of 1 is output. The BMO difference detection circuit 19 is R-BMO'
and the actual memory occupancy of the reception buffer memory 11 R−B
These differences are detected using the MO information as input. LP
F20 is for smoothing the output of the BMO difference detection circuit 19, and the output of this LPF 20 is supplied to the decoding operation clock generation circuit 21.

Note that among the functions of the UW detection circuit 18, the function of determining the synchronization timing 5YNC is necessary in the conventional example, and is omitted for simplicity in the block diagram of FIG. 10, but in FIG. - It is also used to obtain BMO', so it is clearly indicated.

With the configuration shown in Fig. 2, first, in the initial state, R-BMO'-
Assume R-BMO. Here, if we consider the case where the decoding operation clock frequency is higher than the encoding operation clock frequency, the memory occupancy of the reception buffer memory 11 is R
-BMO'>R-BMO decreases. A difference signal corresponding to these differences (R-BMO') (R-BMO) is output from the BMO difference detection circuit 19, and further outputted from the LP
After smoothing at F20, negative feedback is provided to the decoding operation clock generation circuit 21 so as to reduce the decoding operation clock frequency.

FIG. 3 is a block diagram showing another embodiment on the receiving device side according to the present invention. The difference from FIG. 2 is that the memory occupancy fiT-
The only difference is that the UW detection circuit 23 for detecting BMO information is connected to the front stage of the reception buffer memory 11.

A UW detection circuit 22 for detecting synchronization timing 5YNC is connected to the subsequent stage of the reception buffer memory 11, similar to the UW detection circuit 18 in FIG.

The difference between FIG. 2 and FIG. 3 mainly lies in the initial setting method of the reception buffer memory 11. To explain this,
More detailed operations including complementary matching operations of the transmitting/receiving buffer memory 5.11 will be described.

FIG. 4 shows complementary operations of the transmit buffer memory 5 and the receive buffer memory 11 when a fixed rate transmission line is used as the transmission line 9.

FIG. 4(a) shows a video variable length encoded signal outputted at regular intervals from the variable length encoding circuit 4 on the transmitting side, and in the example shown, the code length varies in the range of 1 to 4 bits. . Same figure (
b) shows the operation of the transmission buffer memory 5, and shows the smoothing effect and coding control for fixing the output rate. The numerical value shown in FIG. 5B represents the memory occupation amount T-BMO of the transmission buffer memory 5. FIG. 2C is a diagram of a variable length encoded signal on the transmission path 9. The transmission rate is 2 bits with one sample period as a unit time. The figure (d) shows the reception buffer memory 11.
The numerical value shown represents the memory occupation amount R-BMO of the reception buffer memory 11.

As is clear from FIG. 4, the sum of the memory occupancies of the sending and receiving buffer memories 5 and 11 shown in (b) and (d) is constant (-maximum occupancy of buffer memory capacity), that is, (T- BMO) + (R-BMO)-consL.

-T-BMOsax -R-BMOmax. That is, the transmission buffer memory 5 and the reception buffer memory 11 are complementary and matched.

FIG. 5 shows complementary operations of the transmit buffer memory 5 and the receive buffer memory 11 when a variable rate transmission line is used as the transmission line 9, and the view of the figure is the same as that of FIG. 4. The difference from Fig. 4 when a fixed rate transmission line is used is that basically no coding control is performed (except for the restriction to prevent the maximum rate from being exceeded), so IL'l is (the period indicated by the X mark in FIG. 5(c)) exists. During this period, the memory occupancy iT-BMO of the transmission buffer memory 5 becomes O, and conversely, the memory occupancy fnR-BMO of the reception buffer memory 11 becomes maximum. Even when a variable rate transmission line is used in this way, the complementary matching operation of the transmitting/receiving buffer memory 5.11 is maintained.

Next, transmit and receive buffer memory 5゜111: F
I F O (First In-Plrst 0ut
) More specific operations when using memory will be explained.

FIG. 6 shows an example of the operation of the transmission buffer memory 5 consisting of a FIFO memory. Since FIFO memory is assumed, the memory occupancy of the transmit buffer memory 5 is determined by the relative difference between the read and write address pointers.
(indicated simply as BMO in the figure) is determined. The read address pointer position of the buffer memory 5 is marked R,
The write address pointer positions are each indicated by the symbol W. First, it is assumed that T-BMO-0 has been established in advance. Two bits of data -3° are input at time t-0, and two bits corresponding to the transmission rate are output at time t-1. Thereafter, the process is repeated as follows.

1) At time t-12, when data "3" is input, the transmission buffer memory 5 is empty (T-BMO-0).

When data “3” is input, instantaneous T-BMO-“4”
becomes.

2) At time t-13, a part of data '3' is outputted and becomes T-BMO-'2'.

If data “3” is the final data such as a frame of a video signal, this T-BMO information (T-BMO-“21”)
is stored and transmitted to the receiving side. However, T-BM
The timing for transmitting the information of O is after all data "3" has been output.

3) At time t-14, the next data "4°" is input. If this data is also 4 bits long, the instantaneous T-BMO~
It becomes 6.

4) At time t-15, the remainder of data “3” is output and becomes T-BMO-“4’. At this time, as mentioned in 2), T-BMO-“2” is output together with the synchronization UW. ” information is transmitted. This multiplexing of T-BMO information is
As shown in the figure, this is performed in a multiplexing circuit 103 on the output side of the transmission buffer memory 5. That is, unlike UW, T-BMO information is not stored in the transmission buffer memory 5.

5) At time t-te, the next data is input, and similar input/output operations are repeated until the next synchronization UW arrives.

FIG. 7 shows an example of the operation of the reception buffer memory 11 when a FIFO memory is used. First, it is assumed that the memory occupation amount R-BMO (simply shown as BMO in FIG. 7) of the FIFO memory is initialized to "6" in advance. 6th
Corresponding to the operation of the transmission buffer memory 5 shown in the figure, the data "-3" is transferred to the reception buffer memory 1 at time t-1.
1 is entered. However, in FIG. 7, the delay of the transmission line 9 is ignored. Thereafter, input/output continues in the same manner as in the transmission buffer memory 5, and when data "3" at time t-20 is output, R-BMO-"4" is reached, and the memory of the transmission buffer memory 5 is occupied by IT-BMO- Complementarily matches “2”. That is, (R-BMO) + (T-B
MO) −”6′=const.

The examples shown in FIGS. 6 and 7 show cases where the FIFO memory has been properly initialized in advance. Next, such initialization means will be explained. First, in order to initialize and set the memory occupancy R-BMO of the reception buffer memory 5, (1) as shown in FIG.
There are two methods: (2) detecting the UW at the input of the reception buffer memory 5, as shown in FIG. FIG. 8 shows the operation when method (1) is used, and FIG. 9 shows the operation when method (2) is used.

Summarizing the above, the synchronous operation of the transmitting/receiving buffer memory 5.11 will be described step by step as follows.

In the initial state, the R/W address points are reset at the same time. However, if it is a fixed rate transmission, the output is not output until the BMO signal becomes approximately El (BM Osaw)/2, so that an underflow of the transmission buffer memory 5 does not occur even momentarily. In variable rate transmission, there is no problem because the output is stopped when the memory occupancy of the transmission buffer memory 5 is small (8MO20).

2) Receiving side start On the receiving side, the FI used for the receiving buffer memory 11
There are two initial setting states depending on the BMO setting method of the FO memory. One is about the B M O setting (+) in FIG. 8, where the R/W (read/write) pointer of the receive buffer memory 11 is set to the same position and the receive buffer memory 11 is set to through mode. a)~(d))
, UW is detected at the input end of the reception buffer memory 11. The other method is BMO setting (2) in FIG. 9, which is a method of simply waiting for UW to be detected at the input end of the receiving buffer memory 11. Since the process is the same after UW detection, the method (2) in FIG. 9 will be described below.

3) UW Detection When a UW is detected at the input end of the receiving buffer memory 11, the following (BMO' (information on the memory occupied mBMo of the transmitted transmitting buffer memory 5) is stacked and at the same time, as shown in FIG. 9(e) Receive buffer memory 11 as in
Reset the write pointer of (write from address 0).

4) While leaving the W clock count R pointer arbitrary, data is sequentially written into the reception buffer memory 11 according to the arrival of input data (UW is also written together).

At this time, the write clock (W clock) is counted (FIGS. 9(d) and (c)).

5) Detect R-BMO-R-BMO' When the write clock reaches BMO', reset the R pointer. At this time, the memory occupancy of the reception buffer memory 11 is R-BMO-R-BMO'. (Figure 9 (“)
) 6') Output according to the decoding process Since the read clock for the reception buffer memory 11 is supplied from the variable length decoding circuit 12, the contents of the memory 11 are read in accordance with this. Writing to the reception buffer memory 11 is performed sequentially as data arrives, as shown in FIGS. 9(g) and 9(h). If there is no difference between the encoding operation clock and the decoding operation clock, the reception buffer memory 11 will not underflow or overflow. If this happens, just start over.

The difference between R-BMO' and R-BMO is due to the frequency difference between the encoding operation clock and the decoding operation clock, so the difference signal (R-BMO') (R-BMO) is decoded. By feeding back to the clock generation circuit 21, clock control becomes possible. However, here, the memory occupancy for UW of the reception buffer memory 11 is jlR-BMO.
The deviation is ignored.

By the way, in the description of the above embodiment, information on the occupied amount T-BMO of the transmission buffer memory 5 is directly multiplexed into a variable length encoded signal and transmitted. In this case, on the receiving side, the occupancy amount T-BMO of the transmission buffer memory 5 must be converted into the memory occupancy amount fiR-BMO of the reception buffer memory 11. For example, the following conversion formula may be used for this purpose.

R-BMO' -BMOsax-(T-BMO)R-
BMO': Occupancy amount of reception buffer memory BMO
saw: Transmission buffer memory capacity (maximum occupancy) T-BMO: Transmission buffer memory occupancy Therefore, after performing the above conversion on the transmission side in advance, this converted value (R-B
Exactly the same effect can be obtained even if the MO') is multiplexed into a variable length coded signal and transmitted.

Furthermore, T-BMO or R-B which is multiplexed and transmitted
The MO' information does not need to be information that directly represents the memory occupancy of each buffer memory as a numerical value, and a specific code predetermined for transmission and reception is sufficient. Furthermore, the accuracy required for this memory occupancy information is expected to vary depending on the use and purpose of the transmission system to which the present invention is applied. That is, the information on the memory occupancy of each buffer memory may be expressed with a smaller number of levels,
And with a specific code assignment, it can be easily represented with a smaller number of bits.

[Effects of the Invention] According to the present invention, the initialization of the reception buffer memory and the reception side, which were conventional problems when transmitting video signals such as television signals and information signals such as audio signals by variable length encoding, can be solved. In synchronizing the decoding operation clock of the transmitter and the encoding operation clock of the transmitter, the transmit buffer can be used without creating unnecessary margins in the receive buffer memory and without imposing any encoding control constraints on the transmitter. Complementary alignment of the memory occupancies of the memory and the receive buffer memory can always be obtained. This makes it possible for the receiving side to perform correct decoding operations without causing data underflow or overflow due to non-synchronization of the operating clock with the transmitting side, thus solving the problems of the prior art.

Furthermore, the present invention provides similar effects not only when using a fixed rate transmission line, but also when using a variable rate transmission line, which has had problems with conventional variable length coding transmission systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the transmitting side according to one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the receiving side according to the same embodiment, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the receiving side according to the embodiment of the present invention, and FIG. A diagram for explaining the complementary operations of the transmit buffer memory and the receive buffer memory during rate transmission, FIG. 6 is a diagram showing a specific example of the operation of the transmit buffer memory in the present invention, and FIG. A diagram showing a specific operation example, FIG. 8 is a diagram showing an example of the initial setting of the buffer memory occupancy of the FIFO buffer memory, and FIG. 9 is another example of the initial setting of the buffer memory occupancy of the same FIFO buffer memory. FIG. 10 is a block diagram for explaining a conventional video variable length encoding transmission system. 4... Variable length encoding circuit, 5... Transmission, buffer memory, 8... Encoding operation clock generation circuit, 9...
Transmission line, 11... Reception buffer memory, 12... Variable length decoding circuit, 15... Decoding operation clock generation circuit, 100... Video synchronization unique word generation circuit,
101...Video synchronization unique word multiplex circuit, 10
2... Transmission buffer memory occupancy register circuit, 10
3... Transmission buffer memory occupancy multiplexing circuit, 18,
22.23... Unique word detection circuit, 19...
・Reception buffer memory occupancy difference detection circuit.

Claims (3)

[Claims] (1) In a transmission method in which an information signal is variable-length encoded and transmitted, the transmitting side multiplexes the memory occupancy information of the transmission buffer memory into a variable-length encoded signal and transmits it, and the receiving side records the transmitted memory occupancy information. The initial occupancy of the reception buffer memory is set using the amount information, and the difference between the specified memory occupancy of the reception buffer memory obtained from the memory occupancy information that is subsequently transmitted and the actual reception buffer memory occupancy is calculated. A variable length coding transmission system characterized by detecting the difference signal and controlling the decoding operation clock frequency using the difference signal as a control signal. (2) Encoding means that variable-length encodes an input information signal and outputs a variable-length encoded signal; a transmission buffer memory that temporarily stores the variable-length encoded signal; and memory occupancy information of the transmission buffer memory. and means for multiplexing the memory occupancy information with the encoded signal output from the transmission buffer memory and transmitting the multiplexed signal to a transmission path. . (3) means for receiving a variable length encoded signal transmitted from a transmitting side; a reception buffer memory for temporarily storing the received variable length encoded signal; and a variable length encoded signal output from the reception buffer memory. means for variable-length decoding using a decoding clock; and setting an initial memory occupancy of the reception buffer memory from memory occupancy information of the transmission buffer memory that is multiplexed and transmitted together with the variable-length encoded signal. means for determining a specified memory occupancy of the reception buffer memory from the memory occupancy information; and means for determining the specified memory occupancy of the reception buffer memory based on a difference signal indicating the difference between the specified memory occupancy and the actual memory occupancy of the reception buffer memory. 1. A receiving device for variable length encoded transmission, comprising means for controlling the frequency of a decoding operation clock.