JPH03116225A - State transition circuit - Google Patents

Abstract

PURPOSE:To reduce the packing area and to correct the errors and the change with no change of hardware by performing the state transition via a ROM and obtaining a state in response to the output via number of the ROM in a simple circuit constitution. CONSTITUTION:A state transition circuit is provided with a ROM 11 which is capable of the reading operations every (m) bits, and the transition state data 12 showing the state of the transition goal is outputted through an output terminal OUT of the ROM 11 as the m-bit parallel data. This parallel data is inputted to an input terminal D of the latchable flit-flop 13, and the present state display data 14 is outputted through an output terminal Q. Then the data 12 obtained at a certain time point is held until the next action cycle as the data 14 of a new action cycle. This data 14 is applied to the address input part of the ROM 11. Thus it is possible to cope with the flow errors or change of the state transition with a simple circuit without changing the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a state transition circuit that displays the next state to which a system should transition, and particularly relates to a state transition circuit in a communication network control device. .

[Conventional technology]

In recent years, multimedia information networks have been proposed and partially implemented as communication systems that perform advanced communication by mutually complementing individual systems using multiple media. In such communication systems, a device called Multimedia Max (commonly known as Triple M) is usually used.

This device can accommodate various devices such as facsimile machines, telephones, personal combination coaters, and televisions as terminals, and realizes multimedia information communication by mutually converting information such as images, sounds, and codes. can do. In such devices, a state transition circuit is used as a package to create and output data representing the state to which the system should transition next. This state transition circuit has characteristics as a sequential circuit in that the output response of the circuit to the current input is not determined by current human power alone, but depends on the past history of the input, and has a different character from that of a combinational circuit. have

Conventionally, this type of state transition circuit creates and holds a transition destination state based on the result and state obtained by decoding human data, and uses this together with the result of decoding input data to determine the next transition destination state. The method used was to create one. In this case, the state transition circuit is configured to use a decoder for decoding input data, a flip-flop and a counter for holding the transition destination state, etc., depending on the code type and state type of the input data. It had been.

[Problem to be solved by the invention]

In this way, the conventional state transition circuit has a structure in which a decoder for decoding input data and a flip-flop or counter for holding the state are used as necessary. Therefore, for example, when there are many types of codes or states of input data, the circuit configuration becomes large-scale and complicated, resulting in an increase in cost.

Another disadvantage is that if there is an error or change in the logic of the state transition flow, large-scale circuit changes are required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a state transition circuit that can be configured with a simple circuit and that can cope with errors or changes in the flow of state transitions without changing the hardware.

[Means to solve the problem]

In the present invention, (i) when current state display data representing the current state of the own system and data newly input from the outside are input to the address manual section, the next address specified by these data is (ii) a read-only memory that outputs transition destination state display data representing a future state to be transitioned to in an operation cycle;
A flip-flop that holds the transition destination state display data output from the only memory during the next operation cycle and supplies it to the address input section of the read-only memory as new current state display data for that operation cycle. The state transition circuit is equipped with the following.

In the present invention, at a certain point, the read-only
Memo 9 The transition destination state display data output from (ROM) is held for the next operation cycle, and this is R as the current state display data for the new operation cycle.
Give the address of OM to the human resources department. Based on this, this RO
M also outputs data indicating the next transition destination state.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows a state transition circuit in one embodiment of the present invention. This circuit is equipped with a ROMII that can be read in units of m bits, and its output terminal OUT outputs transition destination state display data 12 indicating the transition destination state.
It is designed to be output as bit parallel data. A state transition table created by associating states that the own system can take with addresses is written in advance in this ROMII.

The transition destination state display data 12 is input to the input terminal of a flip-flop 13 capable of latching m bits, and the current state display data 14 indicating the current state is output from the output terminal Q. This current state display data 14 is m-bit parallel data, and is inputted to address input terminals A+ and A2 of the ROM 1l, together with n-bit parallel input data 15 inputted every operation cycle. . Further, the flip-flop 13 is provided with a clock input terminal CLK and a clear input terminal CLR, so that a clock signal 16 and a clear signal 17 are input manually, respectively.

Next, an outline of the operation of the state transition circuit configured as described above will be explained with reference to FIG.

Initially, this circuit is in an initial state due to the clear signal 17 being input to the clear input terminal CLR of the flip-flop 13. After the input of this clear signal 17 is released, the human data 15 is transferred to the ROMII (Fig. 2a).
When input, data previously written as a state transition table is read out at the timing of a read signal (not shown) and output as transition destination state display data 12 (C in the figure). In the flip-flop 13, the clock signal 16 (
This transition destination display data 12 is held at the timing d) in the same figure, and the current state display data 1 is held in the next operation cycle.
4 (b in the same figure) is the address input terminal A of ROM11.
1. Manpower. By repeating this operation, state transitions will be performed sequentially.

FIG. 3 is for explaining the operation of this state transition circuit in detail.

First, while the clear signal 17 is being applied to the clear input terminal CLR of the flip-flop, the current state display data 14 output from the flip-flop 13 is in the initial state (step 2). After this clear signal 17 is released, the ROMII address input terminal A2
When the data Dz (Fig. 2 a) is given as the data 15 (step ■: Y), the current state display data 14 in the initial state and the manually input data D1 are used to obtain the following data.
The address where the data to be read is stored is specified. Then, reading is performed at the timing of a read signal (not shown), and the transition destination state display data 12 is state BS,
(C in the same figure). When the transition destination state display data 12 indicating this state gS is input to the input terminal of the flip 70 knob 13, the timing 1. of the clock signal 16 is input. is latched, and the current state display data 14 is also in state S, (b in the same figure)
Then (step ■), the data is input to the ROMII.

Here, when the next data D2 (a in the same figure) is input to the ROMII, reading is performed again at the timing of a read signal (not shown) in step ■: Y), and the transition destination state display data 12 is in the state S2 (in the same figure). C>. Then, when the transition destination state display data 12 indicating this state S2 is input to the input terminal of the flip-flop 13, it is latched at timing t2 of the clock signal 16, and the current state display data 14 also changes to the state S2. (Figure b) becomes (step ■
). This operation is repeated in the same way thereafter, and state transitions are performed sequentially. Naturally, for example, when data D is input, the state changes to the initial state (step There is also a case (step ■: N).

〔Effect of the invention〕

As explained above, according to the present invention, state transition is performed by using ROM, so it is possible to create states corresponding to the number of output bits of ROM with a simpler circuit configuration than in the past. be.

Therefore, there is an effect that the mounting area can be significantly reduced. In addition, even if there is an error or change in the state transition flow, R
Another advantage is that it can be corrected simply by changing the OM data.

[Brief explanation of drawings]

The drawings are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram showing a state transition circuit, and FIG. 2 is a timing diagram for explaining the operation of the state transition circuit shown in FIG. 1. , FIG. 3 is a flowchart for explaining the operation of the state transition circuit of FIG. 1. 11...ROM. 12... Transition destination state display data, 13...
...Flip-flop, 14...Current status display data, 15...
・Human power data.

Claims (1)

[Claims] When current state display data representing the current state of the own system and data newly input from the outside are input to the address input section, the next operation is performed from the address specified by these data. A read-only memory that outputs transition destination state display data representing a future state to be transitioned to in a cycle, and retains the transition destination state display data output from this read-only memory for the duration of the next operation cycle. and a flip-flop that supplies new current state display data in the operation cycle to an address input section of the read-only memory.