JPH0311437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to testing circuits for monolithic integrated circuits. Monolithic integrated circuits are generally equipped with test circuits to determine whether the integrated circuit itself is good or bad, and to make adjustments when combined with other elements. Conventionally, as an example of a method for creating this test mode, a test terminal 10 is provided as shown in FIG. 1, and the signal line 12 is connected to the -Vss side (Low level side,
Note that the Low level is hereinafter expressed as L level. )It is connected to the. When the test terminal 10 is floating, the gate potential 12 of the inverter 13, which is a buffer, is kept at L level by the MOS resistor 11, and the output potential 14 of the inverter 13 is set to +V _DD.
(High level side, High level is hereinafter expressed as H level). Furthermore, when the test terminal 10 is set to +V _DD (H level) by a low impedance signal source external to the integrated circuit, the potential of the signal line 12 becomes almost +V _DD ,
The output potential 14 of the inverter 13 becomes L level. As described above, in the conventional test circuit system, when focusing on the level of the signal line 14, only two states are created by one test terminal. The situation that only two states can be created for one test terminal remains the same even if the pull-down resistor 11 in FIG. 1 is replaced with a pull-up resistor. Therefore, if a large number of test modes are required, it is necessary to prepare a correspondingly large number of test terminals, but providing a large number of test terminals results in a large loss in terms of chip area for integrated circuits, and at the same time reduces the circuit block size. Since the number of pins is generally limited when assembling it into a package or package, it becomes a major obstacle.

In order to alleviate such problems, the present invention provides a method in which three states can be selected using one test terminal. The present invention provides, in an integrated circuit having a test terminal, a buffer that outputs a clock signal that periodically repeats potentials at a first level and a second level to an output terminal connected to the test terminal; a first holding circuit electrically connected to a test terminal and an output end of the buffer, inputting and holding a signal at the input end when the clock signal is at a first level; and a second holding circuit that is electrically connected to the output end of the buffer and receives and holds the signal at the input end when the clock signal is at a second level; The two output terminals of the holding circuit generate different types of signals within the integrated circuit depending on whether the test terminal is in an unconnected state to a substantial potential, a high potential level state, or a low potential level state. It is characterized by being output. FIG. 2 shows an example of the circuit, and this circuit example will be explained in detail below.

In the circuit diagram of FIG. 2, signal 106 is connected to the clock of frequency divider 27, and the output of frequency divider 27 is connected to the clock of frequency divider 28. Signal 110, one of the outputs of frequency divider 27, is connected to the gate of inverter 21. Inverter 21
The output 101 is connected to the terminal 26 and the latch circuits 22 and 23.
connected to data. A signal line 108, which is an internal signal of the frequency divider 27, is connected to the second gate of the NOR gates 24 and 25. Signal 110 is connected to the first gate of NOR gate 24. The signal line 111 that inverts the signal 110 is the NOR gate 2.
5 is connected to the first gate of No. 5. Signal 102 of NOR gate 24 is connected to the clock of latch 22. Signal 103 of NOR gate 25 is connected to the clock of latch 23.

The operation of the circuit shown in FIG. 2 will be explained below along with the timing chart shown in FIG. If the signal on the signal line 106 in FIG. 2 is a timing signal of Q _{N -2} in FIG. It comes out as a timing signal. This _N
The signal 110 is the inverter 21 which is a buffer.
The data signal is passed through the latch circuits 22 and 23 and becomes the data signal for the latch circuits 22 and 23. Therefore, when the terminal 26 is floating, the data signals of the latch circuits 22 and 23 are as shown in FIG.
Q serves as a timing signal for _N. Also signal 1
08 is the timing signal of _N-1 in FIG. 3, signal 110 is the timing signal of _N in FIG. 3, and signal 111 is the timing signal of Q _N in FIG. 3. Therefore, Noah Gate 24
The output signal 102 of the NOR gate 25 becomes the timing signal A in FIG.
This is the timing signal B in the figure. From the above, when the terminal 26 is floated, the data signals of the latches 22 and 23 are the timing signal _QN in FIG. 3, and the clock of the latch circuit 22 is the timing signal A in FIG. The clock of circuit 23 is the timing signal B in FIG. If we pay attention to the relationship between the Q _N signal and the A and B signals, we can see that when the A signal is at H level, Q _N
is at H level, and when the B signal is at H level, Q _N is always at L level. Therefore, terminal 2
6 is floating, the output signal of latch 22 is 10.
4 is always at the H level, and the output signal 105 of the latch 23 is always at the L level.

Next, when the terminal 26 is brought to an H level from outside the integrated circuit using a signal source with sufficiently lower impedance than the inverter 21, the signal 101, that is, the latches 22, 2
Since the data of 3 is always at H level, latch 2
The output signals 104 and 105 of 2 and 23 both become H level.

Furthermore, if the terminal 26 is set to L level externally using a signal source with sufficiently lower impedance than the inverter 21, the signal 101, that is, the data of the latches 22 and 23 will always be at the L level.
The output signals 104 and 105 of both become L level.

From the above, if we organize the states of the latches 22 and 23 inside the integrated circuit as 2 bits by making the H level correspond to 1 and the L level to 0, when the terminal 26 is floated... (1, 0) The terminal 26 is set to the H level. When the terminal 26 is set to the L level...(1, 1) When the terminal 26 is set to the L level...(0, 0). Therefore, one test terminal can create three states inside the integrated circuit, and three modes can be used as a test circuit.

The above has been explained using the circuit example shown in FIG. 2, but this is just an example, and the essence of the multi-mode test terminal circuit is that the inverter 21, which is a buffer, sends signals to the data at the terminal 26 and the latch circuits 22 and 23. When the data signal 101 of the latches 22 and 23 is sent and the terminal 26 is floated, it always goes to the H level when the clock signal 102 is at the H level, and always goes to the L level when the clock signal 103 is at the H level. It is a matter of choice, and as long as the timing relationship is maintained, it can be replaced with another circuit. FIG. 4 shows an example of a circuit other than the circuit shown in FIG. 2.

In the circuit shown in FIG. 4, the signal 207 is connected to the clock of a delay type flip-flop 37 having 2 bits. Signal 206 is connected to the data of delay flip-flop 37 and to the gate of inverter 31. Inverter 31
The output 201 is connected to the terminal 36 and the latch circuits 32 and 33.
connected to your data. A one-bit delay signal 208 of the delay type flip-flop 37 is connected to the first gate of the NOR gate 34. A 2-bit delay signal 210 of the delay type flip-flop 37 is connected to the first gate of the NOR gate 35. A signal 209 obtained by inverting the signal 208 is connected to the second gate of the NOR gate 35. Signal 211 obtained by inverting signal 210
is connected to the second gate of the NOR gate 34. The output signal 202 of NOR gate 34 is connected to the clock of latch circuit 32. The output signal 203 of NOR gate 35 is connected to the clock of latch circuit 33.

In this circuit configuration, the fifth line is connected to the signal line 207.
When the timing signal 207 in the figure and the timing signal 206 in FIG. 5 are applied to the signal line 206 from inside the integrated circuit, each circuit signal in FIG. 4 operates with the timing signal with the corresponding number in FIG. 5. At this time, as can be seen from the timing chart in FIG.
When the data signal 201 is at the H level, the data signal 201 is always at the H level. Further, when the gate signal 203 of the latch circuit 33 is at the H level, the data signal 201 is always at the L level. Therefore, for the same reason as when explaining the circuit operation in FIG.
The output of the latch circuit is 20 depending on whether it is floating, set to H level, or set to L level.
The states of 4,205 are (1, 0), (1, 1), (0,
0) can be created.

Note that the frequency dividing circuit 27, which was explained in FIG.
A concrete example of the circuit configuration of 28 is shown in FIG.

Further, a specific circuit configuration example of the latch circuits 22 and 23 in FIG. 2 and the latch circuits 32 and 33 in FIG. 4 is shown in FIG.

Further, a specific example of the circuit configuration of the 2-bit delay type flip-flop shown in FIG. 4 is shown in FIG.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional test terminal circuit, FIG. 2 is a diagram of an example of the circuit configuration of the present invention, FIG. 3 is a timing chart of the circuit shown in FIG. 2, and FIG. 4 is a diagram showing a second example of the circuit configuration of the present invention, FIG. 5 is a diagram showing a timing chart of the circuit of FIG. 4, and FIG. 6 is a diagram showing a timing chart of the circuit of FIG. 2. 7 is a diagram of a concrete circuit example of the latch circuit used in FIGS. 2 and 4, and FIG. 8 is a diagram of a concrete circuit example of the delay type flip-flop used in FIG. 4. FIG. 2 is a diagram of an example circuit. 21...Inverter that acts as a buffer,
22, 23... Latch circuit, 24, 25... Gate circuit composed of NOR, 26... Terminal, 27,
28... Frequency divider circuit, 104, 105... Output of latch circuit.

Claims (1)

[Claims] 1. In an integrated circuit having a test terminal, a buffer outputs a clock signal that periodically repeats potentials at a first level and a second level to an output terminal connected to the test terminal; and an input terminal. is electrically connected to the test terminal and the output terminal of the buffer, and inputs and holds the signal at the input terminal when the clock signal is at a first level; a second holding circuit electrically connected to a test terminal and an output end of the buffer, inputting and holding the signal at the input end when the clock signal is at a second level; The two output terminals of the second holding circuit are connected to different types of terminals within the integrated circuit depending on whether the test terminal is brought into an unconnected state to a substantial potential, a high potential level state, or a low potential level state. An integrated circuit characterized by outputting a signal.