JPH03109349U - - Google Patents
Info
- Publication number
- JPH03109349U JPH03109349U JP1990016235U JP1623590U JPH03109349U JP H03109349 U JPH03109349 U JP H03109349U JP 1990016235 U JP1990016235 U JP 1990016235U JP 1623590 U JP1623590 U JP 1623590U JP H03109349 U JPH03109349 U JP H03109349U
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- pin
- integrated circuit
- pad
- insertion hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の実施例を示す図、第２図はＩ
／Ｏピンを示す図である。
図において、１……ウエハ、２……ピン挿通孔
、３……Ｉ／Ｏピン、４……集積回路、５……Ｉ
／Ｏパツドである。
Figure 1 is a diagram showing an embodiment of the present invention, Figure 2 is an I
It is a figure which shows the /O pin. In the figure, 1... wafer, 2... pin insertion hole, 3... I/O pin, 4... integrated circuit, 5... I
/O pad.
Claims (1)
３を固定するとともに、該Ｉ／Ｏピン３に前記ウ
エハ１上に構成した集積回路４のＩ／Ｏパツド５
を接続してなるウエハスケール集積回路素子。 An I/O pin 3 is fixed to a pin insertion hole 2 drilled in the wafer 1, and an I/O pad 5 of an integrated circuit 4 formed on the wafer 1 is attached to the I/O pin 3.
A wafer-scale integrated circuit device formed by connecting .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990016235U JPH03109349U (en) | 1990-02-22 | 1990-02-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990016235U JPH03109349U (en) | 1990-02-22 | 1990-02-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03109349U true JPH03109349U (en) | 1991-11-11 |
Family
ID=31519515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990016235U Pending JPH03109349U (en) | 1990-02-22 | 1990-02-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03109349U (en) |
-
1990
- 1990-02-22 JP JP1990016235U patent/JPH03109349U/ja active Pending