JPH03108758A - Paired transistor and electronic circuit utilizing same - Google Patents

Abstract

PURPOSE:To obtain a circuit being free from an offset caused by drawing-in of a charge due to a feed-through error which is generated when a switch operates, by a method wherein input electrodes and paired control electrodes of first and second transistors are formed in the same dispositions and in parallel in the same direction on a semiconductor substrate. CONSTITUTION:A circuit is provided with a first transistor Tr 1 constructed of an input electrode 10 and a pair of control electrodes 7 and 8 formed on a semiconductor substrate 6, and a second transistor Tr 2 which has an input electrode 11 and a pair of control electrodes 9 and 13 disposed and shaped in the same way as the electrodes of the first transistor Tr 1 respectively and of which the paired control electrodes 9 and 13 are formed on the semiconductor substrate 6 separately from the paired control electrodes 7 and 8 of the first transistor Tr 1. According to this constitution, the parasitic capacities of sources/drains on the same side in respect to the input electrodes become equal. By connecting the sources/drains on the same side of the transistors, accordingly, paired transistors of which the parasitic capacities and parasitic resistances are disposed symmetrically and which have the same characteristics can be constructed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a pair of transistors formed, for example, in a semiconductor integrated circuit device, and particularly relates to an improvement in the electrode arrangement structure of the pair of transistors. The present invention also relates to various electronic circuits that utilize paired transistors having this electrode arrangement structure.

(Prior Art) Various analog circuits are known that utilize a pair of transistors in which a pair of transistors having the same characteristics are connected in parallel. One such analog circuit is, for example, a switched capacitor filter (SCF: 5w1t).
There is a ched capacitor filter) circuit.

In other words, this SCF circuit is a type of active filter circuit in which the resistance in a normal active filter circuit, which is composed of passive elements such as resistors and capacitors, and active elements such as transistors and operational amplifiers, is replaced by a switch and a capacitor. - It is well known that this circuit can perform the same function by replacing it with a capacitor (SC).

FIG. 20 is a circuit diagram of an SC circuit using such a pair of transistors as a switch.

That is, switch aXb is connected between input terminal 1 and output terminal 2.
are connected in series, and a connecting point 3 between switches a and b is grounded via a capacitor C. These switches a and b are composed of a pair of transistors using a pair of transistors having the same characteristics. Here, it is assumed that the switches a and b are alternately turned on and off by a control circuit (not shown).

Now, with voltage E applied to input terminal 1, if switch a is turned on and switch b is turned off, a charging current of 1 inch flows through capacitor C, and the capacitor C is charged to voltage E. Therefore, if the capacitance of the capacitor C is made small, the capacitor C will be charged in a very short time.
The charging current Iin immediately becomes zero. Next, when switch a is turned off and switch b is turned on, the capacitor C is discharged and the discharge current I out
flows to the output terminal 2, and eventually it is completely discharged and the discharge current 1out becomes zero.

Therefore, when the switches a and b are turned on and off repeatedly at a constant speed, the average value of the charging current Ijn and the average value of the discharging current I out become the same value. If this is considered over a sufficiently long period of time, the capacitor C viewed from the input side can be considered as a resistor through which a current exactly equal to the average value current (Iin or Iout) flows in an equilateral curve.

More importantly, assuming that the capacitance of capacitor C does not change, if the on/off speed of switches a and b is doubled, the average current value flowing will also be doubled. In other words, by controlling the on/off period, the average current value can be changed in the same way as the value of the equipolar resistance described above. For this reason, the SCF circuit, which cannot use resistors that have problems such as heat generation, is suitable for integrated circuits.
It is widely used in the field of semiconductor integrated circuit devices.

Next, FIG. 21 shows a circuit diagram of a pair of transistors used in the switches a and b described above. That is, the one-pole control electrode (drain) of the transistor Tri constituting the switch a and the other-pole control electrode (source) of the transistor Tr2 constituting the switch b are connected.

Further, the control electrode (source) of the other pole of the transistor Tri is input terminal 1, the control electrode (drain) of one pole of the transistor Tr2 is the output terminal 2, and the control electrode (drain) of the other pole of the transistor Tri
The connection points between ri and Tr2 are respectively connected to connection terminals 3 to which external capacitors C (not shown) are connected.

In addition, each input electrode (gate) of each transistor T rl and T r2 is supplied with clock pulses (φ, φ) having opposite phases to each other so that both transistors are alternately turned on and off. It is connected to input terminal 4.5.

In a paired transistor circuit with such a configuration, parasitic capacitance (
CMal, C as described later as Miller capacity)
Ma2, CMbl and CMb2 are present.

These parasitic capacitances will be explained below with reference to the drawings. FIG. 22 is a layout diagram of the SC circuit shown in FIG. 21 provided on an actual semiconductor substrate, and FIG. 23 is a sectional view taken along the line X--X in FIG. 22.

That is, the paired transistors constituting this SC circuit are formed by ion implantation into the semiconductor substrate 6.
A pair of source/drain injection layers 7, 8.9 which become the source or drain of T r2 are formed, and a gate electrode 10.11 is formed thereon with an insulating layer (not shown) sandwiched therebetween. Metal oxide semiconductor (MOS: Me
tal-Oxid-8eII11 conductor)
It is a type transistor. Due to this MO8 type structure, a parasitic capacitance exists between the injection layers 7, 8.9 and the gate electrode 1011. The parasitic capacitances are CMa1 between the injection layer 7 and the gate electrode 10, CMa2 between the gate electrode 10 and the injection layer 8, and CMb between the injection layer 8 and the gate electrode 11.
l, there is CMb2 between the gate electrode 11 and the injection layer 9; The capacitance value of these parasitic capacitances depends on the thickness of the insulating layer between the gate electrode 11 and the injection layer 7.
It is determined by the lateral overlap width m between the hood 11 and the injection layers 7, 8.9, etc.

In the MO8 structure pair transistor circuit described above, as shown in FIG. 21, a feedthrough error occurs due to the presence of the parasitic capacitance CMa2 when the switch a turns off from on, and the canister is connected. Charge flows into the connecting terminal 3. At the same time, the switch b turns on from off, drawing in the charge via the parasitic capacitance CMbl, and as a result, it is not output to the connection terminal 3.

That is, when the switches a and b operate, charges due to the feedthrough error cancel each other out and do not appear as an offset.

This arrangement has the advantage of being compact because the source/drain and wiring can be shared, and is also commonly used because it is easy to wire each terminal from the outside.

Further, FIG. 24 shows an SC circuit using two pairs of transistors. That is, a first pair of transistors a1 and bl are connected between the input terminal 1 and the ground, and a second pair of transistors a2 and b2 are connected between the output terminal 2 and the ground. In addition, the switch a
The connection point 3a between 1 and bl, and the connection point 3b between a2 and b2
A capacitor C is connected to. This circuit charges a capacitor C with the potential difference between the input terminal 1 and the output terminal 2, the charging current flows to the output terminal 2, and the current stops flowing when charging is completed later.

(Problem to be Solved by the Invention) The parasitic capacitances CMat and CMa2, or CMbl and C
The capacitance values of Mb2 are apparently the same. However, in reality, when forming an implanted layer by implanting ions into a semiconductor substrate, generally speaking, if the incident angle of the ions implanted perpendicularly to the semiconductor substrate is tilted, the gate electrode 10, 11 and the implanted layers 7, 8 Width p with ゜9
The positional shift occurs over the entire surface of the semiconductor substrate, which causes each parasitic capacitance to be different.

Here, taking the injection layer 8 as an example, the position shown by the broken line where the injection layer 8 is originally formed at the time of formation] 2 and the position of the injection layer 8 actually formed are as follows with respect to the gate electrode 10.11. Assuming that the position is shifted by a width p, comparing the parasitic capacitance cMa2 and CMbl, it is found that the gate electrode 1
0.11, the parasitic capacitance CMa2 having a larger area facing the injection layer 8 has a larger capacitance.

In this way, when the implanted ions, which should normally be incident perpendicularly to the horizontal plane of the semiconductor substrate, are incident at a slight angle when forming the implanted layers for the source/drain of a transistor, this inclination causes the implanted layers to become closer to the gate. On the other hand, positional deviation occurs in a certain direction. Therefore, the actual parasitic capacitances do not have the same capacitance value, and the charges generated due to the 1 refeed-through error due to the operation of the switches a and b cannot be captured completely. In other words, the charges cannot cancel each other out, and the charges synchronized with the clock pulse are transferred to the connection terminal 3.
feedthrough to. As a result, the charge feedthrough affects the output value and generates an output offset.

Furthermore, similar to such parasitic capacitance, parasitic resistances exist between each injection layer and the gate oxide film, and these parasitic resistances also become asymmetrical due to the positional deviation and affect current performance.

When the conventional paired transistors described above are used in various electronic circuits, offset voltages generated by feedthrough errors during the operation of the paired transistors tend to cause offsets in operational amplifiers and the like.

In the present invention, each transistor is formed so that each positional shift between the source/drain and gate is biased in the same direction,
Electrodes having the same parasitic capacitance and resistance are connected together to form a pair of transistors. The object of this invention is to provide a pair of transistors in which the charge due to the feed-through error that occurs when the switch is operated is drawn in, and no offset occurs.

A further object of the present invention is to provide various electronic circuits with reduced offset voltages by employing the paired transistors.

[Structure of the Invention (Means for Solving the Problems)] In order to achieve the above-mentioned object, the present invention provides that the input electrodes and the pair of control electrodes of the first and second transistors are arranged in the same manner and are the same on the semiconductor substrate. The first and second transistors form a pair of transistors that are arranged in a direction and are separately formed without sharing a control electrode, so that the first and second transistors have the same characteristics.

Furthermore, to solve the problem by providing a pair of transistors having a configuration in which one of the control electrodes on the same side as the input electrode of each of the first and second transistors is connected, and the other of each becomes an input/output terminal. I can do it.

3 Furthermore, the arrangement configuration of the paired transistors of the present invention can be applied to, for example, a switched capacitor circuit and a switched capacitor circuit.
A filter circuit, a sample and hold circuit,
The problem can be solved by applying it to electronic circuits such as chopper/comparator circuits and current mirror constant current circuits.

(Function) The first transistor formed in the arrangement of pair transistors as described above
The control electrodes of the transistor and the second transistor that are in the same direction with respect to the input electrode have the same parasitic capacitance, and are formed separately. This allows the offset voltage to be reduced as described above.

Furthermore, a pair of transistors having symmetrical parasitic resistances as well as the parasitic capacitances can be configured.

Furthermore, the arrangement configuration of the paired transistors of the present invention can be applied to electronic circuits such as switched capacitor circuits, switched capacitor filter circuits, sample-and-hold circuits, chopper comparator circuits, and current mirror constant current circuits. By applying this method to the above, each offset voltage can be reduced.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Figure 1 is a cross-sectional view showing the configuration of the pair transistors, Figure 2 is a plan view showing the arrangement of the pair transistors, and Figure 3 is a cross-sectional view showing the configuration of the pair transistors.
The figure is its circuit diagram.

That is, the transistor Tri constituting the switch a has an insulating layer (not shown) on the source/drain injection layers 7 and 8.
A gate electrode 10 is provided through the gate electrode. Similarly, the transistor Tr2 constituting the switch b does not share an injection layer with the transistor Tri, but is provided with source/drain injection layers 9 and 13, and a gate electrode 11 is provided thereon via an insulating layer (not shown). The settings are configured. Further, the input terminal 1 is connected to the injection layer 7.

The output terminal 2 is then connected to said injection layer 9, and the connection terminal 3 connected to a capacitor (not shown) is connected to both said injection layers 8.13.

In order to operate each transistor, clock pulses (φ, 7;) of opposite phases are supplied to the clock input terminal 4.5 connected to the gate 5 electrode 10.11.

In such a configuration, the transistor Tri has a parasitic capacitance CMal between the gate electrode 10 and the injection layer 7, and a parasitic capacitance fn CMg2 between the gate electrode 10 and the injection layer 8, as in the conventional case. have. Further, the transistor Tr2 has a parasitic capacitance i CMb2 between the gate electrode 11 and the injection layer 13, and a parasitic capacitance CMbl between the gate electrode 11 and the injection layer 9.

In this case, since each implanted layer is ion-implanted at the same time in the same process, the positions are shifted by the same distance with respect to the gate. Therefore, since the lateral overlap widths q and r with the injection layer on the same side with respect to the gate are equal, the parasitic capacitance CMa
and CMbl have the same capacity. Similarly, the parasitic capacity jtcMa2
and CMb2 have the same width of overlap in the lateral direction, so they have the same capacity.

That is, the arrangement of the paired transistors is such that the gate electrodes 10 and 11 formed in each transistor face each other in parallel, and the injection layer 8 of the transistor Tri and the injection layer 1 of the transistor Tr2 are arranged as shown in FIG.
3 to the connection terminal 3, the parasitic capacitances of the respective transistors connected to the connection terminal 3 become equal as described above.

Therefore, due to the feedthrough error that occurs when switch a is turned off from on, charges flow into the connection terminal 3 to which the capacitor is connected via the parasitic capacitance CMg2. At the same time, the switch b turns on from off, drawing in the charge through the parasitic capacitance CMb2 having the same capacitance as the CMg2.

Therefore, as a result, the charge is not output to the connection terminal 3. That is, the charges passing through due to the feed-through error of the parasitic capacitance parasitic to each gate can cancel each other out.

Further, the paired transistors can also be arranged as shown in FIG. 4, and a circuit diagram thereof is shown in FIG. That is, in this arrangement, the gate electrodes 10 and 11, which faced each other in parallel in FIG. Connected to 3. This circuit is a useful arrangement when incorporating a mirror circuit or the like.

In the pair transistor of the present invention, each injection layer and each gate electrode may be arranged as described above, and it goes without saying that the wiring can be changed as appropriate depending on various applications.

Such paired transistors according to the present invention have various applications. Some of these applications will be explained below with reference to the drawings. As a first application example, FIG. 6 is a layout diagram in which a pair of transistors according to the present invention is employed in a sample-and-hold circuit (hereinafter abbreviated as S/H circuit), and FIG. 7 is a circuit diagram thereof. Further, for comparison with the S/H circuit applied to the present invention, a layout diagram of a conventional S/H circuit is shown in FIG. 8, and a circuit diagram thereof is shown in FIG. 9.

That is, the conventional S/H circuit shown in FIGS. 8 and 9 uses a pair of transistors T rl configuring switches a and b.
, T r2 share the injection layer 14, and this injection layer 14
is grounded via a hold capacitor C1. This S/H circuit has a parasitic capacitance CMd between the injection layer 14 and the gate electrode 15 of the transistor Tri, a parasitic capacitance CMel between the gate electrode 16 of the transistor Tr2 and the injection layer 14, and a parasitic capacitance CMel between the gate electrode 16 and the injection layer 14. 17 and has a parasitic capacitance CMe2.

In an S/H circuit with such a configuration, Sui-Sochi a (
When the transistor TrL) is turned off, the parasitic capacitance C
Charge due to a clock feedthrough error caused by the presence of Md jumps into the hold capacitor C1 and is charged to the hold voltage. At the same time, switch b is turned on and a certain amount of charge is drawn into the clock pulse input terminal 5 from the hold voltage through the parasitic capacitors icMel and CMe2 due to a clock feedthrough error that occurs due to the presence of the parasitic capacitors CMel and CMe2. . Therefore, the voltage of the output hold voltage drops.

Furthermore, when switch b (transistor Tr2) is turned off, charges due to a clock feedthrough error caused by the presence of parasitic capacitance fficMe2 flow into output terminal 2, causing an error in the actual hold voltage.

On the other hand, FIGS. 6 and 7 show S/H circuits that employ the pair transistor arrangement of the present invention and add a dummy transistor Tr3.

In other words, this S/H circuit consists of the pair I and I in FIG.
In this arrangement, a dummy transistor Tr3 is inserted between the transistors, and their gate electrodes 15 and 16 are arranged in a straight line. In other words, the gate electrode 15 is arranged in a straight line with the gate of the transistor Tr3, which receives the clock pulse φ having the same phase as the gate of the transistor Tri connected to the input terminal, and the gate electrode 15 is arranged in a straight line on the extension of the gate electrode 5. The gate electrodes of Tr2]6 are arranged so that they are lined up. Further, the drain of the transistor Tri and the source of the transistor Tr2 are connected, and they are grounded via the hold capacitor C1.

Furthermore, the drain 17 of the transistor Tr2 is connected to the output terminal 2.
It is also connected to the source 18 of the dummy transistor Tr3.

0 In the S/H circuit with such a configuration, the transistor Tri
The parasitic capacitance CMd between the gate and drain of transistor Tr2 and the parasitic capacitance CMeL between the gate and source of transistor Tr2 have the same capacitance value.
The gate-source parasitic capacitance fficMc has the same capacitance value.

Therefore, since the parasitic capacitances have the same capacitance value, this S/H circuit dissipates the same amount of charge as the amount of charge that causes a clock feedthrough error due to the presence of the parasitic capacitance when switches a and b turn on/off. The feedthrough charge can be canceled out.

Next, FIG. 10 shows the relationship between the output waveforms 0UTI and 0UT2 of the output hold voltages output from the output terminal 2 of the S/H circuits in FIGS.
FIG. 3 is a waveform diagram showing changes in the input voltage VIN.

As can be seen from the waveform 0UTI, in conventional S/H circuits, when the clock pulse φ supplied from the clock input terminal 4 to the gate changes from high (H) to low (L), the transistor Trl turns off. Due to the presence of the parasitic capacitance QCMd, charges generated due to a clock feedthrough error jump into the hold capacitor C1 via the capacitance CMd. At the same time, the transistor Tr2 is turned on, and due to the presence of the parasitic capacitance icMel, the hold capacitor C
If the charge due to the feedthrough error is drawn from the hold voltage of 1, and the capacitances of the capacitance Cgd and CMel become equal, the difference in charge becomes the output hold voltage 0UTI.
is output as an error.

Further, when the clock pulse φ changes from low (L) to no\ (H), the transistor Tr2 turns off from on, and due to the presence of the parasitic capacitance CMel, charge is drawn in due to a clock feedthrough error, and the output hold voltage becomes 0.
UTI drops.

However, as shown in FIGS. 6 and 7, the pair transistor arrangement of the present invention is adopted, and the transistor Tr
A dummy transistor Tr3 is placed on the injection layer 17 side of the drain of No.2.
By adding the parasitic capacitance 2, the capacitance difference between fficMd and CMel and CMc2 and CMc becomes small (and all feedthrough charges are drawn into the opposing parasitic capacitance, so as seen in the output hold voltage waveform 0UT2, the hold No error occurs in the voltage value.Furthermore, since the feed-through charge that enters the output via the parasitic capacitance fficMe2 is drawn in by the capacitor CMc added to the circuit, no voltage drop occurs in the hold voltage of the output 2.

Furthermore, as a second application example of the paired transistors of the present invention, a circuit diagram of a chopper/comparator circuit is shown in FIG. That is, in this circuit, the gate of the transistor Tr4 is connected to the input terminal to which the first clock signal φ1 is input, and the source is connected to the input terminal 18 to which the input signal is supplied. Also, the gate of the i-transistor Tr5 is the second one.
The clock signal φ2 is connected to the input terminal, and the source is connected to one input terminal to which the input signal is supplied. These transistors T r4. Both drains of T r5 are commonly connected and connected to the inverting amplifier 21 via a capacitor C2. Further, the source and drain of a transistor Tr6 are connected in parallel between the input and output terminals of the inverting amplifier 321. Further, the source of a dummy transistor Tr7 is connected to the drain of the transistor Tr6.

The transistor Tr6 has a parasitic capacitance NCMr between its gate and drain, and when it is turned on by the third clock pulse φ3, it bypasses the inverting amplifier 21 on the circuit and becomes conductive.

Further, when the transistor TrG is turned off, the inverting amplifier 21 becomes in a state where it can perform comparison.

At this time, charges are generated due to clock fit-through errors due to the presence of each ffi CMf. In other words, the charge fed through to the capacitor C2 via each fficMf may flow into the inverting amplifier 21 and become an input offset voltage.

Therefore, in order to prevent the feedthrough charge from jumping into the capacitor C2, the source of the dummy transistor Tr7, which has an injection layer formed in the same arrangement as the paired transistors described above, is connected to the drain of the transistor Tr6. 4 Do it. Parasitic capacitance C of this dummy transistor Tr7
Mg has the same capacitance value as the capacitance CMf, and has the same capacitance value as the capacitance CMf.
When transistor Tr6 is turned off, each of the above fflcMr
It is possible to prevent the input offset from occurring by injecting the charge that has passed through the clock feedthrough.

Further, as a third application example of the paired transistor of the present invention,
1] n-bit parallel comparison type A/D conversion (Δnalog to
A digital converter circuit is shown in FIG. This method is the fastest A/D conversion circuit that can digitize input signals almost instantaneously.

That is, the encoding circuit 22 in the A/D conversion circuit
n chopper comparators 231232,...2
Connect 3n in parallel. In particular, chopper comparators are required to have the same performance (characteristics). In particular, if the offsets differ from one another, the accuracy of A/D conversion will be affected. In other words, it is necessary to equalize the parasitic capacitance between the gate and source/drain of the transistors used in each converter, and to make the offset 5 the same.

Therefore, in order to equalize the parasitic capacitance, the parallel comparison type A/D conversion circuit unifies the pattern shape of each comparator formed on the semiconductor substrate, and arranges the comparators in the same direction as in the old pair transistor described above. Align. This suppresses variations in offset between comparators and further improves the accuracy of A/D conversion.

Next, as a fourth application example of the paired transistor of the present invention, an integrating circuit employing the above-mentioned SC circuit is shown in FIG. This circuit consists of a first pair of transistors A consisting of transistors Tri and Tr2, and transistors Tr4 and Tr.
A second pair of transistors B consisting of 5 transistors is connected via a capacitor C2.

Also, the transistor Tr of the first pair of transistors A
J is connected to the negative (-) input terminal of the operational amplifier 26, and this negative input terminal and the output terminal of the operational amplifier 26 are connected via a capacitor C3.

Further, the positive (+) input terminal of the operational amplifier 26 and the drains of the transistors Tr2 and Tr5 are connected to the reference potential 6. The source of the transistor Tr4 is used as an input terminal 24, and the output terminal of the operational amplifier 26 is used as an output terminal 27.

In the integrating circuit having such a configuration, the transistor Tr
There is a parasitic capacitance ffic between the gate 28 and drain 29 of i.
MAi, a parasitic capacitance i between the gate 28 and the source 30;
cMA2, similarly the gate 31 of the transistor Tr2
A parasitic capacitance ffi CMBI exists between the drain 32 and the drain 32 . The capacitors fficMA1 and CMBI have the same capacitance value by arranging the transistors in the same direction.

Therefore, when the transistor Tri is turned off, the charge generated due to a clock feedthrough error due to the presence of the parasitic capacitance CMAI is canceled by being drawn into the capacitor CMBI. However, when the transistor Tri is turned on/off, the charge generated due to a clock feedthrough error due to the presence of the parasitic capacitance CMA2 flows into the capacitor C3 and is offset.

Therefore, the waveform of the clock pulse "φ" supplied to the gate 28 of the transistor Tr.1 and the clock pulse "φ" supplied to the gate 28 of the transistor Tr.
FIG. 14 shows the waveform of the output offset voltage "φゞ" of the charge generated due to the foot-through error. As shown in this figure, the voltage (1) which becomes the output offset is mainly caused by the capacitance C
Due to MA2, only the charge generated due to the clock feedthrough error is generated.

As a fifth application example of the paired transistor of the present invention, the first
In order to constantly reduce the offset voltage V1 in Figure -4,
FIG. 15 shows an integrating circuit in which a dummy transistor is added to the configuration shown in FIG. 13.

This integrating circuit has a parasitic capacitance f with the same capacitance as the parasitic capacitance fficMA2 at the imaginary ground point 33 of the integrating circuit configured as described above.
I transistor Tr formed to have ficMh
The drain 34 of transistor Tr8 is connected, and the source 35 of this transistor Tr8 is made independent and set to a floating potential.

Note that the transistor Tr8 is supplied with a clock pulse having the same phase as that supplied to the transistor Tr2 to its gate 36, and is turned on/off at the same time as the transistor Tr2.

In other words, the integration circuit draws the charge generated by the clock feedthrough error into the capacitor fi CMh by the parasitic capacitance fficMA2 when the transistor 8Tri is turned off, so that the output offset voltage V1 is further reduced and offset can be prevented. .

The above describes an application example of the paired transistor of the present invention that solves the problem caused by the asymmetry of parasitic capacitance between the gate and source and between the gate and drain of each transistor in the paired transistor. The asymmetry of the parasitic resistance that exists at the same time as the parasitic capacitance given can also be solved by using the above-described arrangement of paired transistors of the present invention. Hereinafter, other application examples of the transistor of the present invention will be explained with emphasis on this parasitic resistance.

FIG. 16 is a circuit diagram of a current mirror constant current circuit as a sixth application example of the paired transistors of the present invention, and FIG. 17 is a layout diagram thereof.

This current-mirror constant current circuit employs the arrangement of paired transistors of the present invention, but the wiring is different from the two circuits described above in FIGS. 2 to 5. That is, P
The gates of channel 1 to transistor Tr9 are connected to current source 1 and its drain 37, and also connected to the gate of P-channel transistor T10.

Further, the source of each transistor is connected to a reference potential, and the drain 38 of the transistor Trlo is connected to three current output terminals. In this case, the I transistor T
r9, Trl, and O are parasitic resistances (sos resistances) with the same resistance value between the source and gate, respectively; Rsa,
Rsb, which is shown in the circuit diagram as a resistor connected between each source and a reference potential.

In a conventional current mirror circuit using a pair of transistors, both source resistances do not have the same resistance value, so there is a difference between each transistor, and the current I2 output to the output terminal is the same as the current 1 from the current source. There were cases where the value was not reached. However, by arranging the source, drain, etc. forming the transistor in the same manner as in the paired transistor of the present invention described above, the source resistance is set to Rsa=Rsb, and each source voltage is made to be at the same potential, and the current J2 can be brought close to the current J1.

As a seventh application example of the paired transistor of the present invention, the first
FIG. 18 shows a differential amplifier circuit including the current-mirror constant current circuit shown in FIG. That is, this amplification circuit includes a differential amplification stage 40 consisting of n-channel transistors Trll, TrJ, 2, and transistors Tr9. It is added to the drain side of transistor T rlo and output is obtained from the drain of transistor T r12.

Here, Trl,1 and Tr12 of the transistors are:
It has source resistances Rsc and Rsd which are parasitic resistances between it and the power supply Vdd, and the transistors Tr9 and Trl
O is the sos resistance Rsa which is a parasitic resistance as described above.
, Rsb between the reference potential and the reference potential.

Therefore, by arranging and configuring the transistors T rll and T r12 like a pair of transistors according to the present invention, the resistance values of the source resistors RSc (!: Rsd) can be made equal, and thereby the amplifying power stage 40 It is possible to suppress the offset voltage generated in the

Further, as an eighth application example of the paired transistors of the present invention, FIG. 19 shows a differential amplifier circuit in which the differential amplifier circuit of FIG. 18 is shaped like an inverted boat. This differential amplifier circuit is used in the differential amplifier output stage 42 in which the N channel of the transistor in the amplifier circuit stage 40 described above is replaced with a P channel, and the direction of current flowing is reversed, and in the constant current circuit 41 described above. This is a differential amplifier circuit consisting of a current mirror constant current circuit 43 in which the P channel of the transistor is replaced with an N channel and the direction of current flowing is reversed. Even with this configuration,
By arranging each transistor in the paired transistor configuration of the present invention, the same effect as the circuit shown in FIG. 17 can be obtained.

In addition, it goes without saying that the paired transistors of the present invention can be modified and applied in various ways without departing from the gist of the present invention.

2 [Effects of the Invention] Since the present invention is configured as explained above, it produces the effects as described below.

In other words, in the paired transistors of the present invention, the control electrodes (source/drain) are arranged in the same direction and individually, so that the source/drain on the same side with respect to each input electrode (gate) is free from the parasitic The capacitance becomes the same capacitance value. Therefore, by connecting the sources and drains of the transistors on the same side, it is possible to configure a pair of transistors in which the parasitic capacitance and the parasitic resistance are arranged symmetrically and have the same characteristics.

The pair of transistors can draw in and cancel charges generated by clock field errors associated with switching operations.

When this pair of transistors is applied to various electronic circuits,
The offset voltage that affects these circuits can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a pair of transistors formed on a semiconductor substrate as a first embodiment of the present invention, and FIGS. 2 and 3 are layout diagrams of the paired transistors, respectively. 4 and 5 are layout diagrams and circuit diagrams, respectively, of a pair of transistors as a second embodiment of the present invention, and FIGS. 6 and 7 are a sample diagram and a circuit diagram, respectively, as a first application example. and hold (
Figures 8 and 9 are layout diagrams and circuit diagrams in which the paired transistors of the present invention are applied to S/H) circuits, respectively, and Figure 1 is a layout diagram and circuit diagram of a conventional S/H circuit for comparison.
Figure 0 is a waveform diagram of the hold voltage of the S/H circuit, No. 31.
The figure is a circuit diagram in which the paired transistor of the present invention is applied to a chopper/comparator circuit as a second application example.
The figure is a circuit diagram in which the paired transistor of the present invention is applied to a chopper/comparator circuit as a third application example.
The figure is a circuit diagram of an integrating circuit to which paired transistors of the present invention are applied as a fourth application example, FIG. 14 is a waveform diagram of the clock supplied to the transistors of the integrating circuit and the output offset voltage, and FIG. 16 and 17 are circuit diagrams in which the paired transistors of the present invention are applied to the integration circuit described above as an application example, and FIGS. Applied circuit diagram and layout diagram, No. 18
The figure is a circuit diagram of a differential amplifier in which a differential input stage is provided in the current mirror constant current circuit as a seventh application example.
The figure is a circuit diagram of a differential amplifier circuit in which the channels of the transistors of the current mirror constant current circuit are changed and the direction of current flowing is reversed as an eighth application example. Figure 20 illustrates a conventional pair of transistors. The first example used to
21 and 22 are respectively a circuit diagram and a layout diagram of a conventional pair transistor, FIG. 23 is a cross-sectional view of the structure of a conventional pair transistor formed on a semiconductor substrate, and FIG. 24 is a block diagram of the SCF circuit of The figure is a block diagram of a second SC circuit taken as an example to explain a conventional pair transistor. 2... Output terminal, 3... Connection point, 4, 5... Input electrode (gate), 6... Semiconductor substrate, 7, 8, 9°5 13... Control electrode (source and drain) )26 ・
・・Operational amplifier, CMal, ・CMa2. CMbl
, CMb2--parasitic capacitance, Trl, Tr2. T
r3. Try, Tr7. Tr8゜Tr9.
TrlO, Trll, Trl2- l□ runcista.

Claims (8)

[Claims] (1) A first transistor consisting of an input electrode and a pair of control electrodes formed on a semiconductor substrate, and an input electrode and a pair of control electrodes having the same arrangement and shape as each electrode of the first transistor. a pair of electrodes, the pair of control electrodes being separated from the pair of control electrodes of the first transistor and a second transistor formed on the semiconductor substrate; transistor. (2) A pair of transistors according to claim (1) is adopted, and one pole of the control electrode on the same side as the input electrode of each of the pair of transistors is connected in common, and the other side of the control electrode is connected to the opposite side of the pair of transistors. 1. A switched capacitor, wherein the other electrode of each control electrode is connected to an input/output terminal, and the commonly connected connection point is connected to a reference potential via a capacitor. (3) The switched capacitor according to claim (2) is employed, and a differential input stage connected to the capacitor of the switched capacitor, and a differential amplifier connected to the switched capacitor. An integrating circuit comprising: an operational amplifier whose negative input terminal is connected to the other pole of the control electrode of the first transistor and whose positive input terminal is grounded. (4) In the integrating circuit according to claim (3), one pole of the control electrode of the third transistor having the same parasitic capacitance as the other pole of the control electrode of the first transistor has the other pole. An integral circuit characterized by being connected to a pole. (5) The switched capacitor according to claim (2) is adopted, and the capacitance is the same as the parasitic capacitance of the other electrode of the control electrode of the first transistor of the switched capacitor connected to the output terminal. A sample-and-hold circuit, characterized in that one pole of a control electrode of a third transistor having a parasitic capacitance of a value of 0.05 is connected to the other pole. (6) The switched capacitor according to claim (2) is employed, and the other electrode of the control electrode of the first transistor of the switched capacitor is set to a floating potential, and the voltage of the first and second transistors is set to a floating potential. A chopper comparator, characterized in that one pole of each is connected to a capacitor and an input end of an inverting amplifier, and the other pole of the control electrode of the second transistor is connected to an output end of the inverting amplifier. (7) A pair of transistors according to claim (1) is employed, wherein the other electrode of the control electrode of the first transistor of the pair of transistors is connected to a reference current source serving as an input signal, and the second transistor The other pole of the control electrode on the same side as the other pole of is connected to a current output terminal, one pole of each of the first and second transistors is grounded, and each input electrode is connected to the reference current source. A current mirror circuit characterized by: (8) A current mirror circuit according to claim (7), and a differential input stage in which each electrode is formed in the same arrangement as a pair of transistors used in the current mirror circuit. Differential amplifier.