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JPH03107326A - Power supply - Google Patents

Power supply

Info

Publication number
JPH03107326A
JPH03107326A JP24263089A JP24263089A JPH03107326A JP H03107326 A JPH03107326 A JP H03107326A JP 24263089 A JP24263089 A JP 24263089A JP 24263089 A JP24263089 A JP 24263089A JP H03107326 A JPH03107326 A JP H03107326A
Authority
JP
Japan
Prior art keywords
current
load
value
power supply
abnormal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24263089A
Other languages
Japanese (ja)
Inventor
Koji Watanabe
渡辺 耕治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP24263089A priority Critical patent/JPH03107326A/en
Publication of JPH03107326A publication Critical patent/JPH03107326A/en
Pending legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)
  • Protection Of Static Devices (AREA)

Abstract

PURPOSE:To protect a load by measuring with a timer the time when the load current detected by a current detector has a specified value larger than the normal value but yet smaller than the abnormal value to be cut off, and interrupting the power supply if the condition has continued for a specified time. CONSTITUTION:An AC power source is connected to a load 1 through a power supply stabilizing circuit 2, a current detecting resistor 3, and an interrupting circuit 4. The voltage drop across the current detecting resistor 3 is amplified with an amplifier 5, and it is inputted to the A/D conversion port 7 of a microcomputer 6. And, if the load current has an abnormal level requiring interruption of the power supply, the interrupting circuit 4 is operated immediately. When the load current has a specified value higher than the normal value but lower than the abnormal value, the value is inputted to a memory 9 and a timer 8 starts. If the current of the specified value continues until the timer 8 reaches a specified value, an output of the microcomputer 6 lets the interrupting circuit 4 to operate. And, this prevents the heat generation from a load such as solenoids, transistors, capacitors, etc., and consequently prevents smoking and firing.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は電子機器等に用いられる電源回路に係り、更
に詳しくは電子機器等の負荷に電流を供給した際、その
負荷の異常状態に応じて供給電流の遮断を制御する電源
回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power supply circuit used in electronic equipment, etc., and more specifically, when supplying current to a load of electronic equipment, etc., it responds to an abnormal state of the load. This invention relates to a power supply circuit that controls the interruption of supply current.

[従 来 例] 従来、この種の電源回路は負荷の変動等に対して出力電
流が安定化する回路構成になっており、またこの電源回
路にはその負荷に異常電流が流れるのを防止するために
、異常電流の検出回路や出力制限の回路あるいは遮断回
路が備えられている。
[Conventional example] Conventionally, this type of power supply circuit has a circuit configuration that stabilizes the output current against load fluctuations, etc., and this power supply circuit also has a circuit configuration that prevents abnormal current from flowing to the load. Therefore, an abnormal current detection circuit, an output limiting circuit, or a cutoff circuit is provided.

すなわち、負荷電流が異常値になったときには、負荷に
供給する電流を制限し、あるいはその電流をシャットO
FF L、、負荷を保護している。
In other words, when the load current reaches an abnormal value, the current supplied to the load is limited or the current is shut down.
FF L, protecting the load.

[発明が解決しようとする課題] ところで、上記電源回路あっては、例えば異常。[Problem to be solved by the invention] By the way, if there is an abnormality in the above power supply circuit, for example.

電流の設定値を負荷変動の最大値に対応して決めている
ため、負荷変動に対する応答性に問題がああった。すな
わち、上記負荷としてのソレノイドやトランジスタ等の
通電時間が規定時間幅を越えている場合でも、検出電流
が異常値に達しないこともあり、またコンデンサの逆接
続により余分な電流が流れる場合がある。このような場
合、そのソレノイド、トランジスタやコンデンサ等に必
要以上の電流が流れてしまい、それらの発熱による発煙
や発火を招くとともに、それら部品が破損することにな
る。
Since the current setting value was determined in accordance with the maximum value of load fluctuation, there was a problem with responsiveness to load fluctuation. In other words, even if the energization time of the solenoid, transistor, etc. as the load mentioned above exceeds the specified time range, the detected current may not reach the abnormal value, and extra current may flow due to reverse connection of the capacitor. . In such a case, more current than necessary flows through the solenoids, transistors, capacitors, etc., causing smoke and ignition due to the heat generated by them, and damage to these parts.

この発明は上記課題に鑑みなされたものであり。This invention was made in view of the above problems.

その目的は負荷の各電子部品を保護し、かつ、負荷の異
常状態に応じて電源断を判断することができるようにし
た電源回路を提供することにある。
The purpose is to provide a power supply circuit that protects each electronic component of a load and that can determine whether to turn off the power depending on an abnormal state of the load.

[問題点を解決するための手段] 上記目的を達成するために、この発明は、負荷に電流を
供給し、かつ、この電流を検出するとともに、この検出
電流が異常値に達したときには前記供給電流の出力を制
限し、あるいは上記供給電流を遮断する電源回路におい
て、上記検出電流が上記異常値より低い所定値に達して
いる時間を計測するタイマ手段と、上記検出電流と上記
所定値とを比較し、かつ、上記計測時間と所定時間とを
比較し、この比較結果に応じて上記電流の遮断を制御す
る制御手段と、上記所定値および所定時間を記憶してい
る記憶手段とを備えていることを要旨とする。
[Means for Solving the Problems] In order to achieve the above object, the present invention supplies a current to a load, detects this current, and when the detected current reaches an abnormal value, the supplied current is In a power supply circuit that limits the output of current or cuts off the supply current, a timer means for measuring the time during which the detected current reaches a predetermined value lower than the abnormal value; and a control means for comparing the measured time and a predetermined time and controlling cutoff of the current according to the comparison result, and a storage means for storing the predetermined value and the predetermined time. The main point is that

また、この発明は、上記記憶手段には上記所定値および
所定時間に代え、上記負荷の状態に対応してその所定値
および所定時間のパターンを種々記憶しておき、上記検
出電流と計測時間によるパターンと上記記憶手段のパタ
ーンとを比較し、この比較結果により前記負荷の異常状
態を判断し。
In addition, in the present invention, instead of the predetermined value and predetermined time, the storage means stores various patterns of the predetermined value and predetermined time corresponding to the state of the load, and The pattern is compared with the pattern in the storage means, and the abnormal state of the load is determined based on the comparison result.

上記供給電流の遮断を制御するようにしたものである。The cutoff of the above-mentioned supply current is controlled.

[作  用] 上記構成としたので、負荷が正常状態でない場合、例え
ばリーμの通電時間が規定時間を越えていたり、コンデ
ンサが逆接続されている場合、負荷電流が異常値に達し
ていない場合がある。このとき、上記検出電流が所定値
(異常値より低い値)に達すると、この所定値に達して
いる時間が上記タイマ手段にて計測される。また、その
検出電流値および計測時間とが上記記憶手段に記憶され
ている値と比較され、この比較結果により負荷が異常で
あるか否かが判断される。そして、負荷が異常である場
合には、負荷に供給する電流が断状態にされる。
[Function] With the above configuration, if the load is not in a normal state, for example, if the energization time of Lee μ exceeds the specified time, if the capacitor is reversely connected, or if the load current has not reached an abnormal value. There is. At this time, when the detected current reaches a predetermined value (a value lower than the abnormal value), the timer means measures the time during which the detected current reaches this predetermined value. Further, the detected current value and the measured time are compared with the values stored in the storage means, and it is determined whether or not the load is abnormal based on the comparison result. If the load is abnormal, the current supplied to the load is cut off.

そこで、予め負荷の異常状態に応じた電流値およびその
電流が流れている時間データを上記記憶手段に記憶して
おけば、負荷電流が異常値に達していないが、上述した
ように負荷が異常状態になっている場合電源を断にする
ことができ、負荷を保護することができる。
Therefore, if the current value corresponding to the abnormal state of the load and the time data for which the current is flowing are stored in the storage means in advance, the load current does not reach the abnormal value, but the load is abnormal as described above. If this occurs, the power can be turned off to protect the load.

[実 施 例] 以下、この発明の実施例を図面に基づいて説明する。[Example] Embodiments of the present invention will be described below based on the drawings.

図において、電源回路には、負荷1に電圧を印加し、そ
の負荷に電流を供給する電源安定化回路2と、その電流
を検出するための抵抗3と、上記負荷1に供給する電流
を遮断する遮断回路4と。
In the figure, the power supply circuit includes a power supply stabilization circuit 2 that applies voltage to a load 1 and supplies current to the load, a resistor 3 for detecting the current, and a resistor 3 that cuts off the current supplied to the load 1. With the cutoff circuit 4.

上記抵抗3の電圧降下分を増幅する増幅器5と、この増
幅電圧をディジタル変換して検出電流のデータとし、こ
の検出電流と所定値aとを比較し、かつ、その電流が流
れている時間と所定値tとを比較し、この比較結果によ
り負荷1の異常状態を判断して上記遮断回路4を制御し
て上記負荷電流を遮断する制御回路6とが備えられてい
る。そのため、制御回路6としては、例えばA/D変換
変換ポート上びこのA/D変換変換ポート上した検出電
流が所定値以上に達している時間を計測するタイマ8を
有するマイクロコンピュータである。
An amplifier 5 that amplifies the voltage drop across the resistor 3, converts this amplified voltage into digital data to use as detected current data, compares this detected current with a predetermined value a, and calculates the time during which the current is flowing. A control circuit 6 is provided which compares the load current with a predetermined value t, determines an abnormal state of the load 1 based on the comparison result, and controls the cutoff circuit 4 to cut off the load current. Therefore, the control circuit 6 is, for example, a microcomputer having a timer 8 for measuring the time during which the detected current flowing through the A/D conversion port and the A/D conversion port reaches a predetermined value or more.

また、このマイクロコンピュータには上記所定値aおよ
び所定時間tを記憶するメモリ9と、この記憶所定値a
と検出電流との比較し、かつ、上記所定値tとタイマ8
の時間と比較する比較手段とが備えられている。
Further, this microcomputer includes a memory 9 for storing the predetermined value a and the predetermined time t, and a memory 9 for storing the predetermined value a and the predetermined time t.
and the detected current, and also compare the above predetermined value t and the timer 8.
Comparison means are provided for comparing the time.

ここで、電源回路にAC電源が供給され、この電源回路
にて電圧が負荷1に印加されているとき。
Here, when AC power is supplied to the power supply circuit and a voltage is applied to the load 1 in this power supply circuit.

何等かの原因により負荷1のソレノイド等の通電時間が
規定時間以上になってたり、コンデンサが逆接続されて
いるものとする。このとき、その負荷1の電流が抵抗3
および増幅器5により検出され、この検出電流が制御回
路6にてディジタル変換されるとともに、この検出電流
のデータとメモリ9の所定値aとの比較が実行されてい
る。なお、所定値aとしては負荷の異常状態時の値が設
定される。
Assume that for some reason the energization time of the solenoid, etc. of load 1 is longer than the specified time, or that the capacitor is reversely connected. At this time, the current of load 1 is
This detected current is digitally converted by the control circuit 6, and the data of this detected current is compared with a predetermined value a in the memory 9. Note that the predetermined value a is set to a value when the load is in an abnormal state.

続いて、その検BJl電流が所定Maに達すると。Subsequently, when the detected BJl current reaches a predetermined value Ma.

タイマ8が作動され、このタイマ8の時間と所定時間t
との比較が実行される。さらに、その所定時間tが経過
するまで、上記検出電流と所定値aとの比較が実行され
る。そして、上記所定時間tの経過後にあっても、例え
ば上記検出電流が継続して所定値aに達している場合に
は負荷が異常状態であると判断し、負荷1に供給する電
流を遮断するための制御信号が遮断回路4に出力される
The timer 8 is activated, and the time of this timer 8 and the predetermined time t
A comparison is performed. Furthermore, the comparison between the detected current and the predetermined value a is performed until the predetermined time t has elapsed. Even after the predetermined time t has elapsed, for example, if the detected current continues to reach the predetermined value a, it is determined that the load is in an abnormal state, and the current supplied to the load 1 is cut off. A control signal for this is output to the cutoff circuit 4.

すると、遮断回路4にて負荷1の供給電流が遮断され、
上記ソレノイドやコンデンサ等の通電が停止されるため
、そのソレノイドやコンデンサ等の発熱を防止し、発煙
や発火が起こることもない。
Then, the supply current to the load 1 is cut off by the cutoff circuit 4,
Since the energization of the solenoid, capacitor, etc. is stopped, heat generation in the solenoid, capacitor, etc. is prevented, and smoke and ignition do not occur.

なお、上記実施例は従来例の異常電流検出による動作と
併用してもよい、すなわち、負荷1の短絡等により、極
めて異常な電流が負荷1に流れるときは、従来例の回路
により供給電流を遮断することができるからである。
Note that the above embodiment may be used in combination with the operation based on abnormal current detection in the conventional example. In other words, when extremely abnormal current flows to the load 1 due to a short circuit in the load 1, the supplied current is controlled by the conventional circuit. This is because it can be blocked.

また、上記負荷1の電流変動に対応する電流値と時間値
とによる種々パターンを制御回路6のメモリ(記憶手段
)9に記憶しておいてもよい、そして、制御回路6のA
/D変換ボート7を介して得たデータとタイマ8による
時間データとによるパターンがメモリ9に記憶されてい
る何れかのパターンと一致しているか否かを判断するよ
うにしてもよい。この場合、上記メモリ9に記憶してお
く種々パターンとして1例えば負荷1の正常状態時にお
ける値とすると、上記判断が不一致になったときに遮断
回路4をトリガする制御信号を出力するようにする。こ
れにより、負荷lが異常状態になると、負荷1の供給電
流が遮断されるため、負荷1の発熱、発煙や発火を事前
に防止することができる。
Further, various patterns of current values and time values corresponding to the current fluctuations of the load 1 may be stored in the memory (storage means) 9 of the control circuit 6.
It may be determined whether the pattern of the data obtained via the /D conversion port 7 and the time data from the timer 8 matches any pattern stored in the memory 9. In this case, if one of the various patterns to be stored in the memory 9 is, for example, a value when the load 1 is in a normal state, a control signal that triggers the cutoff circuit 4 is output when the above judgments do not match. . Thereby, when the load 1 becomes abnormal, the supply current to the load 1 is cut off, so that heat generation, smoke generation, and ignition of the load 1 can be prevented in advance.

このように、負荷1に供給されている電流とこの″重膜
の流れている時間とにより、負荷1の異常状態を判断す
るようにしたので、例えばソレノイドトランジスタ等の
通電時間が規定時間幅を越えた場合、またコンデンサが
逆接続されている場合、従来であればそれらソレノイド
、トランジスタやコンデンサ等にとって異常事態が生じ
ているにもかかわらず、負荷1に異常なしと判断されて
しまうが、この発明では上記判断により異常を検出する
ことができ、供給電流を遮断することができる。
In this way, the abnormal state of load 1 is determined based on the current being supplied to load 1 and the time during which this "heavy membrane" is flowing, so that, for example, the energization time of a solenoid transistor, etc. If the voltage is exceeded, or if the capacitor is connected in reverse, conventionally it would be determined that there is no abnormality in load 1, even though there would be an abnormal situation in the solenoid, transistor, capacitor, etc. In the invention, an abnormality can be detected by the above judgment, and the supply current can be cut off.

[発明の効果] 以上説明したように、この発明の電源回路によれば、負
荷の電流を検出し、この負荷電流とこの電流の流れてい
る時間とにより負荷の異常状態を判断し、負荷に供給す
る電流を遮断するようにしたので、負荷に異常値の電流
が流れていなくとも、その負荷の通電時間が規定時間幅
以上になっている場合、またコンデンサが逆接続されて
いる場合、供給電流が遮断されるため1例えば負荷であ
るソレノイド、トランジスタやコンデンサ等の発熱を防
止し、それらの発煙や発火を未然に防ぐことができ、負
荷を保護することができるという効果がある。
[Effects of the Invention] As explained above, according to the power supply circuit of the present invention, the current of the load is detected, the abnormal state of the load is determined based on the load current and the time during which this current is flowing, and the Since the supplied current is cut off, even if an abnormal value of current is not flowing through the load, if the energization time of the load is longer than the specified time width, or if the capacitor is reversely connected, the supply will be interrupted. Since the current is cut off, for example, it is possible to prevent the loads such as solenoids, transistors, capacitors, etc. from generating heat, thereby preventing them from emitting smoke or catching fire, thereby protecting the loads.

【図面の簡単な説明】[Brief explanation of drawings]

図はこの発明の一実施例を示す電源回路の概略的回路図
である。 図中、1は負荷、2は電源安定化回路、3は抵抗(電流
検出用)、4は遮断回路(供給電流遮断)、5は増幅器
(電流検出用)、6は制御回路(マイクロコンピュータ
)、7はA/D変換ボート58はタイマ、9はメモリで
ある。
The figure is a schematic circuit diagram of a power supply circuit showing an embodiment of the present invention. In the figure, 1 is a load, 2 is a power supply stabilization circuit, 3 is a resistor (for current detection), 4 is a cutoff circuit (for supply current cutoff), 5 is an amplifier (for current detection), and 6 is a control circuit (microcomputer) , 7 is an A/D conversion board 58 is a timer, and 9 is a memory.

Claims (2)

【特許請求の範囲】[Claims] (1)負荷に電流を供給し、かつ、該電流を検出すると
ともに、該検出電流が異常値に達したときには前記供給
電流の出力を制限し、あるいは前記供給電流を遮断する
電源回路において、 前記検出電流が上記異常値より低い所定値に達している
時間を計測するタイマ手段と、 前記検出電流と前記所定値とを比較し、かつ、前記計測
時間と所定時間とを比較し、該比較結果に応じて前記電
流の遮断を制御する制御手段と、前記所定値および所定
時間を記憶している記憶手段とを備えていることを特徴
とする電源回路。
(1) In a power supply circuit that supplies current to a load, detects the current, and limits the output of the supply current or cuts off the supply current when the detected current reaches an abnormal value, a timer means for measuring the time during which the detected current reaches a predetermined value lower than the abnormal value; and a timer means for comparing the detected current and the predetermined value, and comparing the measured time and the predetermined time, and calculating the comparison result. 1. A power supply circuit comprising: a control means for controlling interruption of the current according to the current flow; and a storage means for storing the predetermined value and the predetermined time.
(2)前記記憶手段には前記所定値および所定時間に代
え、前記負荷の状態に対応してその所定値および所定時
間のパターンを種々記憶しておき、前記検出電流と計測
時間によるパターンと前記記憶手段のパターンとを比較
し、該比較結果により前記負荷の異常状態を判断し、か
つ、前記供給電流の遮断を制御するようにした請求項(
1)記載の電源回路。
(2) Instead of the predetermined value and predetermined time, the storage means stores various patterns of the predetermined value and predetermined time corresponding to the state of the load, and the pattern based on the detected current and the measurement time and the A pattern stored in a storage means is compared with a pattern stored in the storage means, an abnormal state of the load is determined based on the comparison result, and cutting-off of the supply current is controlled.
1) Power supply circuit described.
JP24263089A 1989-09-19 1989-09-19 Power supply Pending JPH03107326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24263089A JPH03107326A (en) 1989-09-19 1989-09-19 Power supply

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24263089A JPH03107326A (en) 1989-09-19 1989-09-19 Power supply

Publications (1)

Publication Number Publication Date
JPH03107326A true JPH03107326A (en) 1991-05-07

Family

ID=17091911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24263089A Pending JPH03107326A (en) 1989-09-19 1989-09-19 Power supply

Country Status (1)

Country Link
JP (1) JPH03107326A (en)

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US8544210B2 (en) 2008-03-26 2013-10-01 Aisin Seiki Kabushiki Kaisha Mounting structure for frame garnish
US8640385B2 (en) 2009-02-23 2014-02-04 Aisin Seiki Kabushiki Kaisha Trim attachment structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8127501B2 (en) 2007-04-17 2012-03-06 Aisin Seiki Kabushiki Kaisha Vehicle door having a garnish
US8544210B2 (en) 2008-03-26 2013-10-01 Aisin Seiki Kabushiki Kaisha Mounting structure for frame garnish
US8640385B2 (en) 2009-02-23 2014-02-04 Aisin Seiki Kabushiki Kaisha Trim attachment structure
JP2011041410A (en) * 2009-08-12 2011-02-24 Nec Access Technica Ltd Overcurrent protective device for electronic apparatus, power supply cut-off control method, and program

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