JPH03105972A - Manufacture of semiconductor integrated circuit; semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor integrated circuit and a semiconductor device, and in particular to a gate array method that allows for high integration and has a highly reliable fine structure. The present invention relates to a method for manufacturing a semiconductor integrated circuit and a semiconductor device.

(Prior art) As an example of a semiconductor integrated circuit using a gate array method, a static R
AM (hereinafter referred to as "CMOS 6-transistor SRAM") is conventionally known. Figure 3 shows CMOS
61 is a diagram showing a planar configuration of a conventional gate array constituting a 61-transistor SRAM. The basic cell BC of this CMOS61-transistor SRAM consists of four P-type MOS transistors T Pl-Tr4 and four N-type MOS transistors.
}Equipped with transistors T s 1 to TN4, TP,
The gate electrodes 31 to 34 of ~T, 4 are aligned parallel to each other and facing each other, and the gate electrodes 35 of TN1 to TN4 are aligned parallel to each other and facing each other.
.about.38 are also aligned parallel to each other and facing each other. Contact regions 31a to 38a for connecting lead wires are provided at both ends of each gate electrode, respectively.

The sources of Trl and Tp2 are constituted by a common diffusion layer 39, and the sources of TN2 and TN3 are constituted by a common diffusion layer 40.
It consists of Drain 41 of T F l~TP4
The drains 45 to 48 of ~44 and TN, ~T, and l4 are each constituted by an independent diffusion layer. Also, Tp3
and T. The sources 49 and 50 are each formed of a common diffusion layer with the source of the outermost P-type MOS transistor of the adjacent basic cell. Also, TNI and TN4
Sources 51 and 52 are each formed of a common diffusion layer with the sources of the outermost N-type MOS transistors of adjacent basic cells. The P-type MOS transistor is formed in the N-type semiconductor well 53, and the N-type MOS transistor
The transistor is formed within a P-type semiconductor well 54.

FIG. 4 shows a CMOS6} transistor SRA by applying two-layer wiring of aluminum to the gate array shown in FIG. 3, for example.
This shows the configuration of M. In Figure 4,
The solid lines indicate first-layer wiring, and the dotted lines indicate second-layer wiring formed on the first-layer wiring via an insulating layer. ○ marks are contacts to the 1st layer wiring, ×
The marks indicate contacts to the second layer wiring.

(Problem to be Solved by the Invention) In the conventional gate array described above, the basic cell BC
Gate electrodes 31 to 31 are separately provided to each transistor in the
38 is formed, and contact regions 31a to 38a are provided at both ends of each gate electrode, which has the drawback of poor mounting efficiency and requiring a large area. In addition, since the gates are formed separately, it is necessary to provide a contact hole to connect the gates, and since the WORD line is made of aluminum wiring, it is difficult to connect the area and the aluminum wiring. It was also necessary to provide contact holes. However, in miniaturized devices, the value of contact resistance is a factor that limits circuit delay time, and it is better to have as few contact holes as possible.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, improve mounting efficiency, enable more elements to be formed in the same chip area, and enable the construction of a desired integrated circuit with fewer contact holes. An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit and a semiconductor device.

(Means and Effects for Solving the Problems) A method for manufacturing a semiconductor device of the present invention is a method for manufacturing a gate array type semiconductor integrated circuit including a CMOS transistor. A step of forming a plurality of wells of a conductivity type and a second conductivity type adjacent to each other, a well isolation region for separating the plurality of wells from each other, and an element isolation region for separating each well into a plurality of element formation regions. a wiring region located above the well isolation region, and at least one gate electrode region that connects mutually adjacent wiring regions and extends over the element formation region using a conductive thin film. a step of forming source and drain diffusion layers in the element formation region; a step of removing a portion of the wiring region according to the circuit specifications; and a step of performing desired wiring according to the circuit specifications. It is characterized by including a process.

Further, the semiconductor device of the present invention is a gate array type semiconductor device including a CMOS transistor, and includes a support having an electrical isolation function, and a first conductivity type and a first conductivity type and a first conductivity type and a first conductivity type and a first conductivity type and a plurality of wells of two conductivity types, a well isolation region that isolates the plurality of wells from each other, an element isolation region that isolates each well into a plurality of element formation regions, and a conductive layer located above the well isolation region. A wiring region made of a thin film, a gate electrode region made of at least one conductive thin film extending over the element formation region so as to connect mutually adjacent wiring regions, and a source formed in the element formation region. and a drain diffusion layer.

As described above, in the present invention, the gate electrode and the wiring area are integrally formed with a conductive thin film, and the unnecessary conductive thin film is later removed according to the circuit specifications to form the gate electrode and the wiring. ing. Therefore, there is no need to provide a separate contact area for each gate electrode, and it is only necessary to leave a contact area as necessary at the stage of removing the conductive thin film, so it is possible to improve mounting efficiency. . In addition, the connections between gates and the connections between gates and wiring can be arbitrarily connected or separated at the stage of removing the conductive thin film according to the circuit specifications, so compared to conventional integrated circuits with similar specifications. The number of contact holes can be reduced. Furthermore, since a conductive thin film is formed in the wiring area and used as part of the wiring, it is possible to improve the efficiency of the wiring layout.

(Embodiment) FIG. 1 is a plan view showing the configuration of an embodiment of a semiconductor integrated circuit according to the present invention. As shown in Figure 1 (A),
An N channel region 2 and a P channel region 3 are formed on a semiconductor substrate 1, and a well isolation region S separates these channels by the LOCOS method, and an element isolation region S separates a plurality of element formation regions 4 in each channel region. S,
to form. Next, as shown in FIG. 1B, a wiring region 5 located above the well isolation region SW separating the N channel region 2 and the P channel region 3 and this wiring region 5
A gate electrode region 6 extending over the element formation region 4 is integrally formed with a polysilicon layer. In this example, two gate electrode regions 6 connecting the wiring regions 5 are formed in parallel to each other on each element formation region 4 . Thereafter, ion implantation is performed using the element isolation region Sr and the gate electrode region 6 as masks by a normal process, and each element formation region 4
Source and drain regions are formed within the wafer. Here, the portion BC surrounded by a chain line represents a basic cell.

FIG. 1C is a plan view showing a state in which a transistor is constructed by removing unnecessary portions of the wiring region 5 made of a polyrecon layer. The number of MOS transistors formed in the basic cell BC is the same as in the conventional example shown in FIG. type MOS transistors TNI to TN4 are formed within the P-type well 3. P
type MOS transistors T P l- T p 4 have their gate electrodes? a to 6d are arranged parallel to each other and adjacent to each other. Also, N-type MOS transistors TN, ~T
The gate electrodes 6e to 6h of s4 are also arranged parallel to each other. The sources of the first and second P-type MOS transistors T1 and Tp2 are constituted by a common diffusion layer 7.

Further, third and fourth P-type MOS transistors T1, 3
The sources of Tp4 and Tp4 are common diffusion layers 9 and 1 with the sources of the outermost P-type transistors of adjacent basic cells, respectively.
-0. Each P-type transistor TP. ~T
Each drain of r4 is an independent diffusion layer], 1 to step 4
It is composed of

On the other hand, the sources of the first and second N-type MOS transistors Told and TN2 are constituted by a common diffusion layer 8. Further, the sources of the third and fourth N-type MOS transistors TN3 and TN4 are common to the sources of the outermost N-type transistors of the adjacent basic cells, respectively, and the diffusion layers 15 and 1.
It is completed in 6. Each N-type transistor Ts1 to TN
The drain of No. 4 is composed of independent diffusion layers ↑7 to 20, respectively.

? The wiring region 5 formed on the well isolation region Sw separating the type well 2 and the P-type well 3 is selectively etched, and the remaining polysilicon wiring region 5 is etched.
a and 5b are the first P as shown in FIG.
between the gate 6a of the type transistor TPI and the gate 6e of the first N type transistor T
It acts as a wiring connecting between the gate 6b of the type transistor T,2 and the gate 1-6f of the second N-type transistor TN2, and also acts as a contact region. Further, the wiring region 5 made of a polysilicon layer formed between the basic cell BC and the cell adjacent to the P channel region 3 side is used as a WORD line, and the wiring region 5 formed between the basic cell BC and the cell adjacent to the P channel region 3 side is used as a WORD line, The polysilicon layer formed in between is completely removed. In the case of this embodiment, the gates 6g of the third and fourth N-type MOS transistors TN3 and the gates 6h of TN4 are kept connected to the polysilicon wiring region 5 used as the WORD line, and the first and second N-type MOS transistors TNI and T
The gates 6e and 6f of N2 and the WORD line are separated. In this way, in the conventional example, a part of the wiring that was configured as the first layer wiring is configured as the wiring region 5 made of the polysilicon layer formed integrally with the gate electrode region 6.

The construction drawing (D) shows that aluminum wiring is applied to the gate array shown in Fig. 1 (C) and the final CMOS 6 transistor S
This figure shows an example in which a RAM is configured. The diffusion layer 7 constituting the common source of the first and second P-type MOSI transistors TPI and T1 and T2 is a power supply line V made of the first layer wiring. D, and the first and second N-type MOSI-
A diffusion layer 8 constituting a common source of the transistors TNI and TN2 is connected to a power supply line Vss formed of a first layer wiring. The diffusion layer 20 forming the drain of the fourth N-type MOS transistor TN4 is connected to the diffusion layer 12 forming the drain of the second P-type MOS transistor Tr2 and the first P-type via lead wires 21 and 22. MOS transistor T,
and the gate 6e of the first N-type MOS transistor TNI.
Connect to a sequentially. Third N-type MOS transistor TN
The diffusion layer 19 constituting the drain of No. 3 is connected to the lead wires 22, 2
3, the diffusion layer 17 constituting the drain of the first N-type MOS transistor T9, the gate 6b of the second P-type MOS transistor T, 2, and the gate 6f of the second N-type MOS transistor TN2. It is sequentially connected to the polysilicon contact region 5b to be connected. Furthermore, a third N-type M
Diffusion layer 15 forming the source of the OS transistor TN3
is connected to the bit line BIT formed by the second layer wiring via the lead wire 24, and is connected to the fourth N-type MOS transistor TN4.
-6 is connected to the inverted bisotrine BIT formed by the second layer wiring via the lead wire 25. In this way, a CMOS 6-transistor SRAM is constructed using the first layer wiring, the bit line, and the volt-type wiring.

-L In the embodiment described above, the conductive thin film formed in the gate electrode and wiring area is made of polysilicon.
For example, a high melting point metal such as tungsten may be used. In addition, in the above-described embodiment, the wiring region made of polysilicon layer was separated and removed to configure a CMOS 6-transistor SRAM, and further wiring was applied to connect each region. Wiring can also be performed by separating and removing regions. Furthermore,
Although a semiconductor substrate is used as the base in the above-described embodiment, the base may be made of an insulating substrate such as sapphire, for example.

FIG. 2 is a cross-sectional view showing a step of removing wiring region 5 made of a polysilicon layer by etching. These cross-sectional views are taken along line a-a in FIG. 1 CB). Reference numeral 6 denotes the gate electrode of the outermost P-type transistor of the adjacent basic cell, 26 denotes the drain region of the outermost P-type transistor of ω11 of the adjacent basic cell, 2
A field oxide film 7 separates the element formation region 4. As shown in this figure, a resist film 28 is attached to the portions other than the polysilicon layer to be removed, and selective etching is performed as a mask to remove the unnecessary polysilicon layer.

(Effects of the Invention) As described above, according to the present invention, since the gate electrode and part of the wiring of each transistor are formed of an integrally formed conductive thin film, it is possible to reduce the size of the cell. In addition, the number of contacts in the entire device can be reduced because contact holes are not required for connection between gate electrodes and for connection between gate electrodes and a wiring region constituted by a conductive thin film. Furthermore, since the wiring layout can be made more efficient, it is possible to provide a gate array suitable for large-scale, high-speed LSIs.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the sequential manufacturing process of a semiconductor integrated circuit according to the present invention, FIG. 2 is a cross-sectional view showing the process of removing a wiring region made of a polysilicon layer, and FIG. 3 is a conventional gate array. The plan view, Figure 4, shows
FIG. 6 is a plan view showing a state in which they are connected to form a CMOS 61-transistor SRAM. 1,. Substrate 2/3. ．． Challenging area 4. ．． 4 element formation area 5. Wiring area 6, . Gate electrode region TP. ~T. 4. ．． ．． P-type MOS transistor Ts+-
T-<. ．． ．． N-type MOS} transistors 5a, 5b.
．． Contact regions 6a-6l. Gate electrodes 7, 8, 9, 10, 15, 16, . Sources 11-14
, 17-20. ．． ．． Drain 21-25. ．． Lead wire BC. ．． ．． Basic cell Figure 1 (A> Figure 1 <B) Figure 1 (C) Figure 1 (D)

Claims (1)

[Claims] 1. In a method for manufacturing a gate array type semiconductor integrated circuit including a CMOS transistor, a plurality of wells of a first conductivity type and a second conductivity type are mutually formed on a support having an electrical isolation function. a step of forming a well isolation region that separates the plurality of wells from each other and an element isolation region that isolates each well into a plurality of element formation regions; a step of integrally forming a conductive thin film with at least one gate electrode region connecting adjacent wiring regions and extending over the element formation region; and a step of forming a drain diffusion layer, a step of removing a part of the wiring region according to circuit specifications, and a step of applying desired wiring according to circuit specifications. Method. 2. In a gate array type semiconductor device including a CMOS transistor, a support body having an electrical isolation function, and a plurality of wells of a first conductivity type and a second conductivity type formed adjacent to each other on the support body. a well isolation region that isolates the plurality of wells from each other; an element isolation region that isolates each well into a plurality of element formation regions; and a wiring region made of a conductive thin film located on the well isolation region; A gate electrode region made of at least one conductive thin film extending over the element formation region and source and drain diffusion layers formed in the element formation region so as to connect mutually adjacent wiring regions. A semiconductor device characterized by the ability to