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JPH03105924A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH03105924A
JPH03105924A JP24197089A JP24197089A JPH03105924A JP H03105924 A JPH03105924 A JP H03105924A JP 24197089 A JP24197089 A JP 24197089A JP 24197089 A JP24197089 A JP 24197089A JP H03105924 A JPH03105924 A JP H03105924A
Authority
JP
Japan
Prior art keywords
ccb
chip
substrate
bumps
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24197089A
Other languages
Japanese (ja)
Inventor
Ikuo Yoshida
吉田 育生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24197089A priority Critical patent/JPH03105924A/en
Publication of JPH03105924A publication Critical patent/JPH03105924A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the positional displacement of a semiconductor chip due to mechanical vibrations, etc., at the time of carrying by forming a recessed groove at a position, where a CCB bump on a substrate is abutted, in a semiconductor integrated circuit device of flip chip system. CONSTITUTION:In a micro-chip carrier 1, recessed grooves 9 are shaped at positions, where CCB bumps 2 are abutted, in the main surface of a mullite substrate 3. The CCB bumps 2 are joined on lands 4 shaped into the recessed grooves 9. The lands 4 are connected electrically to the lands 4 on the rear of the mullite substrate 3 through internal wirings 10 made up of tungsten. A semiconductor chip 5 is positioned onto the mullite substrate 3 by employing the chip mounting device, and the CCB bumps 2 are brought to the state in which the bumps 2 are supported by the recessed grooves 9 during a time when the mullite substrate 3 is carried to a reflow device. Accordingly, positional displacement from the lands 4 of the CCB bumps 2 due to mechanical vibrations, etc., at the time of carrying can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置に関し、特にCC B(
Controlled Collapse Bondi
ng)  バンプを介して半導体チップを基板に実装す
るフリップチップ方式の半導体集積回路装置に適用して
有効な技術に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a CCB (
Controlled Collapse Bondi
ng) This relates to a technique that is effective when applied to a flip-chip type semiconductor integrated circuit device in which a semiconductor chip is mounted on a substrate via bumps.

〔従来の技術〕[Conventional technology]

ゲートアレイやマイクロコンビ二一夕などの論理LSI
においては、集積回路の多機能化、高密度化に伴い、外
部回路との接続を行う端子(入出力ビン)の数が急速に
増大し、半導体チップの周辺部に設けたボンディングパ
ッドにワイヤを接続して外部回路との接続を行うワイヤ
ボンディング方式が限界に達している。またワイヤボン
ディング方式は、内部領域の配線を周辺部のボンディン
グバッドまで引き回すので配線長が長くなり、信号伝達
速度が遅延する欠点があるため、高速動作が要求される
論理LSIの実装方式としては不向きである。
Logic LSIs such as gate arrays and microcombiners
As integrated circuits become more multi-functional and denser, the number of terminals (input/output bins) used to connect external circuits rapidly increases, and it becomes necessary to connect wires to bonding pads located around the periphery of semiconductor chips. The wire bonding method, which connects devices to external circuits, has reached its limit. In addition, the wire bonding method has the drawback that the wiring in the internal area is routed to the bonding pads in the peripheral area, which increases the wiring length and delays signal transmission speed, so it is not suitable as a mounting method for logic LSIs that require high-speed operation. It is.

これらの理由から、集積回路の最上層配線に半田などで
構或されたCCBバンプ(Bump,突起電極)を接合
し、このCCBバンプを介して半導体チップを基板に実
装する、いわゆるフリップチップ方式が注目されている
。このフリップチップ方式は、チップの周辺部のみなら
ず、内部領域にも端子を設けることができるので、チッ
プの多ピン化を促進することができる利点がある。また
フリップチップ方式は、ワイヤボンディング方式に比べ
てチップ上の配線長を短くすることができるので、論理
LSIの高速化を促進することができる利点がある。な
お、上記フリップチップ方式については、例えばIBM
社発行、MBMジャーナル・オブ・リサーチ・アンド・
ディベロップメント,■3巻, No. 3 (IB!
J Journal of Research and
 Development, VOI,13, NO.
3)J P 2 3 9 〜P 2 5 0に詳細な記
載がある。
For these reasons, the so-called flip-chip method is used, in which CCB bumps (protruding electrodes) made of solder or the like are bonded to the top layer wiring of an integrated circuit, and the semiconductor chip is mounted on the substrate via the CCB bumps. Attention has been paid. This flip-chip method has the advantage that terminals can be provided not only in the periphery of the chip but also in the internal region, so that the number of pins on the chip can be increased. Furthermore, the flip-chip method has the advantage that the length of wiring on the chip can be made shorter than that of the wire bonding method, so that the speed of the logic LSI can be increased. Regarding the above flip-chip method, for example, IBM
Published by MBM Journal of Research and
Development, Volume ■3, No. 3 (IB!
J Journal of Research and
Development, VOI, 13, NO.
3) Detailed descriptions are given in JP 2 3 9 to P 2 5 0.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

フリップチップ方式の実装工程では、CCBバンプを介
してチップを基板に実装する際、まずチップマウント装
置を用いてチップを基板の所定箇所に位置決めし、次い
でこの基板をリフロー装置に搬送して不活性雰囲気中で
CCBバンプを加熱溶融(リフロー)させている。とこ
ろが、基板をチップマウント装置からりフロー装置まで
搬送する間に、基板上に位置決めされたチップが機械的
振動などによって位置ずれを引き起こし、CCBバンプ
の接続不良が発生するという問題がある。
In the flip-chip mounting process, when a chip is mounted on a board via CCB bumps, the chip is first positioned at a predetermined location on the board using a chip mount device, and then the board is transferred to a reflow machine where it is inactivated. The CCB bumps are heated and melted (reflowed) in an atmosphere. However, while the substrate is being transported from the chip mounting device to the reflow device, there is a problem in that the chip positioned on the substrate is displaced due to mechanical vibration or the like, resulting in poor connection of the CCB bumps.

その対策として、チノプを基板に位置決めする際に、チ
ップをフラックスで基板に仮固定する方法が一部で用い
られているが、この方法は、フラックスがチノブの汚染
源となり易く、チップの電気特性が経時的に劣化すると
いう問題がある。また、チップを基板に位置決めする際
に、チップの裏面から荷重を印加しながらCCBバンプ
をその融点以下の温度で加熱してチノプを基板に仮固定
するという方法もあるが、この方法はチップに機械的な
ダメージが加わるのでチップの電気特性が劣化し易いと
いう問題や、CCBバンプを加熱する際にその表面が酸
化されてCCBバンプの接合強度が低下するという問題
がある。
As a countermeasure, some methods are used to temporarily fix the chip to the board with flux when positioning the chip on the board, but this method tends to cause the flux to become a source of contamination of the chip and affect the electrical characteristics of the chip. There is a problem that it deteriorates over time. Additionally, when positioning the chip on the substrate, there is a method of temporarily fixing the chip to the substrate by heating the CCB bumps at a temperature below their melting point while applying a load from the back side of the chip. There is a problem that the electrical characteristics of the chip are likely to deteriorate due to mechanical damage, and a problem that the bonding strength of the CCB bump is reduced because the surface of the CCB bump is oxidized when the CCB bump is heated.

本発明は上記した問題に着目してなされたものであり、
その目的は、半田バンプの接続信頼性を向上させること
のできる技術を提供することにある。
The present invention has been made focusing on the above-mentioned problems,
The purpose is to provide a technique that can improve the connection reliability of solder bumps.

本発明の前記ならびにその他の目的と新規な特黴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、次のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

本願の一発明は、基板上のCCBバンプ当接箇所に凹構
を設けたフリップチップ方式の半導体集積回路装置であ
る。
One invention of the present application is a flip-chip type semiconductor integrated circuit device in which a concave structure is provided at a CCB bump contact location on a substrate.

〔作用〕[Effect]

上記した手段によれば、チップマウント装置を用いて基
板上にチップを位置決めした後、この基板をリフロー装
置まで搬送する間は、CCBバンプが基板上に設けた凹
溝によって支持された状態になっているので、搬送時の
機械的振動などによるチップの位置ずれが確実に防止さ
れる。
According to the above means, after the chip is positioned on the substrate using the chip mount device, the CCB bumps are supported by the grooves provided on the substrate while the substrate is being transported to the reflow device. This ensures that chips are prevented from shifting due to mechanical vibrations during transportation.

以下、実施例を用いて本発明を詳述する。Hereinafter, the present invention will be explained in detail using Examples.

〔実施例1〕 第l図に示すように、本実施例1の半導体集積回路装置
であるマイクロチップキャリャ(!;ticro Ch
ip Carrier;MCC)  1は、CCBバン
プ2を介してムライト基板3の主面(上面)のランド4
上に半導体チップ5を接続するとともに、この半導体チ
ップ5を、例えば窒化アルミニウム(A Ir N)か
らなるキャップ6で気密封止した構造を有している。上
記キャップ6は、封止用半田7によってムライト基板3
上に接合されている。一方、上記半導体チ/プ5の裏面
(上面)は、伝熱用半田8を介してキャップ6の裏面に
接合されており、これにより、半導体チップ5から発生
する熱がキャップ6を通じて外部に放赦される構造にな
っている。
[Example 1] As shown in FIG. 1, a microchip carrier (!; ticro Ch
ip carrier; MCC) 1 is connected to a land 4 on the main surface (upper surface) of the mullite substrate 3 via the CCB bump 2.
It has a structure in which a semiconductor chip 5 is connected thereon and the semiconductor chip 5 is hermetically sealed with a cap 6 made of, for example, aluminum nitride (A Ir N). The cap 6 is attached to the mullite substrate 3 by the sealing solder 7.
is joined on top. On the other hand, the back surface (top surface) of the semiconductor chip 5 is bonded to the back surface of the cap 6 via the heat transfer solder 8, so that the heat generated from the semiconductor chip 5 is radiated to the outside through the cap 6. It is structured to be forgiven.

本実施例lのマイクロチソブキャリャ1においては、前
記ムライト基板3の主面のCCBバンプ2が当接される
箇所に凹溝9が設けられており、この凹a9の内部に形
或された前記ランド4上にCCBバンプ2が接合されて
いる。このランド4は、例えばW(タングステン)から
なる内部配線10を通じてムライト基板3の裏面(下面
)のランド4と電気的に接続されている。
In the microtisobucarrier 1 of this embodiment 1, a groove 9 is provided in the main surface of the mullite substrate 3 at a location where the CCB bump 2 comes into contact, and a groove a9 is formed inside the groove a9. A CCB bump 2 is bonded onto the land 4. This land 4 is electrically connected to the land 4 on the back surface (lower surface) of the mullite substrate 3 through an internal wiring 10 made of, for example, W (tungsten).

このような構戊からなる本実施例1においては、チップ
マウント装置を用いて半導体チップ5をムライト基板3
上に位置決めした後、このムライト基板3をリフロー装
置に搬送する間は、CCBバンプ2が凹溝9で支持され
た状態になる。これにより、搬送時の機械的振動などに
よってCCBバンプ2がランド4から位置ずれするのを
確実に防止することができるので、CCBバンプ2の接
続信頼性を向上させることができる。また、凹溝9内に
形或されたランド4上にCCBバンプ2を接合するので
、CCBバンプ2とランド4との接触面積が大きくなり
、この点からもCCBバンプ2の接続信頼性を向上させ
ることができる。さらに本実施例1では、フラノクスを
用いて半導体チップ5をムライト基仮3上に仮固定しな
いので、フラックスによる半導体チップ5の汚染も生じ
ない。
In the first embodiment having such a structure, the semiconductor chip 5 is mounted on the mullite substrate 3 using a chip mounting device.
After being positioned above, the CCB bumps 2 are supported by the grooves 9 while the mullite substrate 3 is being transported to a reflow apparatus. Thereby, it is possible to reliably prevent the CCB bump 2 from being displaced from the land 4 due to mechanical vibrations during transportation, so that the connection reliability of the CCB bump 2 can be improved. Furthermore, since the CCB bump 2 is bonded onto the land 4 formed in the groove 9, the contact area between the CCB bump 2 and the land 4 is increased, and from this point of view as well, the connection reliability of the CCB bump 2 is improved. can be done. Furthermore, in the first embodiment, since the semiconductor chip 5 is not temporarily fixed on the mullite base 3 using flanox, the semiconductor chip 5 is not contaminated by flux.

なお、上記マイクロチップキャリャ1は、第2図に示す
ように、ムライト基板3の下面のランド4に接合したC
CBバンプ12を介してモジュール基板1lの主面に実
装される。そこでこの場合は、モジュール基板1lの主
面において上記CCBバンプ12が当接される箇所に凹
溝13を設け、この凹溝13内にランド4を形戊するこ
とにより、チップマウント装置を用いてマイクロチップ
キャリャ1をモジュール基板11上に位置決めした後、
このモジュール基板11をリフロー装置に搬送する間は
、CCBバンプ12が凹溝l3で支持された状態になる
。これにより、モジュール基板王1をチップマウント装
置からりフロー装置に搬送する間の機械的振動などによ
るマイクロチップヰヤリャ1の位置ずれを確実に防止す
ることができるので、CCBバンプ12の接続信頼性を
向上させることができる。
As shown in FIG.
It is mounted on the main surface of the module board 1l via the CB bumps 12. Therefore, in this case, a groove 13 is provided in the main surface of the module substrate 1l at a location where the CCB bump 12 contacts, and a land 4 is formed in the groove 13, thereby making it possible to use a chip mount device. After positioning the microchip carrier 1 on the module board 11,
While the module board 11 is being transported to the reflow apparatus, the CCB bumps 12 are supported by the grooves l3. This makes it possible to reliably prevent the positional shift of the microchip carrier 1 due to mechanical vibrations while transporting the module substrate king 1 from the chip mounting device to the flow device, thereby ensuring reliable connection of the CCB bumps 12. can improve sex.

〔実施例2〕 第3図に示すように、本実施例2のマイクロチップキャ
リャ1は、一部のCCBバンプ2aの径を他のCCBバ
ンプ2の径よりも大きくするとともに、ムライト基板3
の主面上において上記大径のCCBパンブ2aが当接さ
れる箇所にのみ凹溝ブ2aの数は、例えば1〜4個程度
でよいが、これに限定されるものではない。
[Example 2] As shown in FIG. 3, the microchip carrier 1 of Example 2 has a diameter of some CCB bumps 2a larger than that of other CCB bumps 2, and a mullite substrate 3.
The number of concave grooves 2a may be, for example, about 1 to 4 at the portions on the main surface of which the large-diameter CCB breads 2a come into contact, but the number is not limited to this.

このような構或からなる本実施例2のマイクロチップキ
ャリャ1においても、チップマウント装置を用いて半導
体チップ5をムライト基板3のランド4上に位置決めし
た後、このムライト基板3をリフロー装置に搬送する間
は、大径のCCBバンプ2aが凹溝9で支持された状態
になるので、搬送時の機賊的振動などによる半導体チッ
プ5の位置ずれを確実に防止することができる。
In the microchip carrier 1 of the second embodiment having such a structure, the semiconductor chip 5 is positioned on the land 4 of the mullite substrate 3 using a chip mounting device, and then the mullite substrate 3 is placed in a reflow device. Since the large-diameter CCB bumps 2a are supported by the grooves 9 during transportation, it is possible to reliably prevent the semiconductor chips 5 from being displaced due to vibrations caused by pirates during transportation.

〔実施例3〕 第4図に示すように、本実施例3のマイクロチップキャ
リャ1は、ムライト基板3の主面上に小形のプラスチッ
ク基板14を積層し、このプラスチック基板14の主面
のランド4上にCCBバンプ2を介して半導体チップ5
を接続する構或になっている。上記プラスチック基板1
4は、マイクロチソブキャリャ1の配線密度を大きくす
るためのものであり、前記ランド4とムライト基板3の
内部配線10とは、このプラスチック基板14の図示し
ない内部配線を通じて電気的に接続されている。そして
、上記プラスチック基1fl4の主面上においてCCB
バンプ2が当接される箇所には凹溝9が設けられ、この
凹溝9の内部に前記ランド4が形成されている。従って
、本実施例3のマイクロチップキャリャ1においても、
チップマウント装置を用いて半導体チップ5をプラスチ
ック基板l4の主面上に位置決めした後、これをリフロ
ー装置に搬送する間は、CCBバンプ2が凹溝9で支持
された状態になっているいるので、搬送時の機械的振動
などによる半導体チップ5の位置ずれを確実に防止する
ことができる。
[Embodiment 3] As shown in FIG. 4, the microchip carrier 1 of this embodiment 3 has a small plastic substrate 14 laminated on the main surface of the mullite substrate 3, and the main surface of the plastic substrate 14 is Semiconductor chip 5 is placed on land 4 via CCB bump 2.
It is planned to connect. The above plastic substrate 1
4 is for increasing the wiring density of the microtisobucarrier 1, and the land 4 and the internal wiring 10 of the mullite substrate 3 are electrically connected through the internal wiring (not shown) of this plastic substrate 14. There is. Then, on the main surface of the plastic base 1fl4, CCB
A groove 9 is provided at a location where the bump 2 comes into contact, and the land 4 is formed inside the groove 9. Therefore, also in the microchip carrier 1 of the third embodiment,
After the semiconductor chip 5 is positioned on the main surface of the plastic substrate l4 using the chip mount device, the CCB bump 2 is supported by the groove 9 while it is being transferred to the reflow device. , displacement of the semiconductor chip 5 due to mechanical vibration during transportation can be reliably prevented.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例1〜3に限定
されるものではなく、その要旨を逸脱しない範囲で種々
変更可能であることはいうまでもない。
The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 to 3, and can be modified in various ways without departing from the gist thereof. Needless to say.

ムライト基板あるいはプラスチック基板の主面上に設け
る凹溝の形状は、前記実施例l〜3に示すような形状に
限定されるものではなく、例えばU形やV形の断面形状
を有する凹溝であってもよい。
The shape of the groove provided on the main surface of the mullite substrate or the plastic substrate is not limited to the shapes shown in Examples 1 to 3 above, but may be a groove having a U-shaped or V-shaped cross-section, for example. There may be.

前記実施例1〜3では、本発明をマイクロチップキャリ
ャに適用した場合について説明したが、これに限定され
るものではなく、CCBバンプを介して半導体チップを
各種基板に実装するフリップチップ方式の半導体集積回
路装置全般に適用することができる。
In Examples 1 to 3, the present invention is applied to a microchip carrier, but the present invention is not limited to this, and is applicable to a flip-chip method in which a semiconductor chip is mounted on various substrates via CCB bumps. It can be applied to semiconductor integrated circuit devices in general.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

フリップチップ方式の半導体集積回路装置において、基
板上のCCBバンプが当接される箇所に凹溝を設けるこ
とにより、チップマウント装置を用いて半導体チップを
基板上に位置決めした後、この基板をリフロー装置に搬
送する間は、CCBバンプが前記凹溝によって支持され
た状響になるので、搬送時の機械的振動などによる半導
体チップの位置ずれを確実に防止することができる。
In a flip-chip type semiconductor integrated circuit device, a groove is provided on the substrate at the location where the CCB bump comes into contact with the semiconductor chip, and after the semiconductor chip is positioned on the substrate using a chip mount device, the substrate is placed in a reflow device. Since the CCB bumps are supported by the grooves during transportation, it is possible to reliably prevent the semiconductor chip from shifting due to mechanical vibrations during transportation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例である半導体集積回路装置
の要部断面図、 第2図は、この半導体集積回路装置をモジュール基板に
実装した状態を示す要部断面図、第3図は、本発明の他
の実施例である半導体集積回路装置の要部断面図、 第4図は、本発明のさらに他の実施例である半導体集積
回路装置の要部断面図である。 1・・・マイクロチップキャリャ、2.2a,12・・
・CCBバンプ、3・・・ムライト基板、4・・・ラン
ド、5・・・半導体チップ、6・・・キャップ、7・・
・封止用半田、8・・・伝熱用半田、9,l3・・・凹
溝、1o・・・内部配線、11・・・モジュール基板、
14・・・プラスチック基板。
FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part showing a state in which this semiconductor integrated circuit device is mounted on a module board, and FIG. FIG. 4 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to still another embodiment of the present invention. 1... Microchip carrier, 2.2a, 12...
・CCB bump, 3... Mullite substrate, 4... Land, 5... Semiconductor chip, 6... Cap, 7...
-Solder for sealing, 8...Solder for heat transfer, 9,l3...Concave groove, 1o...Internal wiring, 11...Module board,
14...Plastic board.

Claims (1)

【特許請求の範囲】 1、CCBバンプを介して半導体チップを基板に実装し
た半導体集積回路装置であって、前記基板上においてC
CBバンプが当接される箇所に凹溝を設けたことを特徴
とする半導体集積回路装置。 2、前記CCBバンプの一部が他のCCBバンプよりも
大径をなし、前記基板上において前記大径のCCBバン
プが当接される箇所に凹溝を設けたことを特徴とする請
求項1記載の半導体集積回路装置。
[Claims] 1. A semiconductor integrated circuit device in which a semiconductor chip is mounted on a substrate via a CCB bump, wherein a CCB bump is mounted on the substrate.
A semiconductor integrated circuit device characterized in that a groove is provided at a location where a CB bump comes into contact. 2. Claim 1, wherein a part of the CCB bump has a larger diameter than other CCB bumps, and a groove is provided on the substrate at a location where the large diameter CCB bump comes into contact. The semiconductor integrated circuit device described above.
JP24197089A 1989-09-20 1989-09-20 Semiconductor integrated circuit device Pending JPH03105924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24197089A JPH03105924A (en) 1989-09-20 1989-09-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24197089A JPH03105924A (en) 1989-09-20 1989-09-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03105924A true JPH03105924A (en) 1991-05-02

Family

ID=17082294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24197089A Pending JPH03105924A (en) 1989-09-20 1989-09-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03105924A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980044255A (en) * 1996-12-06 1998-09-05 황인길 Lead Finger Structure of Flip Chip Substrate
US5990546A (en) * 1994-12-29 1999-11-23 Nitto Denko Corporation Chip scale package type of semiconductor device
US6288451B1 (en) * 1998-06-24 2001-09-11 Vanguard International Semiconductor Corporation Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5990546A (en) * 1994-12-29 1999-11-23 Nitto Denko Corporation Chip scale package type of semiconductor device
KR19980044255A (en) * 1996-12-06 1998-09-05 황인길 Lead Finger Structure of Flip Chip Substrate
US6288451B1 (en) * 1998-06-24 2001-09-11 Vanguard International Semiconductor Corporation Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength

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