JPH0310537U - - Google Patents
Info
- Publication number
- JPH0310537U JPH0310537U JP1989071910U JP7191089U JPH0310537U JP H0310537 U JPH0310537 U JP H0310537U JP 1989071910 U JP1989071910 U JP 1989071910U JP 7191089 U JP7191089 U JP 7191089U JP H0310537 U JPH0310537 U JP H0310537U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- solder bumps
- circuit board
- mounting position
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
第１図ａは本考案におけるＩＣ取付け位置目安
パターンを設けた回路基板上のパターン配線平面
図、第１図ｂは半田バンプ付ＩＣを本考案の回路
基板に実装した平面図、第１図ｃは第１図ｂのＡ
−Ａ断面図、第２図ａは従来の回路基板のパター
ン配線平面図、第２図ｂは従来の回路基板に半田
バンプ付ＩＣを実装し、位置ズレを発生しシヨー
ト状態となつている例を示した平面図、第２図ｃ
は第２図ｂのＢ−Ｂ断面図である。 １……ＩＣ取付け位置目安パターン、２……シ
ヨートされている配線パターン、３……独立した
配線パターン、４……半田バンプ付ＩＣ、５……
ガラエポ回路基板、６……半田バンプ。
パターンを設けた回路基板上のパターン配線平面
図、第１図ｂは半田バンプ付ＩＣを本考案の回路
基板に実装した平面図、第１図ｃは第１図ｂのＡ
−Ａ断面図、第２図ａは従来の回路基板のパター
ン配線平面図、第２図ｂは従来の回路基板に半田
バンプ付ＩＣを実装し、位置ズレを発生しシヨー
ト状態となつている例を示した平面図、第２図ｃ
は第２図ｂのＢ−Ｂ断面図である。 １……ＩＣ取付け位置目安パターン、２……シ
ヨートされている配線パターン、３……独立した
配線パターン、４……半田バンプ付ＩＣ、５……
ガラエポ回路基板、６……半田バンプ。
Claims (1)
- 半田バンプ付ＩＣの入力端子又は出力端子が複
数本あるパターン配線を有するガラエポ回路基板
形状において、半田バンプ付ＩＣの取付位置目安
パターンを設けたことを特徴とするガラエポ回路
基板のパターン形状。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989071910U JPH0310537U (ja) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989071910U JPH0310537U (ja) | 1989-06-19 | 1989-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0310537U true JPH0310537U (ja) | 1991-01-31 |
Family
ID=31609369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989071910U Pending JPH0310537U (ja) | 1989-06-19 | 1989-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310537U (ja) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152766U (ja) * | 1975-02-10 | 1975-12-18 | ||
| JPS523767U (ja) * | 1975-06-24 | 1977-01-11 | ||
| JP2014132682A (ja) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | 樹脂封止型半導体装置の製造方法 |
| USRE45931E1 (en) | 1999-11-29 | 2016-03-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
-
1989
- 1989-06-19 JP JP1989071910U patent/JPH0310537U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152766U (ja) * | 1975-02-10 | 1975-12-18 | ||
| JPS523767U (ja) * | 1975-06-24 | 1977-01-11 | ||
| USRE45931E1 (en) | 1999-11-29 | 2016-03-15 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
| JP2014132682A (ja) * | 2014-03-14 | 2014-07-17 | Renesas Electronics Corp | 樹脂封止型半導体装置の製造方法 |