JPH03104333A - Coding/decoding device - Google Patents

Abstract

PURPOSE:To miniaturize a device and to realize a coding/decoding device with less economical burden by adding a time slot synchronizing signal generating circuit and an internal state storage device to the coding/decoding device for a reception signal. CONSTITUTION:A multiplex frame signal is arrives to an input terminal 1 and inputted to a synchronous signal generating circuit 2. The synchronous signal generating circuit 2 extracts a frame synchronizing signal 7 from the data of a signal time slot and generates 31 time slot synchronizing signals 8 corresponding to the frame synchronizing signal 7. On the other hand, the coding/ decoding device 3 applies coding or decoding of a multiplex frame signal in the unit of time slot according to the time slot synchronizing signal 8 received from the synchronous signal generating circuit 2. Thus, the coding/decoding device 3 applies coding or decoding to plural channel signals one after another.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an encoding/decoding device, and particularly to an encoding/decoding device that performs encoding/decoding on a multiplexed frame signal in which a plurality of audio signals are multiplexed. related to conversion equipment.

[Conventional technology]

As shown in the block diagram of FIG. 5, the conventional encoding/decoding device separates a multiplexed frame signal obtained by time-division multiplexing of a plurality of audio signals into individual audio signals using a demultiplexing device 21, and then separates these into individual audio signals. An encoder/decoder 22 is provided for each audio signal to perform encoding/decoding processing, and the signals subjected to the encoding/decoding processing are multiplexed again by a multiplexer 23 and output.

[Problem to be solved by the invention]

The conventional encoding/decoding device described above separates a multiplexed frame signal obtained by time-division multiplexing of a plurality of audio signals into individual audio signals using a demultiplexing device, and then runs an encoding/decoding device for each of these audio signals. Since the encoding and decoding process is performed by
The problem is that the scale of the entire device becomes large and there is a heavy economic burden. An object of the present invention is to extract a frame synchronization signal included in an audio signal having a multiplexed frame structure or a multiplexed frame signal into an encoder/decoder that encodes or decodes a received signal, and extracts a frame synchronization signal from the frame synchronization signal to generate a time slot. It has a synchronization signal generation circuit that generates a synchronization signal, and a function to store the internal state when the encoder/decoder is encoding or decoding the received signal, and to read it at the time when the encoder/decoder needs it. The object of the present invention is to provide an encoding/decoding device which can be miniaturized by adding a storage device and which can reduce the economic burden.

[Means to solve the problem]

The encoding/decoding device of the present invention has a function of receiving an audio signal of a multiplexed frame t# precept and further encoding information into a compressed multiplexed frame signal, and receiving and compressing the already compressed multiplexed frame signal. In an encoding/decoding device having a function of decoding into an audio signal having the previous multiplexed frame configuration, the audio signal having the multiplexed frame configuration or a frame synchronization signal included in the multiplexed frame signal is extracted, and A synchronization signal generation circuit that generates a time slot synchronization signal from a synchronization signal, and an audio signal having the multiplexed frame configuration, or the multiplexed frame signal and the output of the synchronization signal generation circuit, and encodes or decodes the received signal. a memory having a function of storing an internal state in which the encoding/decoder is encoding or decoding a received signal and reading it at a time when the encoding/decoder needs it; The configuration includes a device.

The encoding/decoding device of the present invention stores the storage device as a FIFO.
It may also be configured with registers.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The signal input to the input terminal 1 is sent to a synchronization signal generation circuit 2 which extracts the frame synchronization signal contained in this signal and generates a time slot synchronization signal, and an encoder/decoder 3 which encodes or decodes the received signal. is input. The encoder/decoder 3 encodes or decodes the received signal,
The processed internal state is manually input to a FIFO register 4 that stores the signal until the next signal of the same channel is encoded or decoded, and the encoded or decoded signal is outputted to an output terminal 5.

FIG. 2 is a diagram showing an example of an audio signal having a multiplexed frame structure.

One frame of the multiplexed frame consists of a signal time slot 6 and audio time slots for 30 channels (hereinafter referred to as "ch"). A frame synchronization bit is provided at the beginning of the signal time slot 6. FIG. 3 is a diagram showing that the synchronization signal generation circuit extracts the frame synchronization signal 7 and generates 31 time slot synchronization signals 8.

Next, the operation will be explained. The explanation will mainly be given with reference to Figure 1, with references to Figures 2 and 3 as necessary. When the multiplexed frame signal arrives at the input terminal 1 and is input to the synchronization signal generation circuit 2, the synchronization signal generation circuit 2 generates the frame shown in FIG. 3 from the data of the signal time slot shown in FIG. A synchronization signal 7 is extracted, and 31 time slot synchronization signals 8 are generated corresponding to this frame synchronization signal 7.

On the other hand, the encoder/decoder 3 encodes or decodes the signal of the multiplexed frame in units of time slots in accordance with the time slot synchronization signal 8 received from the synchronization signal generation circuit 2. That is, when the time slot synchronization signal 8 input to the encoder/decoder 3 is #0 shown in FIG. Pass through without encoding or decoding. Next, when the time slot synchronization signal 8 is #1, the audio time slot "1" shown in FIG.
” is encoded or decoded and output to the output terminal 5. Subsequently, when #2 of the timeslot synchronization signal 8 arrives, the internal state when the timeslot synchronization signal 8 is #1 is saved in the FIFO register 4, and the audio time corresponding to #2 of the timeslot synchronization signal 8 is saved. Slot “2”
” is encoded or decoded. Thereafter, the processing is performed in the same manner up to #30 of the time slot synchronization signal 8, thereby completing the processing of one frame of the multiplexed frame.

Next, when the encoder/decoder 3 receives #1 of the timeslot synchronization signal 8 following #O of the timeslot synchronization signal 8 of the new frame, it corresponds to #1 of the timeslot synchronization signal 8 of the previous frame. The internal state when encoding or decoding is performed using the previously stored F I F
It reads from the O register 4, takes over the internal state, performs encoding or decoding in a new frame, and stores the internal state in the FIFO register 4 again. In this way,
One encoder/decoder 3 can encode or decode signals of a plurality of channels one after another.

FIG. 4 is a diagram showing an example of application of the present invention.

The private branch exchange 9 uses a digital central office line (
2 Mbps = 64 kbps x 30 c
h) Assume that 11 is used.

At this time, the digital office line (2Mbps) 1 1 and the dedicated line (IMbps = 3 2kbps x 30 c
h) By inserting an encoding/decoding device 13 between 1 and 2, the encoding method for each lch can be changed, the number of bits used can be reduced, and the dedicated line 12 can be used effectively.

In the explanation of the embodiment, a FIFO register is used as a storage device to store the internal state of the encoder/decoder, but this register is used to perform the same function, and is used after a certain period of time after inputting a signal. It is also possible to configure an encoding/decoding device using a delay circuit or the like that outputs the signal.

〔Effect of the invention〕

As explained above, according to the present invention, the encoder/decoder that encodes or decodes the received signal extracts the audio signal having a multiplexed frame configuration or the frame synchronization signal included in the multiplexed frame signal. a synchronization signal generation circuit that generates a time slot synchronization signal from a frame synchronization signal;
By adding a storage device that has the function of storing the internal state in which the encoder/decoder is encoding or decoding the received signal and reading it at the time when the encoder/decoder needs it, the device can be improved. This has the effect of making it possible to construct an encoding/decoding device that is smaller and has less economical burden. 1...Input terminal, 2...Synchronization signal generation circuit, 3...
Encoder/decoder, 4... FIFO register, 5
...Output terminal, 6...Time slot for signal, 7...Frame synchronization signal, 8...
- Time slot synchronization signal, 9... Hitotsubashi exchange, 10... Partner station equipment, 11... Digital office line, 12... Dedicated line, 13・・・・・・
...encoding/decoding device.

Claims (2)

[Claims] (1) A function of receiving an audio signal with a multiplexed frame structure and further encoding information into a compressed multiplexed frame signal, and receiving the already compressed multiplexed frame signal and audio with the multiplexed frame structure before being compressed. An encoding/decoding device having a function of decoding into a signal extracts the audio signal having the multiplexed frame configuration or the frame synchronization signal included in the multiplexed frame signal and generates a time slot synchronization signal from the frame synchronization signal. an encoding/decoding device that receives and encodes or decodes the received signal, the audio signal having the multiplexed frame configuration, or the multiplexed frame signal and the output of the synchronizing signal generating circuit; The encoder/decoder is characterized by having a storage device having a function of storing an internal state in which a received signal is being encoded or decoded and reading it at a time when the encoder/decoder needs it. Encoding/decoding device. (2) The encoding/decoding apparatus according to claim 1, wherein the storage device is constituted by a FIFO register.