JPH03102558A - Transfer destination id designating circuit - Google Patents

Abstract

PURPOSE:To designate a correct transfer destination ID by an MPU and to start a processing excepting for the MPU without waiting for the MPU by applying the contents of a first register to a command when the MPU executes transfer through a system bus, and applying the contents of a second register to the command in the case of transfer excepting for the MPU. CONSTITUTION:An MPU 4 sends out the specified address of allocation for writing the transfer destination ID to a local bus 3 and executes write access. Data are written into a transfer destination ID register 11 for MPU and since an I/O 5 executes writing operation, the data are written into a transfer destination ID register 12 excepting for MPU. In the case of transfer through a system bus 2, the contents of the two registers 11 and 12 are selected while controlling a selector 13 by an ACK signal.

Description

[Detailed Description of the Invention] [Summary] Regarding a transfer destination ID designation circuit for a system bus that performs split transfer, it is possible to accurately assign transfer destination IDs for an MPU and a device other than the MPU that are connected to the same bus interface. The system bus command transfer destination identification information (transfer destination ID
) and transfer source identification information (transfer source ID), and uses the transfer destination ID for reception judgment. It has a bus interface (BIF) between the system bus and the local bus, and the M. If a device with higher local bus authority than the PU is connected to the local bus, the MPU in the BIF is
a first register that holds a transfer destination +D, a second register that holds a transfer destination ID other than the MPU, and a selector that selects the first register and the second register based on an enable signal from the MPIJ. , is equipped with an address determination circuit that determines a specific address, and an inversion circuit that inverts a usable signal. When the MPU performs a transfer via the system bus, the contents of the first register are added to the command, and the When performing transfer via the system bus, the contents of the second register are added to the command.

(Industrial Application Field) The present invention relates to a transfer destination ID designation circuit for a system bus that performs spring transfer.

There are two methods for transferring data between devices using a system bus: lock transfer and split transfer.

Long transfer is a method in which the lotus is exclusively used during the transfer and other transfers are controlled during that time, and split transfer is a method in which other transfers can be interrupted as necessary without monopolizing the lotus. .

Therefore, when performing split transfer, data is transmitted and received in packet format.

In a system using a system bus that performs the above split transfer, the system bus command includes the transfer source identification number (
It is necessary to provide a transfer source ID) and a transfer destination identification number (transfer destination ID).

[Conventional technology] FIG. 3 shows an example of a system configuration for performing split transfer.

In the figure, 20 is a system bus, 2L2223 is a local bus, and 24, 25, and 26 are Hass interfaces (B
IF), 27 is MPU, 28 is memory, 29 is I/O device itA, 3CH;! The I/O device wB is shown.

The bus interface (BIF) is an interface circuit that connects the system bus and local bus.
24 connects T/029 and MPU27 by local bus 21
The BIF 25 is connected to the memory 28 by the local lotus 22, and the B-F26 is connected to l/030 by the local lotus 23. I/O29 and MPU
27 is connected to the same BIF 25 by a local bus, but the connection priority of ■/029 is higher than that of the MPU 27. That is, this is the case when a floppy disk or the like that requires processing within a certain period of time is connected to the same bus as an input/output device.

Figure 4 shows a conceptual diagram of system bus commands.
FIG. 4(a) shows an example of the command format of the system path, and FIG. 4(b) shows the read sequence on the system bus.

As shown in Figure 4(a), examples of commands on the system bus include a transfer source ID (8 bits), a transfer destination ID (8 bits), and a transfer destination ID (8 bits).
Bint), R/W (1 bit), Answer (1 Bint),
Consists of others.

As shown in Figure 4(b), the read sequence on the system bus is to read the transfer destination ID command C to address 8 using the MPU's R/W command, and then read the data from the memory to the transfer source ID using the answer command C. Return D. M
It is sent from the PU via BIFI, and transferred from the memory to the system bus via BTF2.

In the system configuration diagram shown in FIG. 3, when an MPU and a device other than the MPU (for example, ■/○, etc.) are connected to the local bus 21, the priority of receiving a request is given to the Hass arbitration unit (arbitration). is generally lower for MPUs. Therefore, if a local bus request is issued from ■/○ etc. while the MPU is continuously using the local bus, the right to use the bus is transferred from the MPU to the I/O etc. After the transfer is completed, the right to use the bus is transferred to the MPU again and the transfer is resumed.

A conceptual diagram of the right to use the local bus is shown in FIG. FIG. 5(a) shows the local bus arbitration signal, and FIG. 5(b) shows the sequence when the MPU receives a bus request from I/○ during continuous transfer.

In the 5i-th (a) local bus arbitration signal, 31 indicates the MPU, 32 indicates the I/O, and 33 indicates the path arbitration. Due to bus arbitration of Pass Arvik 33,
The bus request (REQ1) from the MPU 31 has a lower priority than the bus request (REQ2) from the I/032. Therefore, when the MPU receives a bus request from I/O during continuous transfer, the path arbiter 33
I/O has higher priority for the available signal ACK from
The enable signal ACK2 for ■/○ has priority over the enable signal ACK1 for the MPU. That is, the stage (has cycle) S. ,S. is followed by stage Sl', 32' from the I/O, followed by stage S3. from the MPU. S4 follows.

As a method of assigning a transfer destination ID to this system bus,
There is a method in which a transfer destination ID register is provided in the bus interface BIF, and when performing transfer via the system bus, the transfer initiator sets the transfer destination ID in the transfer destination ID register in the BIF in advance, and then performs the transfer.

However, in FIG. 5(b), the transfer of S2 is
In the setting of 3, l, there may be a case where a different transfer destination ID is set, and in this case, the transfer S3 performed by the MPU via the system bus is transferred to the location indicated by the transfer destination ID set with 3, +. The MPU cannot know this.

Conventionally, as a method to avoid such a situation, there has been a method of issuing a local bus long signal to stop the transfer of bus usage rights due to requests such as I/O. FIG. 6 shows a conventional local bus usage right issuing method. Figure 6(a) shows the MP
An example of a circuit that issues a bus lock signal when U does not have a pass lock signal is shown in FIG. 6(b). Shows the sequence when a request is made.

In the circuit example of FIG. 6(a), 41 is MPU, 42 is T/O, 43 is path arbiter BA, 44 is BIF, 45 is
indicates a lock signal issuing adapter. Also, ■ is MPU4
In the bus lock/unlock signal from 1, ■ indicates a pass lock signal from the lock signal issuing adapter 45, and ■ indicates a connection signal to the system bus.

The MPU 41 sends a message to the adapter 45 at a specific address.
0" is written to enable the pass lock signal from the adapter 45 (assert). Similarly, when the MPU 41 writes "1" to a specific address for the adapter 45, the bus lock signal from the adapter 45 is disabled (negate). ).

In the sequence example shown in FIG. 6(b), when the path arvic 43 is returning the enable signal ACK 1 in response to the request signal REQI from the MPU 41, when the request signal REQ2 from the r/042 interrupts, the MPU 41 sends the path A lock signal is issued to effectively lock the bus, and an unlock signal is then issued to override the lock signal. Therefore, the signal from 1/042 is immediately sent out via the BIF. That is, stages SLOC and SLINLOC are set by a pass lock signal from the MPU 41. Therefore, on the system bus, the signal stages 81-S4 from the MPU 41 are switched to the signal stages Sl'S2°, . . . from the I/042.

[Problems to be Solved by the Invention] However, in the above conventional method, the number of signal control lines and adapters increases, making the hardware complicated, requiring the addition of software to control the path arbiter, etc., and making it difficult to control the lock signal. Therefore, there is a problem that access time becomes long and I/O must wait until the MPU completes processing.

The present invention transfers the transfer destination ID register in the BrF to the MP
The purpose is to provide two, one for U access and one for non-MPU (I/O) access, and to add a command to specify which transfer is to be made to the transfer destination In) field.

[Means to solve the problem]

FIG. 1 shows the basic structure of the present invention. In the figure, 1 is a bus interface, 2 is a system bus, 3 is a local bus, 4 is an MPU, and 5 is a device other than the MPU (1/○).

The system bus 2 assigns transfer destination identification information (transfer destination D) and transfer source identification information (transfer source TD) to the system bus command, and uses the transfer destination ID for reception determination, and the local bus 3 includes the MPU 4. A plurality of devices 5 are connected, and has a bus interface (B+F) 1 between the system bus 2 and the local bus 3, and a device (1/0) 5 having higher local bus authority than the MPU 4 is connected to the local bus 3. In this case, the first register 11 that holds the transfer destination ID of MPU 4 in the BIFI, the second register 12 that holds the transfer destination ID of 5 other than MPU, and the enable signal from MPU 4 It includes a selector 13 that selects the first register and the second register, an address determination circuit 14 that determines a specific address from the address from the MPU 4, and an inversion circuit 15 that inverts a usable signal.

When MPU 4 transfers via the system bus,
Add the contents of the first register 11 for MPU d to the transfer destination ID field of the system bus command, and
When a device (I/O) 5 other than the U performs transfer via the system bus, the contents of the second register 12 for non-MPUs are assigned to the transfer destination ID field.

[Effect]

MPU4 transfers the transfer destination ID to MPU transfer destination ID register 1.
When writing to the first address, MPU 4 sends a specific address allocated for writing to the transfer destination +D to the address line of the local hash, and at the same time sends transfer destination ID information to the data line to perform write access. Based on the local bus address, the address determination circuit 14 determines that it is a specific address, and sends out "1".A register write signal and a usable signal between the output of the address determination circuit I4 and the local bus 1 signal. When becomes valid, the contents of the local lotus data are written to the first register 11.

Further, when the register write signal and the signal obtained by inverting the enable signal by the inverting circuit 15 become valid, the contents of the local hash data are written to the second register 12.

When the MPU 4 performs a write operation to the transfer destination ID register write address, the MPU transfer destination ID register I
When the I/O 5 performs a write operation, it is written to the transfer destination ID register 12 for non-MPUs.

When transferring via the system bus, two registers I1 and 12
is selected by controlling the selector 13 using the enable signal and the inverted signal.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the bus interface circuit of the present invention. In the figure, ■1 is 12 the first register, 12 is the second register, 13 is the selector, 14 is the address judgment circuit, 15 is the inverter, 16 is the
, 17. 18 shows an AND circuit.

MPU4 transfers the transfer destination ID to MPU transfer destination ID register 1.
1, the MPU 4 transfers the specific address allocated for the transfer destination +D write to the address line (3) of the local bus.
2 bits 1), and at the same time sends the transfer destination ID information to the data line (8 bits) to perform a write access. Based on the local hash address, the address determination circuit 14 determines that it is a specific address and outputs "l". ” is sent.

The output of the address judgment circuit 14 and the line of the local lotus [・
The AND circuit 16 outputs the output (register write signal) obtained by ANDing the signal ACK1 with the ANDlTiI circuit 18.
When the ANDed output (register l1 write signal) is asserted, the contents of the local bus data (8 bits) are written to the register 11. Furthermore, when the output (register 12 write signal) obtained by ANDing the register write signal and the signal obtained by inverting the ACK1 signal by the inverter 15 in the AND circuit 17 is asserted, the local bus data (8
The contents of bit) are written to register 12.

As a result, when the MPU 4 performs a write operation to the transfer destination ID register write address, data is written to the transfer destination ID register 11 for MPU, and when the I/O 5 performs a write operation, the data is written to the transfer destination ID register for non-MPU. Written to register 12.

When transferring via the system bus, two registers 11 and 12
The contents of are selected by controlling the selector 13 with the ACK1 signal. Now, let the control signals of the selector 13 be Sl and 32,
Assuming that the data from the register 11 is A and the data from the register 12 is B, the output data Y from the selector 13 is as follows.

When the write signal from the MPU 4 is "t", the write request is valid (asserted) because the address determination signal is "'1", and when it is "0", the write request is invalidated (negate).

In the local bus sequence at this time, after the transfer destination ID is set in stage 1 of the MPU, even if the bus right is transferred to I/O etc., the transfer destination TD information in the next stage 2 does not change.

〔Effect of the invention〕

The MPU can give the correct transfer destination ID to the system bus command ↓ without using the local bus lock signal and its mechanisms as in the past.
/○) can start processing immediately without waiting for MPU processing.

Therefore, when the ACK1 signal from the MPU 4 is "1", the data becomes valid (asserted), and when it is "0", the data becomes invalid (negate). Also,

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a bus interface circuit diagram of an embodiment, FIG. 3 is an example of a split transfer system configuration, and FIG. 4 is a conceptual diagram of system bus commands. FIG. 5 is a conceptual diagram of the right to use the local bus, and FIG. 6 shows a conventional method for issuing the right to use the local bus. In the figure, 1, 24, 25, 26.44 are bus interface circuits, 2, 20 are system buses, 3, 21
, 22.23 is a local bus, 4 , 27, 31.41
is MPU, 5,2930. 32. 42 is ■/○, 1
1 is a first register, 12 is a second register, 13 is a selector, 14 is an address judgment circuit, l5 is an inversion circuit, 1
6, 17. 18 is an AND circuit, 28 is a memory, 33
．． 43 is a bus arbiter, and 45 is a lock signal issuing adapter. 16

Claims (1)

[Claims] In a system bus transfer destination ID designation circuit that performs split transfer, transfer destination identification information (transfer destination ID) is included in a system bus command.
It has a system bus (2) that assigns transfer source identification information (transfer source ID) and uses the transfer destination ID for reception judgment, and a local bus (3) to which multiple devices including MPU are connected.
), a bus interface (BIF) (1) between the system bus (2) and the local bus (3), and a device (5) having higher local bus authority than the MPU (4) connects the local bus (
3), the first register (
11), a second register (12) that holds the transfer destination ID of a device other than the MPU (5), and the first register (11) and the second register (
12), an address determination circuit (14) for determining a specific address, and an inversion circuit (15) for inverting a usable signal. When performing a transfer, the contents of the first register (11) are added to the command, and when a device other than the MPU (5) performs a transfer via the system bus (2), the contents of the second register (12) are added to the command. A transfer destination ID designation circuit characterized in that a transfer destination ID designation circuit is provided to a command.