JPH03100723A - Processing system for accuracy conversion instruction - Google Patents

Abstract

PURPOSE:To facilitate the conversion of the accuracy form of a floating decimal point and to speed up the processing by performing preprocessing including the rounding processing of excessive low-order bits of a mantissa part and the normalization processing of the rounding processing result when data is converted into a form whose mantissa part is less in the number of bits than the mantissa part before the conversion. CONSTITUTION:When the conversion into the accuracy format whose mantissa part F' has the number n' of bits less than the number (n) of bits of the mantissa part F before the conversion is indicated with a floating point accuracy conversion instruction 1 (n>n'), an accuracy form conversion processing part 3 performs the preprocessing including the the rounding processing for rounding up or down excessive low-order bits of the mantissa part F and the normalization processing of the rounding processing result, and then carries out the actual conversion processing. Therefore, normalization processing after the conversion processing is not necessary, so the need to hurther detect the overflow and underflow of the exponent part and make a bias adjustment, etc., is eliminated as a result of the normalization processing after the conversion processing. Consequently, the processing is facilitated and the conversion processing is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for processing a precision conversion instruction for converting the precision format of a floating point number in a floating point arithmetic processing device.

Simplifies the process of converting precision formats for floating point numbers.

The purpose is to speed up processing.

When processing a precision conversion instruction that converts a floating point number expressed in one precision format to a floating point number in another precision format, and the number of bits in the mantissa is smaller than the format before conversion. When performing the conversion, preprocessing is performed including rounding up or down to round up or truncate the extra lower bits of the mantissa and normalization of the rounding result;
This preprocessing result is used to perform the actual conversion process.

[Industrial application field]

The present invention relates to a floating point arithmetic processing device.

This paper relates to a method for processing precision conversion instructions that convert precision formats of floating point numbers.

[Conventional technology]

A floating point number is expressed by a 1-bit sign part S, an m-bit exponent part E, and an n-bit exponent part F, and also by the difference in the number of bits of the mantissa part, that is, the number of significant digits that can be expressed. Single precision format.

Floating point arithmetic processing devices that handle multiple floating point data formats such as double precision format and extended precision format have been widely used.

Conventionally, the number of bits in the exponent part E is the same in both single-precision format, double-precision format, and extended-precision format.
Floating point representation formats in which the number of bits of the mantissa part F differed were widely used. Therefore, for example, when processing a precision conversion instruction such as converting a floating point number expressed in double precision format to a floating point number in single precision format, the number of bits in the mantissa is basically adjusted to the number of bits in the destination. All I had to do was process it.

In recent years, a floating point representation format that uses a precision format in which the number of bits in the exponent part increases as the number of bits in the mantissa increases, has been proposed as an IEEE standard, and floating point arithmetic processing that handles floating point representation formats based on this has been proposed. The number of devices is increasing.

In a floating-point arithmetic processing unit that handles the IEEE standard or a floating-point representation format that conforms to it, a floating-point number X is represented by a 1-bit sign S, an m-bit exponent E, and an n-bit mantissa F. , the value of the exponent part E is the actual exponent value e plus a predetermined exponent bias value. -Generally, the bias value is 2 (@1-1
1-1 is used.

When X is a normalized floating point number, X represents the value shown by the following equation.

X= (-1)' x 1, f+ f
fs・f,

is a binary bit string forming the mantissa part F.

Further, it is implicitly assumed that the most significant bit (integer part) of the significant digits is 1 if it is a normalized number.

Therefore, the actual significant digits are n+t bits.

In a floating-point arithmetic processing unit that handles such floating-point representation formats, when processing a format conversion instruction that converts a floating-point number expressed in a certain precision format to another format, the number of bits in the mantissa is In addition to processing to match the format of the conversion destination, processing to convert the exponent part to the format of the conversion destination is also required.

The conversion process for the mantissa part is 5. If the number of bits in the mantissa part of the destination part is greater than the number of bits in the mantissa part, zeros are added for the missing number of bits, and if the number of bits in the mantissa part of the destination part is less than the number of bits, the extra lower bits are added. This is done by rounding down or rounding up.

To convert the exponent part, either subtract the bias value in the pre-conversion format from the exponent part and add the bias value in the destination format, or prepare the difference in advance and convert it to the exponent part. This can be done by adding or subtracting from the exponent part.

When converting to a format where the number of bits in the exponent part in the destination format is less than the number of bits in the exponent part in the format before conversion, the conversion result must be expressible in the exponent part in the destination format. It may become larger than the maximum value, resulting in exponent overflow, or it may become smaller than the minimum value that can be expressed by the exponent part of the conversion destination, resulting in exponent underflow. In such a case, bias adjustment is performed if necessary.

Bias adjustment is an exponent value that can be expressed in the destination exponent part by subtracting a predetermined bias adjustment value from an exponent value in an exponent overflow state, or by adding a predetermined bias adjustment value to an exponent value in an exponent underflow state. This is the process of converting it into Bias adjustment value is generally 3 x 21
m-! l is used.

Standard m, n values for single-precision and double-precision formats.

The index bias value and bias adjustment value are shown below.

Single precision format m-8, n-23 Exponential bias value - 127 Bias adjustment value - 192 Double precision format m-11, n = 52 Exponential bias value - 1023 Bias adjustment value - 1536 Also, in the IEEE standard, the maximum of the exponent part The value (all bits in the exponent part are 1) and the minimum value (all bits in the exponent part are O) are special data such as non-numbers (data that is not numerical values) and infinite numbers, unnormalized numbers, Reserved to represent numbers other than normalized numbers, such as zero. Therefore, the range of actual exponent values e that can be expressed by the exponent part in single-precision format and double-precision format when using the above standard values of m and n is as follows.

Single precision format -126 to +127 Double precision format -1022 to +1023 Here 9 For example, when converting a floating point number in double precision format to single precision format, if the exponent value is 1320 or more, exponent overflow will occur, and Even if bias adjustment is performed, the exponent cannot be expressed in single-precision format, and when the exponent value is less than 1319, exponent underflow occurs.
Moreover, even if the bias is adjusted, it cannot be expressed in the exponent part of the single-precision format.If the exponent part of the conversion destination cannot be expressed even if the bias adjustment is made in this way, then - The result is special data.

Furthermore, if processing is selected to round up the extra low-order bits of the mantissa, a carry may occur from the most significant bit of the significant digits due to the rounding-up process of addition to the significant digits.

In such a case, it is necessary to perform normalization processing by right-shifting the entire result of addition to the significant figures by 1 bit and adding 1 to the exponent value. Therefore, if normalization processing is required, the exponent value after conversion will be larger by 1 than the exponent value before conversion.

[Problem to be solved by the invention]

In the conventional precision format conversion method, which processes normalization processing in the converted format, even if exponent underflow occurs in the intermediate result before normalization processing, the exponent underflow does not occur due to normalization processing.

Even if index underflow occurs in the intermediate results before normalization processing and index bias adjustment is not possible, if index bias adjustment is possible through normalization processing, the index underflow will occur in the intermediate results before normalization processing. If an exponential overflow occurs due to normalization processing even if no overflow occurs, even if exponential overflow occurs in the intermediate result before normalization processing and it is possible to adjust the exponential bias, the normalization processing will adjust the exponential bias. may not be possible, and the conversion results will be different in each case.
Even after the normalization process, processes for detecting exponent overflow or underflow and detecting whether or not bias adjustment is possible are required, which poses a problem in that the process is complicated.

An object of the present invention is to simplify the precision format conversion process for floating point numbers and speed up the process.

(Means for Solving the Problems) In the present invention, when converting to a format in which the number of bits of the mantissa part of the conversion destination is smaller than the number of bits of the mantissa part before conversion, the mantissa in the format before conversion is Perform pre-processing to round the part and normalize the rounding result if necessary, and use the intermediate result expressed in the pre-conversion format obtained as the pre-processing result to perform the actual conversion process. This eliminates the need for normalization processing after conversion, and enables correct detection of exponent overflow, exponent underflow, and 4-minus adjustment in the conversion result during exponent part conversion processing.

FIG. 1 is an explanatory diagram of the principle of the present invention.

In FIG.

l is a precision conversion instruction for floating point numbers.

2 is the processing content of the precision conversion instruction l, which converts a precision format with a 1-bit sign part S, a 2m-bit exponent part E, and an n-bit mantissa part F into a 1-bit sign part S' and m' bits. This shows conversion to a precision format having an exponent part E' of , and a mantissa part F' of n' bits.

3 is a precision format conversion processing unit according to the present invention.

When precision conversion instruction 1 instructs conversion to a precision format such that the number of bits n' of the mantissa part F' after conversion is smaller than the number n of bits of the mantissa part F before conversion (nun'), the mantissa Preprocessing including rounding up or down to round up or truncate the extra low-order bits of part F, and normalization processing of the rounding result is performed, after which the actual conversion processing is performed, and the other n′
When a conversion instruction is given for a precision format in which n is greater than n (nun'), conversion processing similar to the conventional one is performed without preprocessing.

[For production]

According to the present invention, when performing precision format conversion that reduces the number of bits in the mantissa after conversion, rounding processing is performed to delete the extra number of lower bits of the mantissa, and rounding is performed when necessary. By performing the normalization process that accompanies the process prior to the conversion process.

There is no need for normalization processing after conversion processing. Therefore, it is no longer necessary to perform normalization processing after conversion processing, detection of overflow or underflow of the exponent part, bias adjustment, etc., as in the conventional method, and the processing becomes simpler.

【Example〕

An example of a format conversion instruction between a single-precision format and a double-precision format expressed in a floating-point number representation format compliant with the IEEE standard will be described according to the method of the present invention.

In an arithmetic processing unit that handles the IEEE standard or a floating point number representation format compliant with this standard, the floating point number X is 1.
It is expressed by a sign part S of bits, an exponent part E of m bits, and a mantissa part F of n bits, and the value of the exponent part E is the sum of the actual exponent part e and a predetermined exponent bias value. When X is a normalized floating point number, X represents a value expressed by the following equation.

X= (1)” X 1. f+ b ts...
fs X2” where h b f after the decimal point of significant figures
s...f.

is a binary bit string forming the mantissa part F.

Further, it is implicitly assumed that the most significant bit (integer part) of the significant digits is l if it is a normalized number.

Therefore, the actual significant number is n+1 bits.

As shown in Fig. 2 (a) and (b), in single precision format, m-8, n=23. Exponential bias value - 127° Bias adjustment value = 192 in single precision format.

m=11. nm52. It is assumed that the index bias value is −1023° and the bias adjustment value −1536.

FIG. 3 is a block diagram of an embodiment of the precision format conversion processing unit according to the present invention, which is controlled by a conversion direction designation signal and converts from single precision format to double precision format or from single precision format to single precision format. Selectively perform one of the conversion processes.

In FIG. 3, the output EXO of the exponent part conversion circuit is an exponent overflow detection signal, which sends out 1 when an exponent overflow occurs in the exponent part conversion output, and sends out O otherwise.

Also, EXU is an exponential underflow detection signal.

If an exponent underflow occurs in the exponent part conversion output, 1 is sent; otherwise, 0 is sent. OB is a bias adjustment failure detection signal, and the exponent conversion circuit sends O when the input exponent is in the range of kl<E<k2 for the predetermined values of 1 and 2. Otherwise, it outputs 1.

Since the number of bits in the exponent and mantissa parts of the double-precision format are both greater than the number of bits in the exponent and mantissa parts of the single-precision format, exponent overflow or exponent underflow occurs when converting from single-precision format to double-precision format. will never occur, therefore, EXO.

EXU and OB are both forced to 0.

When the conversion process from single-precision format to double-precision format is selected by the conversion direction designation signal, the exponent conversion circuit converts the 11 bits as shown in FIG. 4 in response to the 8-bit exponent input.
Outputs bit exponent part conversion output and EXO, EXU, and OB.

The exponent conversion output in Figure 4 is 9. For example, for an 8-bit exponent input, the 11-bit binary number 011100oooo
It can be obtained as a result of adding o, that is, 896 (decimal). 896 corresponds to the difference between the exponential bias value in double precision format and the exponential bias value in single precision format (10
23-127-896).

The final conversion result includes the value of the sign part before conversion, the exponent part conversion output, and the lower 29 bits (52 bits) of the mantissa part before conversion.
-23-29) by adding 0 to them as the sign part, exponent part, and mantissa part in double-precision format, respectively.

When conversion processing from double-precision format to single-precision format is selected by the conversion direction designation signal, the exponent conversion circuit converts an 8-bit exponent as shown in FIG. 5 in response to the 11-bit exponent input. part conversion output and EXO, EXU, OB
Output.

The exponent conversion output in Fig. 5 is 1. For example, for an 11-bit exponent input, an 11-bit binary number 0111ooooo
It can be obtained as the lower 8 bits of the result of subtracting oo, that is, 896 (decimal).

In converting from double precision format to single precision format.

When the exponent value is +128 or more, an exponent overflow occurs, and when the exponent value is less than -127, an exponent underflow occurs. Furthermore, the index value is +320 or more or -3
19 or less, it cannot be expressed by the exponent part in single precision format even if bias adjustment is performed. Therefore, the value of the input exponent part in double precision format is 10001111111.
(binary) or higher is detected and set as EXO-1, and then? ,: Detects that it is less than or equal to 0IIIOQOOOOQ (binary) and becomes EXLI-1.

Furthermore, kl corresponds to the exponent value of -319.

Further, 2 is determined corresponding to the index value of +320.

That is, k 1-01011000000, k 2-1
It is compared with the exponent part input data E as 0100111111, and when kl<E<k2, 0B=0, and otherwise, 0B=1.

Also, when converting from double precision format to single precision format.

Since the number of bits in the mantissa part of the conversion destination is smaller, the following preprocessing is performed prior to the actual conversion processing. In other words, if T1 is the intermediate result in which all the lower 29 bits of the mantissa of the floating-point number data before conversion are O, then if rounding is selected to truncate the extra lower bits of the mantissa, TI is This is the processing result.

On the other hand, if rounding is selected to round up the extra lower bits of the mantissa, 1 is added to the 23rd bit from the top of the mantissa of TI, normalization is performed if necessary, and the result T2 is the preprocessed result.

Using the preprocessing results obtained in this way, the actual conversion can be performed as follows. however.

What kind of conversion result should be output when exponent overflow or underflow occurs in the conversion result may differ depending on the floating point arithmetic processing device, but in this embodiment, when bias adjustment is possible, the result after bias adjustment 5 In the case where bias adjustment is not possible, a predetermined non-numeric value is assumed to be the result.

(1) When exponent overflow occurs in preprocessing Exponent overflow may occur in normalization processing in preprocessing, but exponent values that would cause exponent overflow in single precision format cannot be expressed in single precision format. Therefore, an exponential overflow will occur in the conversion result as well.
Moreover, it is clear that bias adjustment is impossible. Therefore, the conversion result will be a non-numeric value.

(2) When exponent overflow does not occur in preprocessing The exponent part of the preprocessing result is input to the exponent part conversion circuit, and the conversion from double precision format to single precision format is specified by the conversion direction designation signal. Exponent conversion output, EXO, EXU as shown.

It can be selectively obtained as follows depending on the value of OB.

■ When EXO and EXU are both 0, the sign part of the preprocessing result, the exponent part conversion output, and the upper 23 bits of the mantissa part of the preprocessing result are used as the sign part, exponent part, and mantissa part in single precision format, respectively. is the conversion result.

■ Either EXO or EXU is 1 and OB is 0
When , the result of bias adjustment of the sign part and exponent part conversion output of the preprocessing result, and the upper 23 bits of the mantissa part of the preprocessing result are converted into the sign part, exponent part, and mantissa part in single precision format, respectively. result.

(2) When OB is 1 If OB is 1, the conversion result is a predetermined non-numeric value because bias adjustment is impossible.

〔Effect of the invention〕

Since the conversion method including preprocessing according to the present invention does not require post-conversion normalization processing, exponential overflow and underflow detection of the post-conversion normalization processing results, which is necessary in the post-conversion normalization method, is unnecessary. It is also possible to eliminate the need for the processing and the bias adjustment possibility detection processing, and it is possible to speed up the conversion processing.

Furthermore, by providing an exponent conversion circuit as shown in this embodiment, exponent overflow and underflow can be detected in exponent conversion processing.

Furthermore, it is possible to efficiently detect whether bias adjustment is possible, and the conversion process can be further speeded up.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of examples of single-precision format and double-precision format, FIG. 3 is a configuration diagram of an embodiment of the precision format conversion processing section according to the present invention, and FIG. FIG. 5 is an explanatory diagram of an example of exponent part conversion from single precision format to double precision format. FIG. 5 is an explanatory diagram of an example of exponent part conversion from double precision format to single precision format. 1 in Figure 1: Precision conversion instruction 2: Processing details of precision conversion instruction 3: Precision format conversion processing section

Claims (2)

[Claims] (1) 1-bit sign part, m-bit exponent part, and n
In a floating-point arithmetic processing unit that represents a floating-point number using a mantissa of bits and handles floating-point data with multiple precision formats in which the number of bits of the exponent and mantissa differs, a floating-point number expressed in a certain precision format is used. When processing a precision conversion instruction that converts a number to a floating point number in another precision format, and when converting to a format where the number of bits in the mantissa is smaller than the format before conversion, the excess mantissa perform preprocessing including rounding processing to round up or truncate the lower bits and normalization processing of the rounding result;
A precision conversion instruction processing method characterized by performing actual conversion processing using this preprocessing result. (2) Input the exponent part expressed in the format before conversion,
Outputs the exponent part converted to the specified format as the conversion result, and if an exponent overflow or underflow occurs in the conversion result of the exponent part,
An exponent overflow detection signal and an exponent underflow detection signal are generated correspondingly, and the value E of the input exponent part is k with respect to a predetermined lower limit value k1 and upper limit value k2.
An exponent conversion circuit that checks whether or not 1<E<k2 is in the range and outputs a state detection signal indicating a corresponding state, and performs conversion processing using the output of the exponent conversion circuit. The precision conversion instruction processing method according to claim 1, characterized in that: