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JPH0298167A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0298167A
JPH0298167A JP25038288A JP25038288A JPH0298167A JP H0298167 A JPH0298167 A JP H0298167A JP 25038288 A JP25038288 A JP 25038288A JP 25038288 A JP25038288 A JP 25038288A JP H0298167 A JPH0298167 A JP H0298167A
Authority
JP
Japan
Prior art keywords
layer
substrate
type
amplifier
isolated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25038288A
Other languages
Japanese (ja)
Other versions
JP2506993B2 (en
Inventor
Toru Ito
徹 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP25038288A priority Critical patent/JP2506993B2/en
Publication of JPH0298167A publication Critical patent/JPH0298167A/en
Application granted granted Critical
Publication of JP2506993B2 publication Critical patent/JP2506993B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce a parasitic capacity under wiring pads and to alleviate a decrease in an input impedance by forming the pads for inputting a signal externally to a semiconductor integrated circuit containing a positive phase amplifier on a semiconductor region isolated from a substrate through an insulating layer. CONSTITUTION:A P-type epitaxial layer 2 having a P-type isolated region 3 is formed on the P-type semiconductor substrate 1 of a semiconductor integrated circuit, external wiring pads 5 are formed on the layer 2 through an insulating layer 4, and connected to a positive phase amplifier 6 in an integrated circuit. The layer 2 in which the potential branch point of dividing resistors 7, 8 is isolated is connected between the output terminal of the amplifier 6 and the ground. A parasitic capacity 9 between the pad 5 and the layer 2 isolated from the substrate 1 by the region 3 under the pad 5 is reduced to the ratio of the difference between an input signal amplitude and a signal amplitude from the potential branch point fed back to the layer 2 under the pad 5 by the input signal amplitude, thereby reducing the input impedance of the amplifier 6.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、正相増幅回路(以下アンプという)を含む半
導体集積回路(以下ICという)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC) including a positive phase amplifier circuit (hereinafter referred to as an amplifier).

従来の技術 第2図は従来のアンプを含むICの要部の概略斜視図を
示す。第2図において、tCに外部から信号を入力する
ための外部結線パッド25は、p形基板21上に形成さ
れて、動作電圧中の最も高い直流電位に固定されたn形
エピタキシャル層22上に絶縁層24を介して作られて
いる。
BACKGROUND OF THE INVENTION FIG. 2 shows a schematic perspective view of the main parts of an IC including a conventional amplifier. In FIG. 2, an external connection pad 25 for inputting a signal from the outside at tC is formed on a p-type substrate 21 and is placed on an n-type epitaxial layer 22 fixed at the highest DC potential among the operating voltages. It is made with an insulating layer 24 in between.

発明が解決しようとする課題 このような従来の構成では、直流電位に固定されている
n形エピタキシャル層22と外部結線パッド25との間
の寄生容量26のために、IC内部の各回路、たとえば
第2図に示したアンプ28の入力インピーダンスは、1
G外部から見た場合、小さくなってしまう。
Problems to be Solved by the Invention In such a conventional configuration, each circuit inside the IC, for example, is The input impedance of the amplifier 28 shown in FIG.
G When viewed from the outside, it becomes small.

第3図はこの問題を軽減するために、従来とられている
4Mmを示し、p形分jIi層23によって外部結線パ
ッド25の下のn形エピタキシセル層22を他の領域か
ら分離して、寄生容量を外部結線パッド25とn形エピ
タキシャル層22の間の容量26とn形エピタキシ↑I
ル層22とp形基板21の間の容量27との直列容量と
している。しかしこの構成によっても、入力信号によっ
て、直流電位に固定されたn形エピタキシャル層22と
外部結線パッド25との間に存在する寄生容量26を充
放電することに変わりはなく、入力インピーダンスの低
下は避けられない。
In order to alleviate this problem, FIG. 3 shows 4 Mm, which is conventionally used, and the n-type epitaxy cell layer 22 under the external connection pad 25 is separated from other regions by the p-type layer 23. The parasitic capacitance is determined by the capacitance 26 between the external connection pad 25 and the n-type epitaxial layer 22 and the n-type epitaxial layer ↑I
The capacitance 27 is connected to the capacitance 27 between the p-type substrate 21 and the p-type substrate 21. However, even with this configuration, the input signal still charges and discharges the parasitic capacitance 26 existing between the n-type epitaxial layer 22 fixed at a DC potential and the external connection pad 25, and the input impedance does not decrease. Inevitable.

本発明は上記問題を解決するもので、内部にアンプを含
むICにおいて、簡単な構成で外部結線パッドに関係す
る寄生容量を小さくして入力インピーダンスの低下を最
小限におさえることのできる半導体装置を提供すること
を目的とするものである。
The present invention solves the above problem, and provides a semiconductor device that can minimize the drop in input impedance by reducing the parasitic capacitance related to external connection pads with a simple configuration in an IC that includes an internal amplifier. The purpose is to provide

課題を解決するための手段 上記課題を解決するために本発明の半導体装置は、正相
増幅回路を含む半導体集積回路へ外部から信号を入力す
るための結線パッドを基板と分離された半導体領域上に
絶縁層を介して形成するとともに、前記結線下の基板と
分離された半導体領域を前記正相増幅回路の出力端と接
地との中間の電位分岐点に接続したものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the semiconductor device of the present invention has a connection pad for inputting a signal from the outside to a semiconductor integrated circuit including a positive-phase amplifier circuit on a semiconductor region separated from a substrate. A semiconductor region separated from the substrate under the connection is connected to a potential branch point intermediate the output end of the positive phase amplifier circuit and ground.

作用 上記構成により、結線パッドとその下の基板と分離され
た半導体領域との間の寄生容量は、入力信号振幅と結線
パッド下の分離された半導体領域に帰還された信号振幅
の差を入力信号振幅で割ったものの比に実効的に低減す
ることになり、さらに、分離された半導体領域と基板と
の間の寄生容量が帰還される信号で充放電されることに
より入力インピーダンスには関与しなくなり、入力信号
が結線パッドの下の寄生容量を充放電するために要する
電流は小さくなり、人力インピーダンスの低下を大幅に
少なくすることができる。
Effect With the above configuration, the parasitic capacitance between the connection pad and the substrate and isolated semiconductor region below it is reduced by the difference between the input signal amplitude and the signal amplitude fed back to the isolated semiconductor region under the connection pad. In addition, the parasitic capacitance between the separated semiconductor region and the substrate is charged and discharged by the feedback signal, so that it no longer contributes to the input impedance. , the current required for the input signal to charge and discharge the parasitic capacitance under the connection pad becomes smaller, and the drop in human power impedance can be significantly reduced.

実施例 以下本発明の一実施例を図面に基づいて説明する。Example An embodiment of the present invention will be described below based on the drawings.

第1図は本発明の一実施例のアンプを含むICの要部の
概略斜視図である。第1図において、p形半導体基板1
の上にp形分離領域3含有するn形エピタキシャル層2
が形成され、その上に絶縁層4を介して外部結線パッド
5が作られており、IC内部の正相増幅回路(アンプ)
6に接続されている。アンプ6の出力端と接地間に分割
抵抗7゜8が接続され、この分割抵抗7,8の電位分岐
点は分離されたn形エピタキシャル層2に接続されてい
る。外部結線パッド5とその下のp形弁M領域3により
p型基板1から分離されたn形エピタキシャル層2との
間の寄生容量9は、入力信号振幅と外部結線パッド5下
のn形エピタキシャル層2に帰還された電位分岐点から
の信号振幅との差を、入力信号振幅で割ったものの比に
実効的に低減することになる。さらに、分離されたn形
エピタキシャルM2とp形基板1との閂の寄生容量10
は帰還された信号で充放電されることになり、入力イン
ピーダンスには関与しなくなる。そこで、アンプ6の出
力端に接続されている分割抵抗7゜8の値を適当に選択
して、帰還信号の振幅を入力信号振幅の90%とした場
合、外部から見た入力容量を0.7PF〜0.15PF
に減少させることができた。
FIG. 1 is a schematic perspective view of the main parts of an IC including an amplifier according to an embodiment of the present invention. In FIG. 1, a p-type semiconductor substrate 1
An n-type epitaxial layer 2 containing a p-type isolation region 3 on top of the
is formed, and an external connection pad 5 is formed on it via an insulating layer 4, and a positive phase amplifier circuit (amplifier) inside the IC is formed.
6. A dividing resistor 7.8 is connected between the output end of the amplifier 6 and the ground, and a potential branch point of the dividing resistors 7 and 8 is connected to the separated n-type epitaxial layer 2. The parasitic capacitance 9 between the external connection pad 5 and the n-type epitaxial layer 2 which is separated from the p-type substrate 1 by the p-type valve M region 3 therebelow is determined by the input signal amplitude and the n-type epitaxial layer under the external connection pad 5. This effectively reduces the difference in signal amplitude from the potential branch fed back to layer 2 to the ratio of the input signal amplitude. Furthermore, the parasitic capacitance 10 between the separated n-type epitaxial layer M2 and the p-type substrate 1 is
will be charged and discharged by the feedback signal and will no longer be involved in the input impedance. Therefore, if the value of the dividing resistor 7°8 connected to the output terminal of the amplifier 6 is appropriately selected and the amplitude of the feedback signal is set to 90% of the input signal amplitude, the input capacitance seen from the outside will be 0. 7PF~0.15PF
was able to be reduced to

発明の効果 以上のように、本発明によれば、正相増幅回路を含む半
導体集積回路へ外部から信号を入力するための結線パッ
ドをこの層幅回路出力と接地との中間の電位分岐点に接
続し、さらにこの結線パッドを基板と分離された半導体
領域上に絶縁層を介して形成したことにより、結線パッ
ド下の寄生容量を実効的に小さくすることができ、入力
インピーダンスの低下を大幅に軽減でき、工業上極めて
有用である。
Effects of the Invention As described above, according to the present invention, a connection pad for inputting a signal from the outside to a semiconductor integrated circuit including a positive phase amplifier circuit is placed at a potential branch point between the layer width circuit output and the ground. By forming this connection pad on a semiconductor region separated from the substrate via an insulating layer, it is possible to effectively reduce the parasitic capacitance under the connection pad, significantly reducing input impedance. It is extremely useful industrially.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す半導体装置の要g15
4/l成図、第2図および第3図はそれぞれ従来の半導
体装置の要部構成図である。 1・・・p形半導体基板、2・・・n形エピタキシャル
層、3・・・p形分離領域、4・・・絶縁層、5・・・
外部結線パッド、6・・・正相増幅回路、7,8・・・
分お1抵抗、9.10・・・寄生容量。 代理人   森  本  義  弘 第 を 図 t・・−P行a半キトイ4−11抜 2・−n杉工む・夕(シマル層 3・・−P形かぁW願す式 %式% 5・・−タE音p、姦5線ハ0ッド 6・・・正不目槽?品回ごS(ア)ツー)z8・・−分
割抵抗 9、 /θ・・情す容量 第2図 第3図
FIG. 1 shows the outline g15 of a semiconductor device showing one embodiment of the present invention.
The 4/1 diagram, FIG. 2, and FIG. 3 are block diagrams of main parts of conventional semiconductor devices, respectively. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type epitaxial layer, 3... P-type isolation region, 4... Insulating layer, 5...
External connection pad, 6... Positive phase amplifier circuit, 7, 8...
1 resistance, 9.10...parasitic capacitance. Agent Yoshihiro Morimoto Figure t...-P line a half-kitoi 4-11 extraction 2-n Sugimu Yu (Simal layer 3...-P type W request type % type % 5.・-ta E sound p, rape 5 line ha 0 dd 6... right and wrong tank? Goods return S (a) two) z8...-divided resistor 9, /θ... love capacity figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 1、正相増幅回路を含む半導体集積回路へ外部から信号
を入力するための結線パッドを基板と分離された半導体
領域上に絶縁層を介して形成するとともに、前記結線パ
ッド下の基板と分離された半導体領域を、前記正相増幅
回路の出力端と接地との中間の電位分岐点に接続した半
導体装置。
1. A connection pad for inputting a signal from the outside to a semiconductor integrated circuit including a positive phase amplifier circuit is formed on a semiconductor region separated from the substrate via an insulating layer, and the connection pad is separated from the substrate below the connection pad. A semiconductor device comprising: a semiconductor region connected to a potential branch point between an output terminal of the positive phase amplifier circuit and ground;
JP25038288A 1988-10-04 1988-10-04 Semiconductor device Expired - Fee Related JP2506993B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25038288A JP2506993B2 (en) 1988-10-04 1988-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25038288A JP2506993B2 (en) 1988-10-04 1988-10-04 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0298167A true JPH0298167A (en) 1990-04-10
JP2506993B2 JP2506993B2 (en) 1996-06-12

Family

ID=17207088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25038288A Expired - Fee Related JP2506993B2 (en) 1988-10-04 1988-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2506993B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033344A (en) * 1989-05-31 1991-01-09 Fujitsu Ltd Semiconductor device and its measurement method
JPH0621335A (en) * 1991-10-07 1994-01-28 Sony Tektronix Corp Integrated circuit
JP2006278720A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp High-frequency semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033344A (en) * 1989-05-31 1991-01-09 Fujitsu Ltd Semiconductor device and its measurement method
JPH0621335A (en) * 1991-10-07 1994-01-28 Sony Tektronix Corp Integrated circuit
JP2006278720A (en) * 2005-03-29 2006-10-12 Mitsubishi Electric Corp High-frequency semiconductor integrated circuit

Also Published As

Publication number Publication date
JP2506993B2 (en) 1996-06-12

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