JPH0297062A - Manufacture of semiconductor memory element - Google Patents

Abstract

PURPOSE:To eliminate the problem concerning the formation of contact between the lower electrode of a capacitor and a substrate so as to decrease the manufacture of a semiconductor memory element in variability by a method wherein the upper end face of an insulating film of a slit wall is exposed by patterning a photoresist, and the insulating film of the slit side wall is dry-etched through the photoresist and a filler as a mask. CONSTITUTION:A slit 6 is formed on a semiconductor substrate 1 through etching, and an insulating film 7 is formed on the side wall and the base of the slit 6. The resin filler 8 is not, only filled into the slit 6 but also adheres onto the substrate 1, and the filler 8 is left unremoved only inside the slit 6 through a dry etching. Next, a photoresist 9 is patterned for the formation of an opening 9a, and the upper end face of the insulating film 7 formed on the side wall of the slit 6 is exposed at the base of the opening 9a. At least the exposed part of the insulating film 7 is dry-etched using the photoresist 9 and the filler 8 as a mask for the formation of a contact section 10 between a capacitor formed inside the slit 6 and a switching element adjacent to the capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a MIS type dynamic random access memory device.

(Prior Art) Conventionally, an MIS type dynamic random access memory device is referred to as a DRAM. ), an 1-transistor/1-capacitor type memory cell consisting of one switching transistor and one capacitor is commonly used. In this type of memory cell, information is stored depending on the presence or absence of charge accumulated in a capacitor, and read and write operations are performed by turning on and off a switching transistor. Therefore, it is necessary for the capacitor of the memory cell to hold charge during a certain freshening period. However, in reality, various leakage currents and charges generated by alpha particles flow into the capacitor, so the capacitance value of the capacitor must be above a certain level to ensure stable memory operation.

On the other hand, due to the high integration of DRAMs, the size of memory cells has become significantly smaller, and it becomes difficult to secure more than a certain amount of capacitors unless some kind of three-dimensional structure is used.

Therefore, for example, a memory cell whose cross-sectional structure is shown in FIG. 2 has been proposed. In FIG. 2, a field oxide film 102 is formed on a P-type silicon substrate 101, and
A groove 103 is formed in this P-type silicon substrate 101. A thick oxide film 104 connected to the field oxide film 102 is formed in the trench 103, and a capacitor composed of a lower polysilicon layer 106, a dielectric thin film 107, and an upper polysilicon layer 108 is buried therein. The lower polysilicon layer 106 is connected to one diffusion layer 111a of an adjacent transfer gate transistor through a contact portion 105. This contact part 1
05 consists of a part of the upper surface of the diffusion layer 111a and one side of the upper part of the groove 103.

The transfer gate transistor is composed of a gate oxide film 109, a gate electrode 110, and source/drain diffusion layers 111a and 1llb. The other diffusion layer 1 of the transfer gate transistor
11b connects the bit line 11 through the contact hole 113.
Connected to 4. A glabellar insulating film 112 is provided to cover the transfer gate transistor and capacitor, and a passivation film 115 is further provided via the focus line 114.

Next, the main part of the method for manufacturing the semiconductor memory element having the above structure will be explained with reference to FIG. A field oxide film 102 is formed on a P-type silicon substrate 101, an oxide film is further formed in the active SN region, and a trench 103 is then formed.Next, an oxide film is formed on the inner surface of the trench 103, thereby forming a field Oxide film 151 connected to oxide film 102
shall be. Thereafter, a photoresist film 152 of a predetermined thickness is formed to fill the trench 103 and on the field oxide film 102 and the oxide film 151. This resist film 152 is patterned to form an opening 153 so as to expose a portion of the oxide film 151 corresponding to the contact portion 105 shown in FIG.
form. Oxide film 1 exposed through this opening 153
51 portion is removed to expose the P-type silicon substrate 101. Next, the resist film 152 is removed and a lower polysilicon layer 106 is formed in the groove 103 and around the upper part thereof as shown in FIG.

(Problem to be Solved by the Invention) However, even with the method described above, the contact portion 105 between the lower polysilicon 106, which is the lower electrode of the capacitor, and the diffusion layer 111a of the transfer gate transistor
In order to minimize the cell area for high integration, it is necessary to use not only the upper surface of the diffusion layer 111a but also one side of the upper side of the groove 103, which is the side surface of the diffusion layer 111a. An opening 153 is formed to expose one shoulder of the oxide film 151 through the oxide film 151.
The depth 154 of the opening 153 relative to the contact portion 105 must be controlled in accordance with the dimensions of the contact portion 105. Controlling this depth 154 is extremely difficult because it is impossible to monitor in-process, and it is impossible to control the exposure amount in the depth direction with high precision. There were issues such as inviting people.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor memory element that eliminates the above-described problems in forming contact between the lower electrode of a capacitor and a substrate and reduces manufacturing variations.

(Means for Solving the Problems) The method for manufacturing a semiconductor element of the present invention includes filling a slit of a semiconductor substrate with a synthetic resin filler via an insulating film, and patterning a photoresist to form an upper end surface of the insulating film on the side wall of the slit. is exposed, and at least the insulating film on the side wall of the slit is dry-etched using the resist and the filler as a mask.

(Function) According to the method of manufacturing a semiconductor device of the present invention, since the insulating film on the side wall of the slit is dry-etched in the depth direction using the photoresist and the filler as a mask, the etching depth can be controlled with high precision.

(Example) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a process diagram showing an embodiment of the present invention.

First, as shown in FIG. 1A, a P-type wheel crystal silicon substrate 1 is prepared, and a field oxide film 2 is formed to a thickness of about 500 nm by selective oxidation. Then, an oxide film 3 with a thickness of about 30 rm is formed on the active region on the silicon substrate 1 by thermal oxidation, and a silicon nitride film 4 is further formed on the entire surface.
The thickness of the oxide film 5 is about 50n+m, and the thickness of the oxide film 5 is 200n.
A thickness of approximately m is deposited by each CVD method.

Next, as shown in FIG. 1B, the oxide film 5 and the silicon nitride film 4 are patterned, and using these as a mask, a depth is formed on the silicon substrate 1 so as to separate the field oxide film 2 and the oxide film 3. A groove (slit) 6 of approximately 4 Irm is formed by etching such as anisotropic etching using a reactive ion etching device. Thereafter, the remaining portion of oxide film 5 is removed.

Next, as shown in FIG. 1C, using the remaining portion of the silicon nitride film 4 as an oxidation-resistant mask, a silicon oxide film 7 with a thickness of 1100 nm is formed on the side walls of the trench 6 in a wet oxygen atmosphere at around 1000°C. and grow on the bottom. Thereafter, the remaining portion of the silicon nitride film 4 that is no longer needed is removed using a boiling phosphoric acid aqueous solution.

Next, as shown in FIG. 1(D), the inside of the groove 6 is filled over the entire surface, and a filling material, for example, PMMA, is further added to a film thickness of about 1 μm.
(Polymethylmethacrylate) is spin-coded, and after drying and hardening, dry etching is performed using oxygen plasma to leave the PMMA layer 8 only inside the groove 6 so that the upper surface thereof is flat, for example. Next, a positive photoresist film 9 is coated on the entire surface by a spin code method and patterned to form openings 9a. At the bottom of this opening 9a, a part of the upper surface of the PMMA layer 8, one upper end surface of the oxide film 7, and the oxide film 3 are exposed in a connected manner.

At this time, since the inside of the groove 6 is filled with PMMA by the PMMA layer 8, patterning of the photoresist film 9 for forming the contact can be performed very easily.

Next, as shown in FIG. 1(E), using the patterned photoresist film 9 and PMMA layer 8 as masks, the oxide films 3 and 7 at the shoulders of the trenches 6 on the active region side are removed by dry etching. , a contact portion 10 is formed by exposing a portion of the silicon substrate 1 at the shoulder portion of the groove 6. At this time, by using a highly anisotropic etching method using reactive ion etching, the lateral expansion of the contact portion IO is suppressed, and the depth along the side surfaces of the groove 6 is precisely etched (
I can control it. After that, the photoresist film 9 is removed.

Next, as shown in FIG. 1(F), the PMMA layer 8 in the groove 6 is removed using oxygen plasma massaging and a sulfuric acid/hydrogen peroxide aqueous solution, and the polysilicon that will become the lower electrode of the capacitor is removed by LPCVD. Deposited on the entire surface by low pressure chemical vapor deposition method. After depositing arsenic glass on top of this polysilicon to make it conductive, it was heated to 950°C.
A back and forth anneal is performed to diffuse arsenic into the polysilicon. Thereafter, the arsenic glass is removed with a dilute hydrofluoric acid aqueous solution and patterned to form a lower polysilicon layer 11 as the lower electrode of the capacitor. This lower polysilicon layer 11 covers the oxide film 7 in the trench 6 from the shoulder portion (contact portion 10) of the trench 6 on the active region side, and extends onto the edge of the field oxide film 2.

Next, as shown in FIG. 1(G), the silicon nitride film 12 that will become the dielectric thin film of the capacitor is coated with dichlorosilane (Si).
L using HzC4z) and ammonia (Nl+3) gas
The film is deposited over the entire surface to a thickness of about 10 nm by the PCVD method, and 90 nm
Annealing is performed in a wet oxygen atmosphere at 0° C. to 950° C. to form an oxide film of about 21 − on the surface. Polysilicon, which will become the upper electrode of the capacitor, is deposited thereon by LPCVD. At this time, the thickness of the polysilicon film is set so that the inside of the trench 6 is completely filled. In order to make this polysilicon conductive, it is doped with phosphorus at a high concentration. Then, the entire surface is anisotropically etched so that the required film thickness is achieved in areas other than the grooves 6. Thereafter, the phosphorus-doped upper polysilicon 13 is dry-etched according to a pattern using photolithography. Thereafter, the silicon nitride film 12 is etched with a buffered hydrofluoric acid solution, and the silicon nitride film 12 is further dry etched. Thereafter, the photoresist film (not shown) used as a mask when etching the upper polysilicon layer 13 and the silicon nitride film 12 is removed.

This silicon nitride film 12 covers the upper surface of the lower polysilicon layer 11, and the upper polysilicon layer 13 fills inside a6 and covers the upper surface of the silicon nitride film 12.

Next, as shown in FIG. 1H, the oxide film 3 on the silicon substrate 1 is removed, and a gate oxide film 14 with a thickness of about 20 nm is formed in the active region by thermal oxidation. A polysilicon film 15 that will become the gate electrode and word line of the transfer gate transistor is deposited thereon by the LPCVD method, the polysilicon film 15 is doped with impurities at a high concentration, and then the polysilicon film 15 and gate oxidation are formed using photolithography technology. The film 14 is patterned. Then, arsenic ions are implanted from the exposed surfaces of the silicon substrate 1 on both sides of the gate oxide film 14 to form N-type source/drain diffusion layers 16B and 16b. One diffusion layer 16a
reaches the contact portion IO, and connection with the capacitor can be established.

Next, as shown in FIG. 1(I), an oxide film 17 is deposited as an intermediate insulating film over the entire surface by CVD, and a contact hole 18 communicating with the diffusion layer 16b is formed by photolithography. Aluminum line 19
A silicon alloy is deposited on the entire surface using the Yubafuta method, and patterned using photolithography.

After the step shown in FIG. 1(1), a silicon nitride film is applied as a passivation film to the entire surface by plasma CVD, and the wafer process is completed.

In the above example, PMMA was used as the filler, but other synthetic resins that do not dissolve in the organic solvent when forming the upper layer photoresist can be used instead, such as positive resist, polyimide resin, etc. be able to.

(Effects of the Invention) As described above, according to the manufacturing method of the present invention, a synthetic resin filler filled in a slit formed in a semiconductor substrate through an insulating film and a patterned photoresist film are used as a mask to form a mask on the side wall of the slit. Since the formed insulating film is dry-etched, the accuracy of the resist pattern is improved because the photoresist is patterned all the way to the bottom surface, and the etching depth of the insulating film on the sidewalls of the trench can be determined by determining the etching conditions. It can be controlled with high precision and can be expected to reduce manufacturing variations.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a structural sectional view of a conventional semiconductor memory device,
FIG. 3 is a process diagram showing the main parts of a conventional method for manufacturing a semiconductor memory device. 1... Silicon substrate, 2... Field oxide film, 3
．． 5, 7.17... Oxide film, 4.12... Silicon nitride film, 6... Groove, 8... PM? I^ layer, 9...
Photoresist film, 9a... Opening portion, 10... Contact portion, 11... Lower layer polysilicon, 13... Upper layer polysilicon, 14... Gate oxide film, 15... Polysilicon film, 16a, 16b... Source/drain diffusion layer, 18... Contact hole, 19... Bit line. 6: Groove Process diagram of the semiconductor memory element of the present invention Figure 6 Process diagram of the semiconductor memory element of the present invention Figure

Claims (1)

[Claims] A first method for forming slits in a semiconductor substrate by etching.
a second step of forming an insulating film on the side walls and bottom of the slit; a third step of filling the slit with a synthetic resin filling and depositing it on the semiconductor substrate; and removing the filling by dry etching. a fourth step of etching and leaving only in the slit; and patterning the photoresist to form an opening, and exposing the top surface of the insulating film formed on the sidewall of the slit at the bottom of the opening. a fifth step of dry etching at least a portion of the exposed insulating film using the photoresist and the filler as a mask to form a contact portion between a capacitor and an adjacent switching element formed in the slit; A method for manufacturing a semiconductor memory device, comprising: a sixth step of forming a semiconductor memory device.