JPH0294635A - Manufacture of mosfet of ldd structure - Google Patents

Abstract

PURPOSE:To easily control a threshold voltage by a method wherein an overhang shape is formed during an etching operation of a gate electrode layer, a low-concentration region of an impurity is formed by implanting ions in an inclined direction, a conductive material is applied and etched back, a sidewall used as one part of an electrode is formed and a high-concentration region of the impurity is formed in an alignment manner with the electrode. CONSTITUTION:Ions 6 are implanted in an inclined direction with reference to the surface of a substrate 1 by making use of a gate electrode of two or more undercut layers as a mask; low-concentration regions 7 of an impurity which are prescribed by end edges of a lower-layer gate electrode layer are formed. A sidewall 8a of the gate electrode layer is formed on the low- concentration regions 7 so as to be overlapped; a gate electrode composed of gate electrode layers 3, 4 and the sidewall 8a including the lower-layer gate electrode layer is formed. Then, ions 9 are implanted in a direction perpendicular to the surface of the substrate 1; the ions 9 are introduced into one part of the low-concentration regions 7; high-concentration regions 10 are formed. That is to say, a source-drain region of an LDD structure is formed. Thereby, a threshold voltage of a transistor can be controlled easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOSFET having an LDD structure.

[Prior Art] In order to alleviate the electric field gradient in the drain region of a MOS FET, a lightly doped (LDD) region is formed in which a low impurity concentration region is formed in the drain region of the MOS FET.
dDrain) Li-based MOSFETs are known.

Conventional MOSFETs with this type of LDD structure require the formation of a low concentration region of impurities in the drain region and the formation of a low concentration region of impurities in the drain region.
The formation of a high impurity concentration region that will become a drain region is performed by patterning a photoresist and injecting impurities into the substrate using the photoresist as a mask.

That is, as shown in FIG. 2(a), an oxide film 2 is formed on the substrate 1.
After laminating a phosphorus-doped polysilicon film 3 and a tungsten silicide film 4, a photoresist 5 is patterned on the tungsten silicide film 4.

Then, as shown in FIG. 2(b), the photoresist 5
A gate electrode is formed by etching the phosphorus-doped polysilicon film 3 and the tungsten silicide film 4 using as a mask.

Next, as shown in FIG. 2(c), phosphorus ions 6 are implanted into the substrate to form an n- region 7 which is a low concentration region of impurities.

After that, as shown in FIG. 2(d), the photoresist 5
After removing the photoresist 15, as shown in FIG. 2(e), a new photoresist 15 is patterned as a mask for source/drain formation on the electrode and slightly extending from the electrode onto the substrate. do.

Then, as shown in FIG. 2(f), arsenic ions 9 are introduced into the substrate at a high concentration to form an n+ region 10 which is a high concentration region of impurities.

Next, as shown in FIG. 2(g), photoresist 1
By removing 5, a MOSFET with the desired LDD structure can be obtained.

[Problem to be solved by the invention] However, the above-mentioned conventional LDD structure MOSFE
In the T manufacturing method, the source/drain regions are formed by patterning a mask different from the mask used to form the gate electrode, so the effective gate electrode width tends to fluctuate from a predetermined value, which can lead to a change in the threshold value of the transistor. Difficult to control voltage.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing an LDD elliptical MOSFET in which a gate electrode can be formed with high precision and thereby the threshold voltage of the transistor can be easily controlled.

[Means for Solving the Problems] A method for manufacturing an LDD structure MOSFET according to the present invention includes:
A method for manufacturing a MOSFET with an LDD structure in which a low impurity concentration region is formed on the drain side includes a step of forming a gate oxide film on a semiconductor substrate, and a step of forming a gate electrode in two or more layers using gate electrode materials with different etching characteristics. a step of etching the gate electrode layer using the photo resist pattern as a mask and etching the gate electrode layer on the surface of the substrate more than the gate electrode layer above it to create an undercut; a step of forming a low concentration region by implanting ions from a direction inclined to the substrate surface using the gate electrode layer as a mask; a step of forming sidewalls of the gate electrode layer with a conductive material; The method is characterized by a step of forming a high concentration region by implanting ions in a direction perpendicular to the substrate surface using the sidewall as a mask.

[Operation] In the present invention, by implanting ions in a direction oblique to the substrate surface using two or more undercut gate electrode layers as a mask, impurity levels defined by the edges of the lower gate electrode layer can be reduced. Form a concentration region. and,
A side wall of a gate electrode layer is formed overlying this low concentration region, thereby forming a gate electrode consisting of the side wall and the gate electrode layer including the lower gate electrode layer. Next, by implanting ions in a direction perpendicular to the substrate surface, ions are introduced so as to overlap part of the low concentration region to form a high concentration region.

As a result, LDD'! F4-shaped source/drain regions are formed. In the present invention, since the highly doped source/drain regions are formed using the gate electrode itself as a mask, it is easy to control the effective gate electrode width and threshold voltage.

[Example] Next, an example of the present invention will be described with reference to the attached drawings.

FIG. 1 is a sectional view illustrating an example method of the present invention in order of steps.

First, as shown in FIG. 1(a), a gate oxide film 2 is formed on a substrate 1 to a thickness of about 20 nm, and then polysilicon fi3 is deposited to a thickness of about 200 nm.

Next, this polysilicon film 3 is doped with phosphorus by diffusing it. Furthermore, after depositing a tungsten silicide film 4 to a thickness of about 200 nm on the polysilicon film 3,
A photoresist 5 is placed on this tungsten silicide film 4.
pattern.

Next, as shown in FIG. 1(b), using this photoresist 5 as a mask, SF6 and CC! Reactive ion etching is performed using a mixed gas of 22F2, and the polysilicon film 3 and tungsten silicide film 4 are patterned to form a part of the gate electrode. At this time, by appropriately setting the etching pressure and gas flow rate, it is possible to undercut the polysilicon film 3 from the tungsten silicide WA4 with good reproducibility. For example, if the etching pressure is 14 Pa
, etching may be performed with the total etching gas flow rate set to 5 Q sccm.

Next, as shown in FIG. 1(C), for example, phosphorus ions 6
is ion-implanted with an energy of 4QKeV to form an n- region 7 with a low impurity concentration on the surface of the substrate 1.

After that, as shown in FIG. 1(d), the photoresist 5
Peel off.

Then, as shown in FIG. 1<e>, a second polysilicon film 8 is deposited over the entire surface. Furthermore, as shown in FIG. 1(f), SF6 and Cl12F.

Etching back is performed by reactive ion etching using a polysilicon gas, and sidewalls 8 of the second polysilicon film 8 are formed on the sides of the polysilicon M3 and the tungsten silicide film 4.
form a. As a result, a gate electrode consisting of the polysilicon film 3, tungsten silicide film 4, and sidewalls 8a is formed.

Next, as shown in FIG. 1(g), arsenic ions 9 are implanted with an energy of 70 KeV from a direction perpendicular to the substrate surface, converting the n+ region 10, which is a high concentration region of impurities, into an n- region. It is formed by overlapping a part of 7. This n+ area 10
A source/drain is formed by this.

Next, as shown in FIG. 1(h),
Heat treatment is performed at 0° C. to anneal the substrate surface after implantation, and the sidewalls 8 formed from the second polysilicon film 8 are
For a, impurities are diffused from the phosphorus-doped polysilicon film 3 to completely cover the polysilicon film between the tungsten silicide film 4 and the oxide film 2.
Make it.

As a result, an LDD structure MOSFET having an n-region 7 adjacent to the drain region is manufactured.

According to this embodiment, the source/drain n+ region 10 is formed using the electrode composed of the sidewall 8a, the lower polysilicon film 3, and the upper tungsten silicide film 4 as a mask, and the side edge of this electrode is used to define the region. Although the boundaries are defined, the gate electrode width and threshold voltage can be easily controlled.

[Effects of the Invention] As explained above, according to the present invention, after an overhang shape is formed during etching of a gate electrode layer, ions are implanted in an inclined direction to form a low concentration region of impurities, and then a conductive material is etched. After depositing, etching back forms sidewalls that will become part of the electrode, and forming a high impurity concentration region in alignment with this electrode, making it possible to control the gate electrode width with high precision. An excellent effect can be obtained in that the threshold voltage can be easily controlled.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are cross-sectional views showing a method according to an embodiment of the present invention in order of steps, and FIGS. 2(a) to (g) are cross-sectional views showing a conventional method in order of steps.

Claims (1)

[Claims] (1) LD with a low impurity concentration region formed on the drain side
A method for manufacturing a D-structure MOSFET includes a step of forming a gate oxide film on a semiconductor substrate, a step of depositing two or more gate electrode layers using gate electrode materials with different etching characteristics, and a photoresist pattern. etching the gate electrode layer on the substrate surface by etching the gate electrode layer on the substrate surface more than the gate electrode layer on the upper layer to create an undercut; and etching the gate electrode layer on the substrate surface using the gate electrode layer as a mask. A step of forming a low concentration region by ion implantation from an inclined direction, a step of forming sidewalls of the gate electrode layer with a conductive material, and a step of forming a low concentration region by implanting ions in a direction perpendicular to the substrate surface using the gate electrode layer and sidewalls as a mask. A method for manufacturing a MOSFET having an LDD structure, comprising the step of forming a high concentration region by ion implantation.