JPH0294194A - Interleave buffer - Google Patents

Abstract

PURPOSE:To realize high speed access to a memory by writing the same data in two memory blocks and alternately accessing the two memory blocks necessarily at the time of continuous readout cycles. CONSTITUTION:When a write request is issued by referring to two memory 1 and 2 having the same capacity and constitution and a write requesting signal, two memory blocks 1, 2 are selected and the same data are written in the two memory blocks 1, 2. At the time of readout, RAS precharge is performed on either one memory blocks 1 or 2 while the other block 2 or 1 is read out after selection. When readout continues, the memory blocks 1 and 2 are alternately selected. Therefore, when readout cycles continue, the RAS precharge to on memory block 1 or 2 is executed in parallel during the readout time from the other block 2 or 1. Thus high-speed memory access becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and in particular to an interleave buffer [Prior Art] In a conventional interleave buffer, memory blocks contained therein are distinguished by addresses. When a memory block is being accessed, start the next access before the access cycle of the currently accessed memory block ends only if the next access has a different address from the currently accessed memory block. By doing so, I was trying to speed up the process.

[Problem to be solved by the invention]

The conventional interleave buffer described above has two or more memory blocks separated by addresses.

Originally, the effect of interleaving is that multiple memory books are accessed alternately, and before the data in one memory block is output (or input), the other memory block is accessed, and the data in one memory block is At the time between the data to be output (or input) and the data of the next access, the output (or input) in the other memory block is
Alternatively, by inputting data (input) and executing the access time from the start of access until the data is output (or input) within the access time of the other memory block, the apparent last precharge time is reduced, resulting in faster speeds. However, with conventional memory control methods,
Whether or not memory accesses are performed alternately depends on the software of the entire system, so if there are only about two memory blocks, the frequency of accesses after one access moving to another memory block is low, resulting in not much speedup. The drawback is that it cannot be done.

(Means for solving problems) The interleave buffers of the present invention have the same capacity.

Two memory blocks for configuration and two for writing
selecting both of the two memory blocks and writing exactly the same data to both of the two memory blocks at the same time;
In the case of reading, one of the two memory blocks is accessed and read while the other memory block is precharged, and in the case of continuous reading, the two memory blocks are alternately selected and the read is performed. Selects both the memory access control circuit that repeats the operation and the memory block when performing the before-before-last refresh,
It also has a circuit that performs refreshing at the same time.

[Effect]

The same data is loaded into both memory blocks, and these two memory blocks are always accessed alternately during consecutive read cycles, so the last precharge of one memory block takes the same amount of time as the read access of the other memory block. It is executed within the ``Memory'' section, allowing for faster access to memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the interleave buffer of the present invention.

]” The address strobe line 001 is connected to the inverter 6 and the AND gate 9. The output terminal of the impeller 6 is an inverted signal 601 of the row address 1 to the lobe, etc.
It is connected to the CLK input terminal of the toggle flip flop 4, and also to the input terminals of the Nant gates 14 and 15. The output terminal of the toggle flip-flop 4 is connected to the memory block selection signal 401, and this memory block [l
The other end of the select signal line 401 is connected to the OR gate 11 and the inverter 10, and the output end of the inverter 10 is connected to the input end of the OR gate 12. The output terminals of OR gates 11 and 12 are memory block selection signals 1
21 and 122, and the other ends of the memory 10 selection signals 121 and 122 are connected to the input ends of Nandogu 1 to 14.15. The output end of the Nant gate 14.15 is connected to the internal RAS signal line 141.151,
The other end is connected to the last input terminal of the memory block.

The write request signal line 002 is connected to the reset terminal of the toggle flip-flop 4, the memory blocks 1 and 2, and the input terminal of the inverter 7. The output terminal of the inverter 7 is connected to the two OR gates 11. as a write request signal 702.
12.

Column address strobe signal line 003 is connected to memory block 1.2 and to the input end of inverter 8. The output end of this inverter 8 is connected to an AND gate 9, and the output end of this AND gate 9 is connected to a refresh request signal line 903. The refresh request signal line 903 is connected to the CLK input terminal of the DFF 4 and the refresh counter 3. This D-
The output end of FF5 is connected to the refresh signal line 503, and the refresh signal line 503 is connected to the OR gate 11,1.
2 and the inverter 6. The output end of this inverter 6 is connected to a delay line 13, and the output end of the delay line 13 is connected to a reset terminal of the D-FF 5. Further, the preset terminal and D input terminal of this D-FF5 are pulled up. The toggle flip-flop 14 is [ ] address strobe signal O
By passing O1 through the inverter 6, a memory selection signal 401 is generated at the falling edge of the address signal 01. This signal is divided into two (J), one of which passes through the inverter 10, and the memory block is selected by which of the signals entering the OR gates 11 and 12 becomes high level. Memory block selection circuit 12 output from
1,122 is [1 address address 1 to [1-wave signal 001
By taking a NAND with the inverted signal 601 and the numbers 1 to 14.15, the internal RAS signal (either 141 or 151) becomes active (low) to the selected memory block. ]l! ! 1 is precharged last while remaining at a high level.

Furthermore, by inputting the inverted signal 702 of the write request signal 002 to the OAGOO h11.12, both memory blocks 1 and 2 are selected during writing, and the same data is written to both memory blocks 1 and 2.

FIG. 2 is a timing chart showing the read cycle of this embodiment, and FIG. 3 is a timing diagram showing switching from the read cycle to the read cycle of the present embodiment.

As can be seen from FIGS. 2 and 3, it is necessary to hold the row address strobe signal 011 at a high level for last precharging before and after write access. In the figure,
t does not indicate ras precharge RC.

Furthermore, if the column address strobe signal 003 is received before the row address strobe signal 001, it is detected by the AND gate 9 and the refresh counter 3
Generates refresh request number 503, and this signal 50
By inputting 3 to Oagoo 1 to 11.12, both memory blocks 1.2 are selected, and two memory blocks 1.2 can be refreshed at the same time (CBR refresh, 'L). However, when using the ram-only refresh, the memory blocks 1.2 can be accessed alternately by the toggle flip-flop 4, similar to the read recycle, so the operation can be performed as if the rast precharge time had been omitted.

FIGS. 4 and 5 are timing charts showing read 4J cycles during page mode operation. The row address strobe signal 001 must be held at a high level for last precharge before and after the write 1 access, and the write request signal 002 must also be generated at the end of the previous access.

FIG. 6 is a block diagram of a second embodiment of the invention.

The difference in the first embodiment is that the memory block selection circuit does not use a toggle flip-flop, but instead uses two D-FF17,
18 to determine the next memory block to be accessed by referring to which memory block was previously accessed.

The internal row address strobe signal lines 141 and 151 are for memory blocks 1 and 2 (not for memory blocks, but for delay line 38).
．． 39 and these two delay lines 38.3
9 output terminals respectively receive the previous access reference signal 381.
391. The output terminal of AND gate 19 is connected to AND gates 25 and 26 and inverter 22.

Further, the output terminal of the AND gate 20 is connected to one inverter 23 of each of the three AND gates 25, 27, and 28. Output terminals of ANDGOO 1 to 25 and AND gate 26
The output terminals of are connected to respective input terminals of the OR gate 40. Inverter 22 is connected to an input end of AND gate 27, and inverter 23 is connected to one input end of AND gate 26. Further, one of the input terminals of the AND gate 28 is connected to the output terminals of the write request signal 703 and the refresh signal 503 of OAG 1 to 12, and the output terminals of the AND gate 27 and the AND gate 28 are connected to the OAG 1 to 4.1. are connected to the respective input terminals of the

The OR gates 40 and 41 are connected to the CL and K input terminals of D-FFs 17 and 18, respectively, and these two D-FFs
The Q output terminals of the FFs 17 and 18 are respectively connected to the input terminal of an AND gate 14i5 as memory block selection signals 121 and 122, as in the first embodiment.

In addition, the two D-FFs 17 and 18 are connected to the inverted signal 601 of the row address strobe signal 001 and the previous access reference signals 381 and 391, respectively.
and connect their respective output terminals to Noagu 1 to 34.
The input terminal is manually input and its output signal is used as a reset signal.

〔Effect of the invention〕

As explained above, the present invention has two memory blocks with the same capacity and configuration, and when a write request is issued by referring to the write request signal (WE low signal), both of the two memory blocks are processed. Select one of the memory blocks and write the same data to both memory blocks, and when reading, select one of the memory blocks and perform a last bridge while reading the other memory block. By alternating the selections, if the read cycles are repeated consecutively, the last selection of one memory block is performed in parallel during the time of the read access of the other memory block, so that This has the effect of enabling high-speed memory access, which eliminates live recharging time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the interleave buffer of the present invention, FIG. 2 shows the read cycle of the first embodiment, and FIG. 3 shows the switching from the read cycle to the write cycle. Figure 4 shows the light recycle and Figure 5 shows the light recycle.
6 is a block diagram of a second embodiment of the present invention. 1...Memory block, 2...Memory block, 3...Refresh counter, 4...T-FF. 5...D-FF, 6.7, 8.10.16...Inverter, 9...And gate, 14.15...Nant gate, 11.12...Oagoo 1~. 13...Delay line, 001...Row address strobe signal (RAS signal), 002...Column address strobe signal (CAS signal), 003...Content request signal (WF double signal, 601...
- Row address strobe inversion signal, 702... Column address inversion signal, 803... Write request inversion signal, 903... Refresh request signal, 401... Memory block selection signal, 121... Memory block Selection signal 122...Memory block selection (No. 0, 133...
Refresh 1 reset i~ signal, 503...Refresh signal, 141...Internal race signal, 151...Internal race signal, 161...Internal waste signal, 171...Internal waste signal 8, 004...・Data signal line group, 006... Address signal line group, 17.18... D-FF 19.20, 25, 26, 27.28... AND gate, 40.41... To OAGOO 1 , 22.23...Inverter, 34.35.36...Noah Gate, 37.38.39...Delay line, 381...
Previous access reference signal, 391...Previous access reference signal.

Claims (1)

[Claims] It has one or two memory blocks and speeds up by starting access to another memory block before the access cycle for one memory block ends and performing redundant memory access. an interleaf buffer for measuring two memory blocks having the same capacity and configuration, and in the case of writing, selecting both of the two memory blocks and writing the same data to both of the two memory blocks at the same time; In the case of reading, one of the two memory blocks is accessed and read while the other memory block is precharged, and if reading is continuous, the two memory blocks are alternately selected and the read operation is performed. An interleave buffer comprising a memory access control circuit that repeats the process, and a circuit that selects both of the memory blocks and refreshes them at the same time when performing a before-last refresh.