JPH0292084A - Picture data transmitter - Google Patents

Abstract

PURPOSE:To realize the efficient processing and the increase in the calculation speed by means of a digital circuit by calculating a quantization step width in one block by an arithmetic equation of (maximum value - minimum value)/2<n> and dividing the signal into 2<n>+1 sets of sections based on nearly a median of the step width. CONSTITUTION:A block data outputted from a data delay section 105 is divided into a prescribed section based on a maximum value from a maximum value detection section 103 and a minimum value of a minimum value detection section 104 by a division conversion section 106. The calculation of a split section width St is realized by only the subtraction of the maximum value and the minimum value and the division of the power of 2. The split section width St is divided into 2<n>+1 sections and to which section each sample belongs is expressed by 2<n>+1 kinds of normalized codes C0-C2<n> per one sample. Simultaneous vector quantization is applied to a 16-dimensional space assembling 16 samples, for example, and the data of ls samples is expressed by a code block in, e.g., 8-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data transmission device, and for example, to an image data transmission device that performs data compression by utilizing redundancy of image data.

[Prior Art] Conventionally, in this type of device, as a method of encoding an image signal by in-field processing, a method of reducing the average number of bits per pixel or the sampling frequency for the purpose of narrowing the transmission band has been used. Some are known.

For example, vector quantization is a method for reducing the average number of bits per pixel. This vector quantization method divides the input signal into blocks of multiple samples, and performs vector quantization all at once on a dimensional space consisting of several samples contained in each block. When the correlation between each sample is high, the number of codebooks representing combinations of k-dimensional sample values can be significantly reduced, and high-efficiency encoding can be realized.

In other words, for example, if blocks are created every 16 samples, a 16-dimensional space becomes the target of vector quantization, and 1
If PCM transmission is attempted for a data sequence expressed by 8 bits per sample, an amount of information of 128 bits will be generated (8 bits x 16 samples).

If this is vector quantized using, for example, 256 codebooks, it can be expressed with 8 bits of index information per block, making it possible to compress the bandwidth by 1/16 (=8/12B).

However, when vector quantization is performed using a fixed codebook, it is difficult to design a general-purpose codebook, and as a preprocessing for vector quantization, local correlation of images is used to generate normalized output. A method has been developed that performs vector quantization after obtaining the vector. One method of normalization is to divide the image into small blocks, obtain the minimum value min and maximum value max of pixel data included in the block, and divide the range between min and max into min, as shown in FIG.
Divide into 2° intervals so that max is the median value of the corresponding area, and vector quantize the n-bit normalization code in units of (k≧2) depending on which interval each pixel value belongs to. A method has been developed to do so.

[Problems to be Solved by the Invention] However, in the conventional example, the normalization method that divides the interval as shown in FIG. L+ (
This is an effective method for correctly reproducing the min and max values because it is necessary to set 0≦i≦n-1) as the median value of each section. It is necessary to divide min by 2n-1. In general, in digital arithmetic circuits, when performing division by a power other than a power of 2, a more complicated circuit is required than when dividing by a power of 2, which is undesirable from the viewpoint of accuracy.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide an image data transmission device that can be realized on the above-mentioned digital circuit and is advantageous in terms of normalization accuracy.

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the objectives, an image data transmission device according to the present invention normalizes image data in units of blocks of pixel data of a predetermined amount, and performs the normalization. A plurality of pieces of data are vector quantized, and the maximum and minimum values of pixel data within the block are added to the vector quantized data as normalization information.

An image data transmission device that adds and transmits at least two of (maximum value - minimum value), wherein the quantization step width in a re-block is calculated by the calculation formula (maximum value - minimum value) ÷ 2''. step width calculating means for calculating the quantization step width; dividing means for dividing the area between the maximum value and the minimum value into 2n+1 sections based on a substantially central value of the quantization step width; The present invention is characterized by comprising a normalization means for expressing normalized data of the section to which the 2n+1 sections belong, and a vector quantization means for collectively vector quantizing a plurality of the normalized data in the block.

Preferably, the arithmetic expression includes a subtraction and a shift operation.

[Operation] According to the above configuration, the step width calculation means (maximum value -
The quantization step width in the Lee block is calculated using the formula: (minimum value) ÷ 2'', and the dividing means divides 2n+1 between the maximum value and the minimum value based on the approximate center value of the quantization step width.
The normalizing means expresses each pixel data in one block with the normalized data of the section to which the 2n+1 sections belong, and the vector quantizing means expresses the normalized data in this block into a plurality of sections. Perform vector quantization all at once.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the image data handled here is data quantized to 8 bits per 1 sample.

First, the transmission method of this embodiment will be explained.

FIG. 1 is a schematic block diagram showing the configuration of the transmitting side of the image data transmission device according to the present embodiment, FIG. 2 is a diagram explaining the block division method according to the present embodiment, and 31m(a) and (b)
FIG. 2 is a diagram showing transmission data in this embodiment. FIG. 4 is a diagram illustrating a method of dividing sections within a block according to this embodiment.

In FIG. 1, 101 is an input terminal for inputting image data in parallel pixel by pixel, and 102 is a block division unit for dividing the image data input from the input terminal 101 into 4×4 pixel blocks. This block dividing section 102
When numbers are added to pixel data as shown in Fig. 2, °“1”-2°°→“3”-4”→”17”→“
18 "..." input the pixel data in the order "1" → "2"
It has a conversion function to output in the order of "-"3"→"4"-"5"→"6"... As shown in Figure 2,
- The area surrounded by the dotted chain line is one normalization processing block. Further, 103 is a maximum value detection unit that detects the maximum value of pixel values in each block divided by the block division unit 102. 104 is a minimum value detection unit that detects the minimum value of pixel values in each block divided by the block division unit 102. Reference numeral 105 is a data delay unit that delays data by the time required to detect the maximum value and minimum value.

106 is a division value conversion unit that divides the block data output from the data delay unit 105 into predetermined intervals based on the maximum value from the maximum value detection unit 103 and the minimum value from the minimum value detection unit 104. . This division value converter 106
, between the maximum and minimum values (max-m
in)/2n (0< n <number of bits of image data) as the division section width St, and the division section width St is min w min + ('/z) St, min as shown in Fig. 4.
+('8) St ~ min + (3/z) st, -min 10 (2'''-1) St/2 ~ max Divide into 2n+1 intervals, and check which interval each sample belongs to for each sample. It is expressed by normalized codes C0 to C02'' of the degree 2°+1''. At this time, calculation of the divided section width St is realized only by subtracting the maximum value and the minimum value and dividing by a power of 2, and this is realized by a digital circuit implemented by a subtraction circuit and a bit shift circuit. Here, the code Coach' is a normalized code in which block-by-block absolute level fluctuations and dynamic range fluctuations are removed.

Further, the normalized representative value Ll (o≦i≦n-1) is set to the median value of each section.

Then, 107 performs batch vector quantization on the normalized code G o "C2n normalized by the division value conversion unit 106, for example, between 16 dimensions in which 16 samples are collected, and converts the data of the 16 samples into, for example, 8 This is a vector quantization unit (hereinafter referred to as rVQj) that is expressed using a bit codebook.108, 109, and 110 are each composed of 8 bits output from the maximum value detection unit 103, minimum value conversion unit 104, and VQ107. Parallel serial data (hereinafter rP) that converts parallel data into serial data
/SJ) conversion unit. Also, 111 is a, b, c
A switching section 112 time-compresses the transmission data from the switching section 111, and outputs one block of data to the synchronization addition section 112, which will be described later, in the form of transmission data shown in FIG. 3(a). After that, set the synchronization signal 5YNC to the third
A synchronization adding section 113 added in the form as shown in FIG. 3(b) is an output terminal for outputting the transmission data outputted from the synchronization adding section 112 to the outside. 114 is a timing control section that controls the timing of each circuit.

According to this device, 16 samples x 8 bits = 128
Bit information is expressed by compressing it into 8 bits x 3.24 bits, and the compression ratio is set to "3/16".

Here, the operation of the transmitting side of the image data transmitting apparatus having the above-described configuration will be briefly described. Note that here, the operation by hardware will be explained.

FIG. 5 is a flowchart illustrating the transmission operation of this embodiment.

First, image data is input from the input terminal 101 (step 510), and is divided into 4×4 pixel sets (step 511). Then, this one block is transferred to the data delay unit 105.
and latches it (step 512). Further, the corresponding block is detected by the maximum value detection unit 103 and the minimum value detection unit 10.
4, and the maximum value and minimum value are detected in each part (step 513). Next, the division value conversion unit 106 calculates the division interval width St, and divides this interval into 2n+1 intervals.Step 5
15) In the VQ 107, determine which section of the sections obtained in step S15 each sample in the corresponding block belongs to, and calculate the normalization code C of each corresponding section.
o-Cz" (step 516). Furthermore, based on the 16 samples normalized in step S16, the corresponding block is expressed as 8-bit vector quantized data (step 517). This vector quantized data For expression purposes, it is expressed as a VQ code.

Then, the maximum value data from the maximum value detection section 103, the minimum value data from the minimum value detection section 104, and the VQ code are P/S converted by each P/S conversion section (step 318), and further timing control is performed. By switching the terminals of the unit 114, the synchronization adding unit 112 forms transmission data corresponding to the corresponding block as shown in FIG. step 520).

Next, the reception method of this embodiment will be explained.

FIG. 6 is a schematic block diagram showing the configuration of the receiving side of the image data transmission apparatus according to this embodiment.

In FIG. 6, 201 is an input terminal for inputting received data in the form of transmission data formed by the above-mentioned transmission processing, and the received data from this input terminal 201 is processed into a synchronizing signal by a synchronizing signal separation unit 211, which will be described later. Extracted. 20
Reference numeral 2 denotes a switching unit that switches the received data inputted at the input terminal 201 between the a° terminal and the b′ terminal and outputs the same. here,
The switching unit 202 outputs maximum value and minimum value data to the a° terminal.
The distribution is output to the vector quantized data terminal. Further, 203 and 204 are serial-parallel (hereinafter referred to as rS/PJ) conversion units that convert serial data input in serial to 8-bit parallel data and output the same. 205 is a maximum value latch circuit that latches the maximum value data supplied from the S/P converter 203; 206 is an S
A minimum value latch circuit that latches the minimum value data supplied from the /P converter 203, and a maximum value latch circuit 20.
5 and the minimum value latch circuit 206 both have the function of holding data until the maximum value or minimum value data of the next block is input.

Further, 207 is an inverse vector quantization unit (hereinafter referred to as "-") which restores normalized codes for 16 samples based on vector quantized 8-bit data. 20
Reference numeral 8 denotes a division inverse transformation unit that performs processing opposite to that of the division transformation unit 106 described above, and this division inverse transformation unit 208 takes in the maximum value and minimum value in block units, and calculates the division interval width St by (m
ax-min) /2n (n is the above-mentioned division value conversion unit 1
As shown in FIG. 5, the representative value Li (0≦i≦n) of each divided area is calculated by min.
, min+st, min+23t, ...mi
It is set to be the median value of each section, such as n+(2n-1)St, max, and the normalized code of each sample supplied from the TTE 207 is decoded into the representative value of the corresponding section. At this time, the calculation of the divided section width St is realized only by the subtraction circuit and the pit shift circuit, and as described above, the configuration is a digital circuit.

Further, 209 is the block dividing unit 102 shown in FIG.
A rask transformer 210 performs the inverse transformation of the processing and converts it into a rask signal. A rask transformer 210 is an output terminal that outputs the rask signal supplied from the rask transformer 209 to the outside. and 412
is the synchronization signal 5Y from the received data supplied from the input terminal.
413 is a synchronization separation unit 41 that separates the NC.
This is a timing control section that generates timing control signals for each section based on the synchronization signal 5YNC supplied from 2.

Here, the operation of the receiving side of the image data transmission apparatus having the above-described configuration will be briefly described. Note that here, the operation by hardware will be explained.

FIG. 7 is a flowchart illustrating the reception operation of this embodiment.

First, when the transmission data configured as shown in FIG. 3(b) described above is input to the input terminal 201 (step 530),
A synchronizing signal 5YNC is separated from this received data (step 531). This synchronization signal 5YNC is sent to the timing control section 212, and the timing control section 212 switches the switching section 202 based on the synchronization signal 5YNC.
control switching. With this switching control, each data of the maximum value and minimum value in the received data is sent to S through the a° terminal.
/P conversion, and the maximum value is sent to the maximum value latch 205.
The minimum value is latched by the minimum value latch 206 (
Step S32, Step 533).

In addition, in the case of VQ code data, S/P conversion is performed in the S/P conversion unit 204 via the b° terminal, and the batch vector quantized data, which becomes parallel data at T1, is
Convert to normalized code for samples (step S34
, step 535). Next, the divided section width St is determined (step 836), and within this divided section width St, the representative value of each section is set to 1 (step 537). Then, each representative value Ll is decoded by associating it with the normalization code obtained in step S35, and the 16 samples in this decoded block are deblocked by the raster conversion unit 209 and converted again into four raster signals. (Step S38,
step 539). Next, the image data based on the raster signal converted in step S39 is output to the outside (step 540).

As described above, according to this embodiment, in a highly versatile vector quantization method using normalized data, it is easy to perform calculations during normalization using a digital circuit, and the LS
It is possible to realize an encoding method that is advantageous for I conversion and the like. Furthermore, since the step size divided during normalization is smaller than in the conventional method, it is possible to reduce errors caused by normalization, and it is also possible to improve the image quality of reproduced images.

Next, as a modification of this embodiment, a method for reducing the amount of hardware when configuring VQ using a ROM table will be described.

First, the VQ of this embodiment may use any algorithm such as a search type as long as it can handle human-powered vectors each having the number of states of 2n◆1 (n is the value in the above-mentioned division value conversion unit 106). , compared to the conventional method using 2'' types of normalization codes, the number of states for each input vector increases by at most 1. However, for the purpose of realizing high-speed processing, etc., the VQ is configured with a ROM table. In this case, the output of the division value converter becomes a 2n+1 bit signal representing n+1 normalized data, so the ROM capacity doubles per dimension for the addition of at most one state. Using a vector quantization table (
A ROM with a capacity of 2n41)K x M bits (M is the number of bits after vector quantization) is required. However, the required data within this ROM capacity is (2n+1)"
Since it is M bits, it is possible to reduce the capacity of the ROM depending on the configuration of the VQ.

FIG. 8 is a schematic block diagram showing the configuration of a VQ that performs two-dimensional vector quantization (k=2) according to a modification of this embodiment. The configuration of this embodiment other than VQ is the same as that of the previous embodiment, and among the 4×4 samples subjected to normalization processing, two normalization codes with high correlation are each subjected to two-dimensional vector quantization. shall be In the figure, 301
, 302 is an n+1 bit signal 2 representing a normalized code.
This input terminal 301, 3
02 has a function of performing appropriate delay processing so that the outputs of the division value converting section 106 in the above-described embodiment can be input in parallel two by two in a predetermined combination.

Here, when the upper one bit of the input signals from the input terminals 301 and 302 is "1", the normalized code C2n-1 is indicated regardless of the value of the lower bit. 303 is input terminal 3
A VQ-ROM that outputs an M-bit code corresponding to each input signal when both input signals supplied from 01.302 have normalized codes 00 to C0-3,
This (DVQ ROM3O3 has a capacity of 2''XM bits.

Further, 304 and 305 are extended VQ-ROMs each having a capacity of 2nXM bits in accordance with the lower n bits of the other input signal when one of the input signals from the input terminals 301 and 302 is Can. 306 is the input terminal 301,
This corresponds to the case where both input signals from 302 are Can, and the extended VQ-RO consists of an M-bit memory with a fixed output.
It is M. 307 outputs the VQ-ROM 303 . Expansion VQ-ROM30
This is a VQ-ROM selection section that selects outputs from 4 to 306 and outputs an M-bit code. Further, 308 is an output terminal for outputting the M-bit code supplied from the VQ-ROM selection section 3o7 to a P/S conversion section (not shown) similar to the previous embodiment.

According to the above explanation, according to the modification of this embodiment, the required R
OM (7) capacity is VQ-ROM303 and extended VQ-R
OM304, 305, 306 total (2”+2X 2n
÷1)×M bits, which can be realized with the minimum necessary capacity. In this way, even when low-dimensional vector quantization is implemented using a ROM to speed up calculations, it can be implemented without adding a large amount of capacity.

Note that although the modification of this embodiment has been explained using an example of two-dimensional vector quantization, the present invention is not limited to this, and the ROM is constructed in the form of expanding (2n+1)K,
A ROM can be selected based on a combination of the most significant bit of each input signal, and a configuration using a minimum number of ROMs can be achieved.

[Effects of the Invention] As described above, according to the present invention, it is possible to improve the speed and efficiency of calculations by digital circuits, and to provide high quality images.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing the configuration of the transmitting side of the image data transmission device according to this embodiment, FIG. 2 is a diagram explaining the block division method according to this embodiment, and FIGS. 3(a) and (b) are FIG. 4 is a diagram illustrating the method of dividing sections within a block according to this embodiment. FIG. 5 is a flowchart explaining the transmission operation of this embodiment. A schematic block diagram showing the configuration of the receiving side of the image data transmission device according to the example, FIG. 7 is a flowchart explaining the receiving operation of the present example, and FIG. 8 is a two-dimensional vector conversion according to a modification of the present example ( FIG. 9 is a schematic block diagram showing the configuration of a VQ that performs (k=2). FIG. 9 is a diagram illustrating a conventional block division method. In the figure, 101, 201, 301, 302...input terminal, 102...block division section, 103...maximum value detection section, 104...minimum value detection section, 105...data delay section, 106... Division value conversion unit, 107・VQ, 108 to 110・P/S conversion unit, 11
1.202...Switching section, 112...Synchronization addition section, 1
13.210.308...Output terminal, 114,212
...Timing control section, 203.204...
・S/P change 11.205...Maximum value latch 1.206
River minimum value latch, 207...VQ, 208... Division value inverse conversion unit, 20
9... Rask conversion unit, 211... Synchronization separation unit, 30
3.VQ-ROM, 304-306...Expansion ■Q-R
This is an OM, 307/VQ-ROM selection section.

Claims (2)

[Claims] (1) Normalize image data in units of blocks of pixel data of a predetermined amount, vector quantize a plurality of pieces of normalized data at once, and set the maximum value of pixel data in the block as normalization information in the vector quantized data, Minimum value, (maximum value −
an image data transmission device that adds and transmits at least two of the minimum value), the step of calculating the quantization step width in one block using the arithmetic expression of (maximum value - minimum value) ÷ 2^n; width calculating means; dividing means for dividing the area between the maximum value and the minimum value into 2^n+1 sections based on a substantially central value of the quantization step width; ^n+
Image data characterized by comprising: normalization means for expressing normalized data of an interval to which one interval belongs; and vector quantization means for collectively vector quantizing a plurality of the normalized data in a block. Transmission device. (2) The image data transmission device according to claim 1, wherein the arithmetic expression includes a subtraction operation and a shift operation.