JPH0289288A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To facilitate the selective setting or clearing of memory cell contents by dividing an ordinary read/write operation and the setting operation or the clearing operation of the memory cell contents with a word line and a bit line pair for a first port and the word line and the bit line pair for a second port. CONSTITUTION:The title device is constituted so that a word line WL1 and a bit line pair BL1 for the first port may be used at the time of the ordinary read/write for dual port memory cells C11-Cnm and a setting signal or a clearing signal may be impressed on a word line WL2 for the second port at the time of setting or clearing the memory cell contents. Thus, without the decrease of an access speed and the necessity of a complicated control circuit, the setting or the clearing of the memory cell contents can be collectively executed to all of the prescribed memory cell or selectively to a part of the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a function of setting or clearing the contents of a memory cell that holds a valid bit flag, for example. .

(Prior Art) Conventionally, when providing a semiconductor memory with a function to clear the contents of some memory cells, a static single-port memory cell SM as shown in FIG. The memory brain was configured as shown in the figure. Here, Vcc is the power supply potential, VSS is the ground potential, and BL
and BL are bit line pairs, WL1 to WLn are word lines,
RD is a row decoder, CL is a clear signal line, ORI~O
Rn is an OR gate, 81 is a bit line load circuit, and 82 is a sense amplifier/write circuit.

In the memory clearing operation, as shown in FIG. 10, the desired memory cell SM is selected by ORing the row decoder output, which is a word line drive signal necessary for normal memory cell access, and the clear signal. Activate and then
Bit line pair BL, BL connected to memory cell SM
is controlled to the "0" write (clear) level, and the internal node pair NSN of the selected memory cell SM is written to the "0" state.

However, the above-mentioned memory has a problem in that the access speed deteriorates because the OR gates OR1 to ORn for redundant or rear functions are inserted in the memory access path where high speed is required. Also,
Since it is necessary to control the potential of the bit line pair BL, BL during the clearing operation, there is also the problem that the control circuit becomes complicated.

(Problems to be Solved by the Invention) As described above, the gate for the clear function is inserted into the memory access path that requires high speed, so the access speed deteriorates. This was developed to solve the problem that the control circuit becomes complicated because it is necessary to control the potential of the bit line pair during operation. It is an object of the present invention to provide a semiconductor memory having a function of setting or clearing the contents of memory cells in all or part of predetermined memory cells at once or selectively.

[Structure of the Invention (Means for Solving the Problems)] The semiconductor memory of the present invention uses a static dual-port memory cell for at least a portion of the memory cells, and the dual-port memory cell has a first port. The word line and bit line pair and the word line and bit line pair for the second port are connected, and in the bit line pair for the second port, one bit line is connected to the power source 7u, and the other bit line is grounded. potential, and during normal read/write to the dual-port memory cell, the first
A word line and a bit line pair for the port are used, and a set signal or a clear signal is applied to the word line for the second port when setting or clearing the contents of the memory cell. do.

(Function) A normal read/write operation for a dual-port memory cell and a setting or clearing operation of memory cell contents are carried out between the word line and bit line pair for the first port and the word line and bit line pair for the second port. The dual-port memory cell contents can be set or cleared selectively in all or part of the dual-port memory cells without adversely affecting normal read/write operations. It becomes easier to do.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of a static type RAM (random access memory), and C11 to Cnm are static type dual port memory cells. These dual-port memory cells C1l to Cnm each have a flip-flop (two high resistances R1 and R2 for load and two cross-connected drive A FF consisting of N-type MOS transistors N1 and N2 is connected between the Vcc power supply and the ground terminal, and a pair of input/output nodes (N
.
One end of each of the second N-type MO5) transistor pair (T3, T4) for the transfer gate is connected to.

Each gate and each other end of the first N-type MOS transistor pair (TI, T2) are connected to a word line WLI and a bit line pair (BLI, BLI) for the first port, respectively. Second N-type MOS transistor pair (T3, T4
) are respectively connected to word line WL2 and bit line pair (BL2, BL2) for the second port. Therefore, it is possible to independently perform a read/write operation using the first port and a read/write operation using the second port for the dual port memory cells C1l to Cnm. and,
One bit line of the bit line pair (BL2, BL2) for the second port is connected to the power supply potential Vcc, and the other bit line is connected to the ground potential Vss.

Here, in the memory cells C11 to Cnm, the -pair of human output nodes, that is, the pair of internal nodes (N, N) correspond to each other (high level, low level) state is "1" state (set state), and the opposite state is the "0" state (clear state). In this example, the clearing operation is performed by the second port, and as shown in Figure 3,
A second N-type MO for the transfer gate is connected to the internal node N which becomes high level when the content of the memory cell is in the “1” state.
Bit line B connected via S transistor T3
L2 is connected to the VSS potential, and the internal node N becomes low level when the content of the memory cell is in the above “1” state.
The bit line BL2 connected to VCC via the second N-type MOS transistor T4 for transfer gate
connected to electrical potential.

Note that instead of the two high resistances R1 and R2 for loading in the dual-port memory cells C1l to Cnm shown in FIG. 2(a), a cross-connected load is used as shown in FIG. 2(b). Alternatively, two P-type MOS transistors P1 and R2 may be used.

In FIG. 1, memory cells C1l to Cnm are arranged in n rows×m
As shown in FIG. 3, the word lines WLI for the first ports of memory cells in the same row are commonly connected to the row decoder RD, and the word lines WLI for the first ports of the memory cells in the same row are connected in common to the row decoder RD. A clear signal line CL is commonly connected to the two-port word line WL2. Furthermore, the bit line pair (BLI, BLI) for the first port of the memory cells in the same column has a common bit line load circuit 11 and a sense amplifier.
A write circuit 12 is connected. A collective clear signal is applied to the clear signal line CL.

Next, the access operation for the dual port memory cells C11 to Cnm in the above memory will be explained. Normal read/write operations and memory cell content clear operations for dual-port memory cells C1l to Cnm are performed using the word line WL1 and bit line pair (BLI, BLI) for the first port and the word line for the second port. WL2
and bit line pair (BL2, BL2). That is, during normal read/write operations, word lines in a specific row are directly selected and driven by the row decoder output, so high-speed read/write is possible as in a normal memory.

Also, when clearing the contents of memory cells, bulk write (
In this example, the bulk clear signal is activated (in this example, the “1” level) when the request signal is generated, and each memory cell C
Since it is commonly given to 1l to Cnm, each memory cell C
1l~Cnm are the second N! for transfer gates, respectively. The 42M0S transistor T3 is turned on, and the internal node N becomes V ss? via the second N-type MOS transistor T3 and the bit line BL2. It is connected to the ls position and cleared. Therefore, it is possible to easily clear the memory cell contents of all dual port memory cells C11 to Cnm at once without adversely affecting normal read/write operations.

Note that the pattern area of dual-port Φ memory cells C11 to Cnm is approximately 2 compared to single-port memory cells.
Since it is twice as large, dual-port memory cell C1l
~The chip area of memory using Cnm increases. However, when providing a clear function using a single-port memory cell SM as in the conventional example, an OR game that takes OR logic between the row decoder output and the clear signal
Since ORn is required, the memory chip area also increases.

Here, in a memory for holding a valid bit flag that requires a high clearing function, there are many configurations in which about 4 bits are connected to one word line, so the pattern area of this embodiment and the conventional example in this case is Compare. First, in this example, as shown in FIG. 4(a),
If four dual-port memory cells (for example, CIl to C14) are connected to one row, and the pattern area of one dual-port memory cell is expressed as 28, the pattern area required for one row is 8S. It is.

On the other hand, in the conventional example, as shown in FIG. 4(b), one OR gate OR and four single-port memory cells SM are connected to one row. In order to realize this OR gate, normally 8 times the pattern area S of one single port memory cell SM is required, and the pattern area required for one row is 8S+4S-1.
Becomes 2S. That is, in this embodiment, the pattern area can be smaller than in the conventional example.

Note that when performing a data set operation on the dual-port memory cells C1l to Cnm using the second port, a transfer gate signal is connected to the internal node N, which becomes high level when the content of the memory cell is in the "1" state. The bit line BL2 connected via the second N-type MO3) transistor T3 is connected to the cc potential, and the transfer gate is connected to the internal node N which becomes low level when the content of the memory cell is in the above "1" state. second N-type MOS transistor T for
The bit line BL2, which is connected through 4, may be connected to the VSS potential, and the data set signal may be used instead of the batch clear signal.

In the above embodiment, dual port memory cells C11 to
Although all of the dual port memory cells C1l to Cnm are cleared at once, if you want to clear the memory cell contents of all of the dual port memory cells C1l to Cnm at once or selectively for a part, for example, as shown in FIG. Just make the changes as shown in.

That is, compared to the memory shown in FIG. 1, the memory shown in FIG. 5 has content addressable memory cells I M 1 to l M n in each row.
One OR gate ORI to ORn is provided for each row, and each row of OR gates ORI to ORn has a corresponding content addressable memory cell IM.
A search match signal and a batch clear signal generated when the contents of I to I M n match the search signal are input,
The difference is that the OR output serves as the clear signal input for the dual-port memory cell in the corresponding row.

Note that as the number of rows in the memory cell array increases with the increase in memory capacity, the number of dual-port memory cells connected to the same column increases. Therefore, during bulk clearing, the peak current flowing from the VccfK source to each dual-port memory cell via the bit line BL2 in the same column increases, causing the bit line BL2 (usually an aluminum wiring) to become disconnected due to electronic migration. It is possible that this could happen. In order to avoid this, as shown in FIG. 6, a P-type MO3h transistor TP whose gate is grounded may be inserted between the Vcc power supply and the bit line BL2 to limit the peak current value. In this case, the clearing time increases slightly due to the insertion of the MOS transistor TP, but there is no problem since high-speed clearing operations are generally not required.

In addition, in each of the above embodiments, all of the memory cells are dual-port memory cells, but as shown in FIG. 7, for example, as shown in FIG. By using the dual port memory cell C1 only as a memory cell, it is possible to perform bulk clearing or selective rearranging as described above. here,
WLl is a word line, SM, . . . are single-port memory cells, (BLSBL) is a bit line pair connected to the single-port memory cells, and CL is a clear signal line.

[Effects of the Invention] As described above, according to the present invention, the access speed can be improved without deteriorating the access speed, and without requiring a complicated control circuit.
It is possible to realize a semiconductor memory having a function of setting or clearing memory cell contents in all or part of a predetermined memory cell at once or selectively.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the semiconductor memory of the present invention, FIG. 2(a) is a circuit diagram showing an example of the dual-port memory cell in FIG. 1, and FIG. Figure (a)
Schematic diagram showing a variant of the dual-port fist memory cell,
FIG. 3 is a circuit diagram showing one row of the memory cell array in FIG. 1, and FIGS. 4(a) and (b) are circuit diagrams showing one row of the memory cell array. A circuit diagram showing one row of memory cell arrays in the memory shown in the figure and a conventional memory; FIG. 5 is a configuration explanatory diagram showing another embodiment of the semiconductor memory of the present invention;
FIG. 6 is a circuit diagram showing one row of memory cell arrays in the memories of FIGS. 1 and 5, FIG. 7 is a configuration explanatory diagram showing still another embodiment of the semiconductor memory of the present invention, and FIG. 9 is a configuration explanatory diagram showing a conventional semiconductor memory with a clear function, FIG. 9 is a circuit diagram showing a single-port memory cell in FIG. 8, and FIG. 10 is a timing waveform diagram showing the operation of the memory in FIG. 8. It is. C11~Cnm5C1~Cn--Dual port memory cell, FF...Flip-flop, R1, R2-
...High resistance for load, N1, N2...N type M for drive
OS transistor, N, , N... Input/output node of flip-flop, T1, T2... First NTJ1MOS transistor pair for transfer gate, T3, T4...
...Second N-type MOS transistor pair for transfer gate, WLl..., word line for first port, BL
I, BLI...Bit line pair for the first port, WL2.
...Word line for the second port, BL2, BL2...Bit line pair for the second port, Pl, R2...P for the load
type MOS) transistor, RD...low decoder, CL
...Clear signal line, 11...Bit line load circuit, 1
2...Sense amplifier/write circuit, OR1~ORn/
. . . OR gate, IMI to IM n . . . content addressable memory cell, TP . . . P-type MO3) transistor for limiting peak current value. Volume 1 illustration

Claims (4)

[Claims] (1) A static dual-port memory cell is used for at least a portion of the memory cell, and the dual-port memory cell has a word line and bit line pair for the first port and a word line and bit line pair for the second port. are connected, and in the bit line pair for the second port, one bit line is connected to a power supply potential and the other bit line is connected to a ground potential, and during normal read/write to the dual port memory cell, A word line and a bit line pair for the first port are used, and a set signal or a clear signal is applied to the word line for the second port when setting or clearing the memory cell contents. Features of semiconductor memory. (2) A claim characterized in that there is a plurality of the static dual-port memory cells, and the set signal or clear signal is applied to all or part of the plurality of dual-port memory cells in common. The semiconductor memory according to item 1. (3) The set signal or clear signal commonly applied to all of the plurality of dual-port memory cells is activated when a batch write request signal is generated, and is applied to some of the plurality of dual-port memory cells. 3. The semiconductor memory according to claim 2, wherein the applied set signal or clear signal is applied when a search match signal is generated for an associative memory cell. (4) The one bit line of the bit line pair for the second port is connected to the power supply potential via a P-type MOS transistor whose gate is connected to the ground potential. The semiconductor memory according to claim 1.